1 /* 2 * Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #ifndef __XT_PERF_CONSTS_H__ 24 #define __XT_PERF_CONSTS_H__ 25 26 #include <xtensa/config/core.h> 27 28 /* 29 * Performance monitor counter selectors 30 */ 31 32 #define XTPERF_CNT_COMMITTED_INSN 0x8002 /* Instructions committed */ 33 #define XTPERF_CNT_BRANCH_PENALTY 0x8003 /* Branch penalty cycles */ 34 #define XTPERF_CNT_PIPELINE_INTERLOCKS 0x8004 /* Pipeline interlocks cycles */ 35 #define XTPERF_CNT_ICACHE_MISSES 0x8005 /* ICache misses penalty in cycles */ 36 #define XTPERF_CNT_DCACHE_MISSES 0x8006 /* DCache misses penalty in cycles */ 37 38 #define XTPERF_CNT_CYCLES 0 /* Count cycles */ 39 #define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */ 40 #define XTPERF_CNT_INSN 2 /* Successfully completed instructions */ 41 #define XTPERF_CNT_D_STALL 3 /* Data-related GlobalStall cycles */ 42 #define XTPERF_CNT_I_STALL 4 /* Instruction-related and other GlobalStall cycles */ 43 #define XTPERF_CNT_EXR 5 /* Exceptions and pipeline replays */ 44 #define XTPERF_CNT_BUBBLES 6 /* Hold and other bubble cycles */ 45 #define XTPERF_CNT_I_TLB 7 /* Instruction TLB Accesses (per instruction retiring) */ 46 #define XTPERF_CNT_I_MEM 8 /* Instruction memory accesses (per instruction retiring) */ 47 #define XTPERF_CNT_D_TLB 9 /* Data TLB accesses */ 48 #define XTPERF_CNT_D_LOAD_U1 10 /* Data memory load instruction (load-store unit 1) */ 49 #define XTPERF_CNT_D_STORE_U1 11 /* Data memory store instruction (load-store unit 1) */ 50 #define XTPERF_CNT_D_ACCESS_U1 12 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 1) */ 51 #define XTPERF_CNT_D_LOAD_U2 13 /* Data memory load instruction (load-store unit 2) */ 52 #define XTPERF_CNT_D_STORE_U2 14 /* Data memory store instruction (load-store unit 2) */ 53 #define XTPERF_CNT_D_ACCESS_U2 15 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 2) */ 54 #define XTPERF_CNT_D_LOAD_U3 16 /* Data memory load instruction (load-store unit 3) */ 55 #define XTPERF_CNT_D_STORE_U3 17 /* Data memory store instruction (load-store unit 3) */ 56 #define XTPERF_CNT_D_ACCESS_U3 18 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 3) */ 57 #define XTPERF_CNT_MULTIPLE_LS 22 /* Multiple Load/Store */ 58 #define XTPERF_CNT_OUTBOUND_PIF 23 /* Outbound PIF transactions */ 59 #define XTPERF_CNT_INBOUND_PIF 24 /* Inbound PIF transactions */ 60 #define XTPERF_CNT_PREFETCH 26 /* Prefetch events */ 61 62 #if XCHAL_HW_VERSION >= 270004 63 64 #define XTPERF_CNT_IDMA 27 /* iDMA counters */ 65 #define XTPERF_CNT_INSN_LENGTH 28 /* Instruction length counters */ 66 67 #endif /* HW version >= 270004 */ 68 69 /* 70 * Masks for each of the selector listed above 71 */ 72 73 /* XTPERF_CNT_COMMITTED_INSN selector mask */ 74 75 #define XTPERF_MASK_COMMITTED_INSN 0x0001 76 77 /* XTPERF_CNT_BRANCH_PENALTY selector mask */ 78 79 #define XTPERF_MASK_BRANCH_PENALTY 0x0001 80 81 /* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */ 82 83 #define XTPERF_MASK_PIPELINE_INTERLOCKS 0x0001 84 85 /* XTPERF_CNT_ICACHE_MISSES selector mask */ 86 87 #define XTPERF_MASK_ICACHE_MISSES 0x0001 88 89 /* XTPERF_CNT_DCACHE_MISSES selector mask */ 90 91 #define XTPERF_MASK_DCACHE_MISSES 0x0001 92 93 /* XTPERF_CNT_CYCLES selector mask */ 94 95 #define XTPERF_MASK_CYCLES 0x0001 96 97 /* XTPERF_CNT_OVERFLOW selector mask */ 98 99 #define XTPERF_MASK_OVERFLOW 0x0001 100 101 /* 102 * XTPERF_CNT_INSN selector mask 103 */ 104 105 #define XTPERF_MASK_INSN_ALL 0x8DFF 106 107 #define XTPERF_MASK_INSN_JX 0x0001 /* JX */ 108 #define XTPERF_MASK_INSN_CALLX 0x0002 /* CALLXn */ 109 #define XTPERF_MASK_INSN_RET 0x0004 /* call return i.e. RET, RETW */ 110 #define XTPERF_MASK_INSN_RF 0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */ 111 #define XTPERF_MASK_INSN_BRANCH_TAKEN 0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */ 112 #define XTPERF_MASK_INSN_J 0x0020 /* J */ 113 #define XTPERF_MASK_INSN_CALL 0x0040 /* CALLn */ 114 #define XTPERF_MASK_INSN_BRANCH_NOT_TAKEN 0x0080 /* Conditional branch fall through (aka. not-taken branch) */ 115 #define XTPERF_MASK_INSN_LOOP_TAKEN 0x0100 /* Loop instr falls into loop (aka. taken loop) */ 116 #define XTPERF_MASK_INSN_LOOP_BEG 0x0400 /* Loopback taken to LBEG */ 117 #define XTPERF_MASK_INSN_LOOP_END 0x0800 /* Loopback falls through to LEND */ 118 #define XTPERF_MASK_INSN_NON_BRANCH 0x8000 /* Non-branch instruction (aka. non-CTI) */ 119 120 /* 121 * XTPERF_CNT_D_STALL selector mask 122 */ 123 124 #define XTPERF_MASK_D_STALL_ALL 0x01FE 125 126 #define XTPERF_MASK_D_STALL_STORE_BUF_FULL 0x0002 /* Store buffer full stall */ 127 #define XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT 0x0004 /* Store buffer conflict stall */ 128 #define XTPERF_MASK_D_STALL_CACHE_MISS 0x0008 /* DCache-miss stall */ 129 #define XTPERF_MASK_D_STALL_BUSY 0x0010 /* Data RAM/ROM/XLMI busy stall */ 130 #define XTPERF_MASK_D_STALL_IN_PIF 0x0020 /* Data inbound-PIF request stall (incl s32c1i) */ 131 #define XTPERF_MASK_D_STALL_MHT_LOOKUP 0x0040 /* MHT lookup stall */ 132 #define XTPERF_MASK_D_STALL_UNCACHED_LOAD 0x0080 /* Uncached load stall (included in MHT lookup stall) */ 133 #define XTPERF_MASK_D_STALL_BANK_CONFLICT 0x0100 /* Bank-conflict stall */ 134 135 /* 136 * XTPERF_CNT_I_STALL selector mask 137 */ 138 139 #define XTPERF_MASK_I_STALL_ALL 0x01FF 140 141 #define XTPERF_MASK_I_STALL_CACHE_MISS 0x0001 /* ICache-miss stall */ 142 #define XTPERF_MASK_I_STALL_BUSY 0x0002 /* Instruction RAM/ROM busy stall */ 143 #define XTPERF_MASK_I_STALL_IN_PIF 0x0004 /* Instruction RAM inbound-PIF request stall */ 144 #define XTPERF_MASK_I_STALL_TIE_PORT 0x0008 /* TIE port stall */ 145 #define XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL 0x0010 /* External RunStall signal status */ 146 #define XTPERF_MASK_I_STALL_UNCACHED_FETCH 0x0020 /* Uncached fetch stall */ 147 #define XTPERF_MASK_I_STALL_FAST_L32R 0x0040 /* FastL32R stall */ 148 #define XTPERF_MASK_I_STALL_ITERATIVE_MUL 0x0080 /* Iterative multiply stall */ 149 #define XTPERF_MASK_I_STALL_ITERATIVE_DIV 0x0100 /* Iterative divide stall */ 150 151 /* 152 * XTPERF_CNT_EXR selector mask 153 */ 154 155 #define XTPERF_MASK_EXR_ALL 0x01FF 156 157 #define XTPERF_MASK_EXR_REPLAYS 0x0001 /* Other Pipeline Replay (i.e. excludes $ miss etc.) */ 158 #define XTPERF_MASK_EXR_LEVEL1_INT 0x0002 /* Level-1 interrupt */ 159 #define XTPERF_MASK_EXR_LEVELH_INT 0x0004 /* Greater-than-level-1 interrupt */ 160 #define XTPERF_MASK_EXR_DEBUG 0x0008 /* Debug exception */ 161 #define XTPERF_MASK_EXR_NMI 0x0010 /* NMI */ 162 #define XTPERF_MASK_EXR_WINDOW 0x0020 /* Window exception */ 163 #define XTPERF_MASK_EXR_ALLOCA 0x0040 /* Alloca exception */ 164 #define XTPERF_MASK_EXR_OTHER 0x0080 /* Other exceptions */ 165 #define XTPERF_MASK_EXR_MEM_ERR 0x0100 /* HW-corrected memory error */ 166 167 /* 168 * XTPERF_CNT_BUBBLES selector mask 169 */ 170 171 #define XTPERF_MASK_BUBBLES_ALL 0x01FD 172 173 #define XTPERF_MASK_BUBBLES_PSO 0x0001 /* Processor domain PSO bubble */ 174 #define XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS 0x0004 /* R hold caused by DCache miss */ 175 #define XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE 0x0008 /* R hold caused by Store release */ 176 #define XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP 0x0010 /* R hold caused by register dependency */ 177 #define XTPERF_MASK_BUBBLES_R_HOLD_WAIT 0x0020 /* R hold caused by MEMW, EXTW or EXCW */ 178 #define XTPERF_MASK_BUBBLES_R_HOLD_HALT 0x0040 /* R hold caused by Halt instruction (TX only) */ 179 #define XTPERF_MASK_BUBBLES_CTI 0x0080 /* CTI bubble (e.g. branch delay slot) */ 180 #define XTPERF_MASK_BUBBLES_WAITI 0x0100 /* WAITI bubble */ 181 182 /* 183 * XTPERF_CNT_I_TLB selector mask 184 */ 185 186 #define XTPERF_MASK_I_TLB_ALL 0x000F 187 188 #define XTPERF_MASK_I_TLB_HITS 0x0001 /* Hit */ 189 #define XTPERF_MASK_I_TLB_REPLAYS 0x0002 /* Replay of instruction due to ITLB miss */ 190 #define XTPERF_MASK_I_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */ 191 #define XTPERF_MASK_I_TLB_MISSES 0x0008 /* ITLB Miss Exception */ 192 193 /* 194 * XTPERF_CNT_I_MEM selector mask 195 */ 196 197 #define XTPERF_MASK_I_MEM_ALL 0x000F 198 199 #define XTPERF_MASK_I_MEM_CACHE_HITS 0x0001 /* ICache Hit */ 200 #define XTPERF_MASK_I_MEM_CACHE_MISSES 0x0002 /* ICache Miss (includes uncached) */ 201 #define XTPERF_MASK_I_MEM_IRAM 0x0004 /* InstRAM or InstROM */ 202 #define XTPERF_MASK_I_MEM_BYPASS 0x0008 /* Bypass (i.e. uncached) fetch */ 203 204 /* 205 * XTPERF_CNT_D_TLB selector mask 206 */ 207 208 #define XTPERF_MASK_D_TLB_ALL 0x000F 209 210 #define XTPERF_MASK_D_TLB_HITS 0x0001 /* Hit */ 211 #define XTPERF_MASK_D_TLB_REPLAYS 0x0002 /* Replay of instruction due to DTLB miss */ 212 #define XTPERF_MASK_D_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */ 213 #define XTPERF_MASK_D_TLB_MISSES 0x0008 /* DTLB Miss Exception */ 214 215 /* 216 * XTPERF_CNT_D_LOAD_U* selector mask 217 */ 218 219 #define XTPERF_MASK_D_LOAD_ALL 0x000F 220 221 #define XTPERF_MASK_D_LOAD_CACHE_HITS 0x0001 /* Cache Hit */ 222 #define XTPERF_MASK_D_LOAD_CACHE_MISSES 0x0002 /* Cache Miss */ 223 #define XTPERF_MASK_D_LOAD_LOCAL_MEM 0x0004 /* Local memory hit */ 224 #define XTPERF_MASK_D_LOAD_BYPASS 0x0008 /* Bypass (i.e. uncached) load */ 225 226 /* 227 * XTPERF_CNT_D_STORE_U* selector mask 228 */ 229 230 #define XTPERF_MASK_D_STORE_ALL 0x000F 231 232 #define XTPERF_MASK_D_STORE_CACHE_HITS 0x0001 /* DCache Hit */ 233 #define XTPERF_MASK_D_STORE_CACHE_MISSES 0x0002 /* DCache Miss */ 234 #define XTPERF_MASK_D_STORE_LOCAL_MEM 0x0004 /* Local memory hit */ 235 #define XTPERF_MASK_D_STORE_PIF 0x0008 /* PIF Store */ 236 237 /* 238 * XTPERF_CNT_D_ACCESS_U* selector mask 239 */ 240 241 #define XTPERF_MASK_D_ACCESS_ALL 0x000F 242 243 #define XTPERF_MASK_D_ACCESS_CACHE_MISSES 0x0001 /* DCache Miss */ 244 #define XTPERF_MASK_D_ACCESS_HITS_SHARED 0x0002 /* Hit Shared */ 245 #define XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE 0x0004 /* Hit Exclusive */ 246 #define XTPERF_MASK_D_ACCESS_HITS_MODIFIED 0x0008 /* Hit Modified */ 247 248 /* 249 * XTPERF_CNT_MULTIPLE_LS selector mask 250 */ 251 252 #define XTPERF_MASK_MULTIPLE_LS_ALL 0x003F 253 254 #define XTPERF_MASK_MULTIPLE_LS_0S_0L 0x0001 /* 0 stores and 0 loads */ 255 #define XTPERF_MASK_MULTIPLE_LS_0S_1L 0x0002 /* 0 stores and 1 loads */ 256 #define XTPERF_MASK_MULTIPLE_LS_1S_0L 0x0004 /* 1 stores and 0 loads */ 257 #define XTPERF_MASK_MULTIPLE_LS_1S_1L 0x0008 /* 1 stores and 1 loads */ 258 #define XTPERF_MASK_MULTIPLE_LS_0S_2L 0x0010 /* 0 stores and 2 loads */ 259 #define XTPERF_MASK_MULTIPLE_LS_2S_0L 0x0020 /* 2 stores and 0 loads */ 260 261 /* 262 * XTPERF_CNT_OUTBOUND_PIF selector mask 263 */ 264 265 #define XTPERF_MASK_OUTBOUND_PIF_ALL 0x0003 266 267 #define XTPERF_MASK_OUTBOUND_PIF_CASTOUT 0x0001 /* Castout */ 268 #define XTPERF_MASK_OUTBOUND_PIF_PREFETCH 0x0002 /* Prefetch */ 269 270 /* 271 * XTPERF_CNT_INBOUND_PIF selector mask 272 */ 273 274 #define XTPERF_MASK_INBOUND_PIF_ALL 0x0003 275 276 #define XTPERF_MASK_INBOUND_PIF_I_DMA 0x0001 /* Instruction DMA */ 277 #define XTPERF_MASK_INBOUND_PIF_D_DMA 0x0002 /* Data DMA */ 278 279 /* 280 * XTPERF_CNT_PREFETCH selector mask 281 */ 282 283 #define XTPERF_MASK_PREFETCH_ALL 0x002F 284 285 #define XTPERF_MASK_PREFETCH_I_HIT 0x0001 /* I prefetch-buffer-lookup hit */ 286 #define XTPERF_MASK_PREFETCH_D_HIT 0x0002 /* D prefetch-buffer-lookup hit */ 287 #define XTPERF_MASK_PREFETCH_I_MISS 0x0004 /* I prefetch-buffer-lookup miss */ 288 #define XTPERF_MASK_PREFETCH_D_MISS 0x0008 /* D prefetch-buffer-lookup miss */ 289 #define XTPERF_MASK_PREFETCH_D_L1_FILL 0x0020 /* Fill directly to DCache L1 */ 290 291 #if XCHAL_HW_VERSION >= 270004 292 293 /* 294 * XTPERF_CNT_IDMA selector mask 295 */ 296 297 #define XTPERF_MASK_IDMA_ALL 0x0001 298 299 #define XTPERF_MASK_IDMA_ACTIVE_CYCLES 0x0001 /* Active Cycles */ 300 301 /* 302 * XTPERF_CNT_INSN_LENGTH selector mask 303 */ 304 305 #define XTPERF_MASK_INSN_LENGTH_ALL 0x7FFF 306 307 #define XTPERF_MASK_INSN_LENGTH_16 0x0001 /* 16-bit instruction length */ 308 #define XTPERF_MASK_INSN_LENGTH_24 0x0002 /* 24-bit instruction length */ 309 #define XTPERF_MASK_INSN_LENGTH_32 0x0004 /* 32-bit instruction length */ 310 #define XTPERF_MASK_INSN_LENGTH_40 0x0008 /* 40-bit instruction length */ 311 #define XTPERF_MASK_INSN_LENGTH_48 0x0010 /* 48-bit instruction length */ 312 #define XTPERF_MASK_INSN_LENGTH_56 0x0020 /* 56-bit instruction length */ 313 #define XTPERF_MASK_INSN_LENGTH_64 0x0040 /* 64-bit instruction length */ 314 #define XTPERF_MASK_INSN_LENGTH_72 0x0080 /* 72-bit instruction length */ 315 #define XTPERF_MASK_INSN_LENGTH_80 0x0100 /* 80-bit instruction length */ 316 #define XTPERF_MASK_INSN_LENGTH_88 0x0200 /* 88-bit instruction length */ 317 #define XTPERF_MASK_INSN_LENGTH_96 0x0400 /* 96-bit instruction length */ 318 #define XTPERF_MASK_INSN_LENGTH_104 0x0800 /* 104-bit instruction length */ 319 #define XTPERF_MASK_INSN_LENGTH_112 0x1000 /* 112-bit instruction length */ 320 #define XTPERF_MASK_INSN_LENGTH_120 0x2000 /* 120-bit instruction length */ 321 #define XTPERF_MASK_INSN_LENGTH_128 0x4000 /* 128-bit instruction length */ 322 323 #endif /* HW version >= 270004 */ 324 325 #endif /* __XT_PERF_CONSTS_H__ */ 326
