1 /* 2 xtensa/hal.h -- contains a definition of the Core HAL interface 3 4 All definitions in this header file are independent of any specific 5 Xtensa processor configuration. Thus software (eg. OS, application, 6 etc) can include this header file and be compiled into configuration- 7 independent objects that can be distributed and eventually linked 8 to the HAL library (libhal.a) to create a configuration-specific 9 final executable. 10 11 Certain definitions, however, are release/version-specific -- such as 12 the XTHAL_RELEASE_xxx macros (or additions made in later versions). 13 14 15 $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/target-os-src/hal.h.tpp#1 $ 16 17 Copyright (c) 1999-2015 Cadence Design Systems, Inc. 18 19 Permission is hereby granted, free of charge, to any person obtaining 20 a copy of this software and associated documentation files (the 21 "Software"), to deal in the Software without restriction, including 22 without limitation the rights to use, copy, modify, merge, publish, 23 distribute, sublicense, and/or sell copies of the Software, and to 24 permit persons to whom the Software is furnished to do so, subject to 25 the following conditions: 26 27 The above copyright notice and this permission notice shall be included 28 in all copies or substantial portions of the Software. 29 30 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 31 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 32 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 33 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 34 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 35 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 36 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 37 */ 38 39 #ifndef XTENSA_HAL_H 40 #define XTENSA_HAL_H 41 42 /**************************************************************************** 43 Definitions Useful for Any Code, USER or PRIVILEGED 44 ****************************************************************************/ 45 46 47 /*---------------------------------------------------------------------- 48 Constant Definitions (shared with assembly) 49 ----------------------------------------------------------------------*/ 50 51 /* 52 * Software (Xtensa Tools) version information. Not configuration-specific! 53 * 54 * NOTE: "release" is a misnomer here, these are really product "version" 55 * numbers. A "release" is a collection of product versions 56 * made available at once (together) to customers. 57 * In the past, release and version names all matched in T####.# form, 58 * making the distinction irrelevant. This is no longer the case. 59 */ 60 #define XTHAL_RELEASE_MAJOR 12000 61 #define XTHAL_RELEASE_MINOR 9 62 #define XTHAL_RELEASE_NAME "12.0.9" 63 #define XTHAL_REL_12 1 64 #define XTHAL_REL_12_0 1 65 #define XTHAL_REL_12_0_9 1 66 67 /* HAL version numbers (these names are for backward compatibility): */ 68 #define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR 69 #define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR 70 /* 71 * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV: 72 * 73 * SW Version MAJOR MINOR Comment 74 * ======= ===== ===== ======= 75 * T1015.n n/a n/a (HAL not yet available) 76 * T1020.{0,1,2} 0 1 (HAL beta) 77 * T1020.{3,4} 0 2 First release. 78 * T1020.n (n>4) 0 2 or >3 (TBD) 79 * T1030.0 0 1 (HAL beta) 80 * T1030.{1,2} 0 3 Equivalent to first release. 81 * T1030.n (n>=3) 0 >= 3 (TBD) 82 * T1040.n 1040 n Full CHAL available from T1040.2 83 * T1050.n 1050 n . 84 * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n) 85 * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n) 86 * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2)) 87 * 8.0.n 8000 n Xtensa Tools v8 (RC-20xx.n) 88 * 9.0.n 9000 n Xtensa Tools v9 (RD-201x.n) 89 * 10.0.n 10000 n Xtensa Tools v10 (RE-201x.n) 90 * 91 * 92 * Note: there is a distinction between the software version with 93 * which something is compiled (accessible using XTHAL_RELEASE_* macros) 94 * and the software version with which the HAL library was compiled 95 * (accessible using Xthal_release_* global variables). This 96 * distinction is particularly relevant for vendors that distribute 97 * configuration-independent binaries (eg. an OS), where their customer 98 * might link it with a HAL of a different Xtensa software version. 99 * In this case, it may be appropriate for the OS to verify at run-time 100 * whether XTHAL_RELEASE_* and Xthal_release_* are compatible. 101 * [Guidelines as to which version is compatible with which are not 102 * currently provided explicitly, but might be inferred from reading 103 * OSKit documentation for all releases -- compatibility is also highly 104 * dependent on which HAL features are used. Each version is usually 105 * backward compatible, with very few exceptions if any.] 106 */ 107 108 /* Version comparison operators (among major/minor pairs): */ 109 #define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \ 110 ((maja) == (majb) && (mina) >= (minb))) 111 #define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \ 112 ((maja) == (majb) && (mina) > (minb))) 113 #define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \ 114 ((maja) == (majb) && (mina) <= (minb))) 115 #define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \ 116 ((maja) == (majb) && (mina) < (minb))) 117 #define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb)) 118 119 /* Fuzzy (3-way) logic operators: */ 120 #define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */ 121 #define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE) 122 #define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE) 123 #define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE) 124 125 126 /* 127 * Architectural limit, independent of configuration: 128 */ 129 #define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */ 130 131 /* Misc: */ 132 #define XTHAL_LITTLEENDIAN 0 133 #define XTHAL_BIGENDIAN 1 134 135 136 137 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 138 #ifdef __cplusplus 139 extern "C" { 140 #endif 141 142 #include <stdint.h> 143 #include <stddef.h> 144 145 /*---------------------------------------------------------------------- 146 HAL 147 ----------------------------------------------------------------------*/ 148 149 /* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */ 150 extern const unsigned int Xthal_rev_no; 151 152 153 /*---------------------------------------------------------------------- 154 Optional/Custom Processor State 155 ----------------------------------------------------------------------*/ 156 157 /* save & restore the extra processor state */ 158 extern void xthal_save_extra(void *base); 159 extern void xthal_restore_extra(void *base); 160 161 extern void xthal_save_cpregs(void *base, int); 162 extern void xthal_restore_cpregs(void *base, int); 163 /* versions specific to each coprocessor id */ 164 extern void xthal_save_cp0(void *base); 165 extern void xthal_save_cp1(void *base); 166 extern void xthal_save_cp2(void *base); 167 extern void xthal_save_cp3(void *base); 168 extern void xthal_save_cp4(void *base); 169 extern void xthal_save_cp5(void *base); 170 extern void xthal_save_cp6(void *base); 171 extern void xthal_save_cp7(void *base); 172 extern void xthal_restore_cp0(void *base); 173 extern void xthal_restore_cp1(void *base); 174 extern void xthal_restore_cp2(void *base); 175 extern void xthal_restore_cp3(void *base); 176 extern void xthal_restore_cp4(void *base); 177 extern void xthal_restore_cp5(void *base); 178 extern void xthal_restore_cp6(void *base); 179 extern void xthal_restore_cp7(void *base); 180 /* pointers to each of the functions above */ 181 extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS]; 182 extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS]; 183 /* similarly for non-windowed ABI (may be same or different) */ 184 extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS]; 185 extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS]; 186 187 /*extern void xthal_save_all_extra(void *base);*/ 188 /*extern void xthal_restore_all_extra(void *base);*/ 189 190 /* space for processor state */ 191 extern const unsigned int Xthal_extra_size; 192 extern const unsigned int Xthal_extra_align; 193 extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS]; 194 extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS]; 195 extern const unsigned int Xthal_all_extra_size; 196 extern const unsigned int Xthal_all_extra_align; 197 /* coprocessor names */ 198 extern const char * const Xthal_cp_names[XTHAL_MAX_CPS]; 199 200 /* initialize the extra processor */ 201 /*extern void xthal_init_extra(void);*/ 202 /* initialize the TIE coprocessor */ 203 /*extern void xthal_init_cp(int);*/ 204 205 /* initialize the extra processor */ 206 extern void xthal_init_mem_extra(void *); 207 /* initialize the TIE coprocessor */ 208 extern void xthal_init_mem_cp(void *, int); 209 210 /* the number of TIE coprocessors contiguous from zero (for Tor2) */ 211 extern const unsigned int Xthal_num_coprocessors; 212 213 /* actual number of coprocessors */ 214 extern const unsigned char Xthal_cp_num; 215 /* index of highest numbered coprocessor, plus one */ 216 extern const unsigned char Xthal_cp_max; 217 /* index of highest allowed coprocessor number, per cfg, plus one */ 218 /*extern const unsigned char Xthal_cp_maxcfg;*/ 219 /* bitmask of which coprocessors are present */ 220 extern const unsigned int Xthal_cp_mask; 221 222 /* read & write extra state register */ 223 /*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/ 224 /*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/ 225 226 /* read & write a TIE coprocessor register */ 227 /*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/ 228 /*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/ 229 230 /* return coprocessor number based on register */ 231 /*extern int xthal_which_cp(unsigned reg);*/ 232 233 234 /*---------------------------------------------------------------------- 235 Register Windows 236 ----------------------------------------------------------------------*/ 237 238 /* number of registers in register window */ 239 extern const unsigned int Xthal_num_aregs; 240 extern const unsigned char Xthal_num_aregs_log2; 241 242 243 /*---------------------------------------------------------------------- 244 Cache 245 ----------------------------------------------------------------------*/ 246 247 /* size of the cache lines in log2(bytes) */ 248 extern const unsigned char Xthal_icache_linewidth; 249 extern const unsigned char Xthal_dcache_linewidth; 250 /* size of the cache lines in bytes (2^linewidth) */ 251 extern const unsigned short Xthal_icache_linesize; 252 extern const unsigned short Xthal_dcache_linesize; 253 254 /* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */ 255 extern const unsigned int Xthal_icache_size; 256 extern const unsigned int Xthal_dcache_size; 257 /* cache features */ 258 extern const unsigned char Xthal_dcache_is_writeback; 259 260 /* cache region operations*/ 261 extern void xthal_icache_region_invalidate( void *addr, unsigned size ); 262 extern void xthal_dcache_region_invalidate( void *addr, unsigned size ); 263 extern void xthal_dcache_region_writeback( void *addr, unsigned size ); 264 extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size ); 265 266 #ifndef XTHAL_USE_CACHE_MACROS 267 /* cache line operations*/ 268 extern void xthal_icache_line_invalidate(void *addr); 269 extern void xthal_dcache_line_invalidate(void *addr); 270 extern void xthal_dcache_line_writeback(void *addr); 271 extern void xthal_dcache_line_writeback_inv(void *addr); 272 /* sync icache and memory */ 273 extern void xthal_icache_sync( void ); 274 /* sync dcache and memory */ 275 extern void xthal_dcache_sync( void ); 276 #endif 277 278 /* get/set number of icache ways enabled */ 279 extern unsigned int xthal_icache_get_ways(void); 280 extern void xthal_icache_set_ways(unsigned int ways); 281 /* get/set number of dcache ways enabled */ 282 extern unsigned int xthal_dcache_get_ways(void); 283 extern void xthal_dcache_set_ways(unsigned int ways); 284 285 /* coherency (low-level -- not normally called directly) */ 286 extern void xthal_cache_coherence_on( void ); 287 extern void xthal_cache_coherence_off( void ); 288 /* coherency (high-level) */ 289 extern void xthal_cache_coherence_optin( void ); 290 extern void xthal_cache_coherence_optout( void ); 291 292 /* 293 * Cache prefetch control. 294 * The parameter to xthal_set_cache_prefetch() contains both 295 * a PREFCTL register value and a mask of which bits to actually modify. 296 * This allows easily combining field macros (below) by ORing, 297 * leaving unspecified fields unmodified. 298 * 299 * For backward compatibility with the older version of this routine 300 * (that took 15-bit value and mask in a 32-bit parameter, for pre-RF 301 * cores with only the lower 15 bits of PREFCTL defined), the 32-bit 302 * value and mask are staggered as follows in a 64-bit parameter: 303 * param[63:48] are PREFCTL[31:16] if param[31] is set 304 * param[47:32] are mask[31:16] if param[31] is set 305 * param[31] is set if mask is used, 0 if not 306 * param[31:16] are mask[15:0] if param[31] is set 307 * param[31:16] are PREFCTL[31:16] if param[31] is clear 308 * param[15:0] are PREFCTL[15:0] 309 * 310 * Limitation: PREFCTL register bit 31 cannot be set without masking, 311 * and bit 15 must always be set when using masking, so it is hoped that 312 * these two bits will remain reserved, read-as-zero in PREFCTL. 313 */ 314 #define XTHAL_PREFETCH_ENABLE -1 /* enable inst+data prefetch */ 315 #define XTHAL_PREFETCH_DISABLE 0xFFFF0000 /* disab inst+data prefetch*/ 316 #define XTHAL_DCACHE_PREFETCH(n) (0x800F0000+((n)&0xF)) /* data-side */ 317 #define XTHAL_DCACHE_PREFETCH_OFF XTHAL_DCACHE_PREFETCH(0) /* disable */ 318 #define XTHAL_DCACHE_PREFETCH_LOW XTHAL_DCACHE_PREFETCH(4) /* less aggr.*/ 319 #define XTHAL_DCACHE_PREFETCH_MEDIUM XTHAL_DCACHE_PREFETCH(5) /* mid aggr. */ 320 #define XTHAL_DCACHE_PREFETCH_HIGH XTHAL_DCACHE_PREFETCH(8) /* more aggr.*/ 321 #define XTHAL_DCACHE_PREFETCH_L1_OFF 0x90000000 /* to prefetch buffers*/ 322 #define XTHAL_DCACHE_PREFETCH_L1 0x90001000 /* direct to L1 dcache*/ 323 #define XTHAL_ICACHE_PREFETCH(n) (0x80F00000+(((n)&0xF)<<4)) /* i-side */ 324 #define XTHAL_ICACHE_PREFETCH_OFF XTHAL_ICACHE_PREFETCH(0) /* disable */ 325 #define XTHAL_ICACHE_PREFETCH_LOW XTHAL_ICACHE_PREFETCH(4) /* less aggr.*/ 326 #define XTHAL_ICACHE_PREFETCH_MEDIUM XTHAL_ICACHE_PREFETCH(5) /* mid aggr. */ 327 #define XTHAL_ICACHE_PREFETCH_HIGH XTHAL_ICACHE_PREFETCH(8) /* more aggr.*/ 328 #define XTHAL_ICACHE_PREFETCH_L1_OFF 0xA0000000 /* (not implemented) */ 329 #define XTHAL_ICACHE_PREFETCH_L1 0xA0002000 /* (not implemented) */ 330 #define _XTHAL_PREFETCH_BLOCKS(n) ((n)<0?0:(n)<5?(n):(n)<15?((n)>>1)+2:9) 331 #define XTHAL_PREFETCH_BLOCKS(n) (0x0000000F80000000ULL + \ 332 (((unsigned long long)_XTHAL_PREFETCH_BLOCKS(n))<<48)) 333 334 extern int xthal_get_cache_prefetch( void ); 335 extern int xthal_set_cache_prefetch( int ); 336 extern int xthal_set_cache_prefetch_long( unsigned long long ); 337 /* Only use the new extended function from now on: */ 338 #define xthal_set_cache_prefetch xthal_set_cache_prefetch_long 339 #define xthal_set_cache_prefetch_nw xthal_set_cache_prefetch_long_nw 340 341 342 /*---------------------------------------------------------------------- 343 Debug 344 ----------------------------------------------------------------------*/ 345 346 /* 1 if debug option configured, 0 if not: */ 347 extern const int Xthal_debug_configured; 348 349 /* Set (plant) and remove software breakpoint, both synchronizing cache: */ 350 extern unsigned int xthal_set_soft_break(void *addr); 351 extern void xthal_remove_soft_break(void *addr, unsigned int); 352 353 354 /*---------------------------------------------------------------------- 355 Disassembler 356 ----------------------------------------------------------------------*/ 357 358 /* Max expected size of the return buffer for a disassembled instruction (hint only): */ 359 #define XTHAL_DISASM_BUFSIZE 80 360 361 /* Disassembly option bits for selecting what to return: */ 362 #define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */ 363 #define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */ 364 #define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */ 365 #define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */ 366 #define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */ 367 368 /* routine to get a string for the disassembled instruction */ 369 extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr, 370 char *buffer, unsigned buflen, unsigned options ); 371 372 /* routine to get the size of the next instruction. Returns 0 for 373 illegal instruction */ 374 extern int xthal_disassemble_size( unsigned char *instr_buf ); 375 376 377 /*---------------------------------------------------------------------- 378 Instruction/Data RAM/ROM Access 379 ----------------------------------------------------------------------*/ 380 381 extern void* xthal_memcpy(void *dst, const void *src, unsigned len); 382 extern void* xthal_bcopy(const void *src, void *dst, unsigned len); 383 384 385 /*---------------------------------------------------------------------- 386 MP Synchronization 387 ----------------------------------------------------------------------*/ 388 389 extern int xthal_compare_and_set( int *addr, int test_val, int compare_val ); 390 391 /*extern const char Xthal_have_s32c1i;*/ 392 393 394 /*---------------------------------------------------------------------- 395 Miscellaneous 396 ----------------------------------------------------------------------*/ 397 398 extern const unsigned int Xthal_release_major; 399 extern const unsigned int Xthal_release_minor; 400 extern const char * const Xthal_release_name; 401 extern const char * const Xthal_release_internal; 402 403 extern const unsigned char Xthal_memory_order; 404 extern const unsigned char Xthal_have_windowed; 405 extern const unsigned char Xthal_have_density; 406 extern const unsigned char Xthal_have_booleans; 407 extern const unsigned char Xthal_have_loops; 408 extern const unsigned char Xthal_have_nsa; 409 extern const unsigned char Xthal_have_minmax; 410 extern const unsigned char Xthal_have_sext; 411 extern const unsigned char Xthal_have_clamps; 412 extern const unsigned char Xthal_have_mac16; 413 extern const unsigned char Xthal_have_mul16; 414 extern const unsigned char Xthal_have_fp; 415 extern const unsigned char Xthal_have_speculation; 416 extern const unsigned char Xthal_have_threadptr; 417 418 extern const unsigned char Xthal_have_pif; 419 extern const unsigned short Xthal_num_writebuffer_entries; 420 421 extern const unsigned int Xthal_build_unique_id; 422 /* Version info for hardware targeted by software upgrades: */ 423 extern const unsigned int Xthal_hw_configid0; 424 extern const unsigned int Xthal_hw_configid1; 425 extern const unsigned int Xthal_hw_release_major; 426 extern const unsigned int Xthal_hw_release_minor; 427 extern const char * const Xthal_hw_release_name; 428 extern const char * const Xthal_hw_release_internal; 429 430 /* Clear any remnant code-dependent state (i.e. clear loop count regs). */ 431 extern void xthal_clear_regcached_code( void ); 432 433 #ifdef __cplusplus 434 } 435 #endif 436 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ 437 438 439 440 441 442 /**************************************************************************** 443 Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 444 ****************************************************************************/ 445 446 447 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 448 449 /*---------------------------------------------------------------------- 450 Constant Definitions (shared with assembly) 451 ----------------------------------------------------------------------*/ 452 453 /* 454 * Architectural limits, independent of configuration. 455 * Note that these are ISA-defined limits, not micro-architecture implementation 456 * limits enforced by the Xtensa Processor Generator (which may be stricter than 457 * these below). 458 */ 459 #define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */ 460 #define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */ 461 /* (as of T1040, implementation limit is 7: 0..6) */ 462 #define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */ 463 /* (as of T1040, implementation limit is 3: 0..2) */ 464 465 /* Interrupt types: */ 466 #define XTHAL_INTTYPE_UNCONFIGURED 0 467 #define XTHAL_INTTYPE_SOFTWARE 1 468 #define XTHAL_INTTYPE_EXTERN_EDGE 2 469 #define XTHAL_INTTYPE_EXTERN_LEVEL 3 470 #define XTHAL_INTTYPE_TIMER 4 471 #define XTHAL_INTTYPE_NMI 5 472 #define XTHAL_INTTYPE_WRITE_ERROR 6 473 #define XTHAL_INTTYPE_PROFILING 7 474 #define XTHAL_INTTYPE_IDMA_DONE 8 475 #define XTHAL_INTTYPE_IDMA_ERR 9 476 #define XTHAL_INTTYPE_GS_ERR 10 477 #define XTHAL_INTTYPE_SG_ERR 10 /* backward compatibility name - deprecated */ 478 #define XTHAL_MAX_INTTYPES 11 /* number of interrupt types */ 479 480 /* Timer related: */ 481 #define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */ 482 #define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */ 483 484 /* Local Memory ECC/Parity: */ 485 #define XTHAL_MEMEP_PARITY 1 486 #define XTHAL_MEMEP_ECC 2 487 /* Flags parameter to xthal_memep_inject_error(): */ 488 #define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */ 489 #define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */ 490 #define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */ 491 #define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */ 492 #define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */ 493 #define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error 494 (default is non-corr.) */ 495 496 497 /* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */ 498 #define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none 499 exception on any access (aka "illegal") */ 500 #define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) 501 [or H HC] way from tag match; 502 [or U UC] (ISA: same except Isolate case) */ 503 #define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none 504 [or F FI fill] refill cache on miss, way from LRU 505 (ISA: Read/Write Miss Refill) */ 506 #define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT 507 store immediately to memory (ISA: same) */ 508 #define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none 509 use cache regardless of hit-vs-miss, 510 way from vaddr (ISA: use-cache-on-miss+hit) */ 511 #define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * 512 non-speculative; spec/replay refs not permitted */ 513 #define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M 514 on read, other CPU/bus-master may need to supply data; 515 on write, maybe redirect to or flush other CPU dirty line; etc */ 516 #if 0 517 #define XTHAL_AMB_BUFFERABLE x /* 000 B BU --s: BUfferable ? 518 write response may return earlier than from final destination */ 519 #define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * 520 mem accesses cannot be out of order */ 521 #define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none 522 allow combining/merging/coalescing multiple writes 523 (to same datapath data unit) into one 524 (implied by writeback) */ 525 #define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none 526 memory will not bus error (if it does, 527 handle as fatal imprecise interrupt) */ 528 #define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none 529 on refill, read line+1 into prefetch buffers */ 530 #define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none 531 access one of N stream buffers */ 532 #endif /*0*/ 533 534 #define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION) 535 #define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE) 536 #define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE) 537 #define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU) 538 #define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE) 539 #define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD) 540 #define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT) 541 #if 0 542 #define XTHAL_AM_BUFFERABLE (1<<XTHAL_AMB_BUFFERABLE) 543 #define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED) 544 #define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES) 545 #define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED) 546 #define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH) 547 #define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM) 548 #endif /*0*/ 549 550 /* 551 * Allowed Access Modes (bit combinations). 552 * 553 * Columns are: 554 * "FOGIWACE" 555 * Access mode bits (see XTHAL_AMB_xxx above). 556 * <letter> = bit is set 557 * '-' = bit is clear 558 * '.' = bit is irrelevant / don't care, as follows: 559 * E=1 makes all others irrelevant 560 * W,F relevant only for stores 561 * "2345" 562 * Indicates which Xtensa releases support the corresponding 563 * access mode. Releases for each character column are: 564 * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1 565 * 3 = T1020.2 and later: T1020.2+, T1030 566 * 4 = T1040 567 * 5 = T1050 (maybe), LX1, LX2, LX2.1 568 * 7 = LX2.2 569 * 8 = LX3, LX4 570 * 9 = LX5 571 * And the character column contents are: 572 * <number> = supported by release(s) 573 * "." = unsupported by release(s) 574 * "?" = support unknown 575 */ 576 /* foMGIWACE 2345789 */ 577 /* For instruction fetch: */ 578 #define XTHAL_FAM_EXCEPTION 0x001 /* ........E 2345789 exception */ 579 /*efine XTHAL_FAM_ISOLATE*/ /*0x012*/ /* .---I.-C- ....... isolate */ 580 #define XTHAL_FAM_BYPASS 0x000 /* .----.--- 2345789 bypass */ 581 /*efine XTHAL_FAM_NACACHED*/ /*0x002*/ /* .----.-C- ....... cached no-allocate (frozen) */ 582 #define XTHAL_FAM_CACHED 0x006 /* .----.AC- 2345789 cached */ 583 /* For data load: */ 584 #define XTHAL_LAM_EXCEPTION 0x001 /* ........E 2345789 exception */ 585 #define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 2345789 isolate */ 586 #define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2...... bypass speculative */ 587 #define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .345789 bypass guarded */ 588 #define XTHAL_LAM_CACHED_NOALLOC 0x002 /* .O---.-C- 2345789 cached no-allocate speculative */ 589 #define XTHAL_LAM_NACACHED XTHAL_LAM_CACHED_NOALLOC 590 #define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .?..... cached no-allocate guarded */ 591 #define XTHAL_LAM_CACHED 0x006 /* .----.AC- 2345789 cached speculative */ 592 #define XTHAL_LAM_COHCACHED 0x046 /* .-M--.AC- ....*89 cached speculative MP-coherent */ 593 /* For data store: */ 594 #define XTHAL_SAM_EXCEPTION 0x001 /* ........E 2345789 exception */ 595 #define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 2345789 isolate */ 596 #define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 2345789 bypass */ 597 #define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 2345789 writethrough */ 598 /*efine XTHAL_SAM_WRITETHRU_ALLOC*/ /*0x02E*/ /* -O-G-WAC- ....... writethrough allocate */ 599 #define XTHAL_SAM_WRITEBACK 0x026 /* F--G--AC- ...5789 writeback */ 600 #define XTHAL_SAM_WRITEBACK_NOALLOC 0x022 /* ?--G---C- .....89 writeback no-allocate */ 601 #define XTHAL_SAM_COHWRITEBACK 0x066 /* F-MG--AC- ....*89 writeback MP-coherent */ 602 /* For PIF attributes: */ /* -PIwrWCBUUUU ...9 */ 603 #define XTHAL_PAM_BYPASS 0x000 /* xxx00000xxxx ...9 bypass non-bufferable */ 604 #define XTHAL_PAM_BYPASS_BUF 0x010 /* xxx0000bxxxx ...9 bypass */ 605 #define XTHAL_PAM_CACHED_NOALLOC 0x030 /* xxx0001bxxxx ...9 cached no-allocate */ 606 #define XTHAL_PAM_WRITETHRU 0x0B0 /* xxx0101bxxxx ...9 writethrough (WT) */ 607 #define XTHAL_PAM_WRITEBACK_NOALLOC 0x0F0 /* xxx0111bxxxx ...9 writeback no-alloc (WBNA) */ 608 #define XTHAL_PAM_WRITEBACK 0x1F0 /* xxx1111bxxxx ...9 writeback (WB) */ 609 /*efine XTHAL_PAM_NORMAL*/ /*0x050*/ /* xxx0010bxxxx .... (unimplemented) */ 610 /*efine XTHAL_PAM_WRITETHRU_WA*/ /*0x130*/ /* xxx1001bxxxx .... (unimplemented, less likely) */ 611 /*efine XTHAL_PAM_WRITETHRU_RWA*/ /*0x1B0*/ /* xxx1101bxxxx .... (unimplemented, less likely) */ 612 /*efine XTHAL_PAM_WRITEBACK_WA*/ /*0x170*/ /* xxx1011bxxxx .... (unimplemented, less likely) */ 613 614 615 #if 0 616 /* 617 Cache attribute encoding for CACHEATTR (per ISA): 618 (Note: if this differs from ISA Ref Manual, ISA has precedence) 619 620 Inst-fetches Loads Stores 621 ------------- ------------ ------------- 622 0x0 FCA_EXCEPTION LCA_NACACHED SCA_WRITETHRU cached no-allocate (previously misnamed "uncached") 623 0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached 624 0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass cache (what most people call uncached) 625 0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate 626 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 627 0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK[M] write-back [MP-coherent] 628 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 629 0x5 FCA_CACHED LCA_CACHED SCA_WRITEBACK_NOALLOC write-back no-allocate 630 or FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 631 0x6..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved) 632 0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate 633 0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal 634 * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G) 635 */ 636 #endif /*0*/ 637 638 639 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 640 #ifdef __cplusplus 641 extern "C" { 642 #endif 643 644 645 /*---------------------------------------------------------------------- 646 Register Windows 647 ----------------------------------------------------------------------*/ 648 649 /* This spill any live register windows (other than the caller's): 650 * (NOTE: current implementation require privileged code, but 651 * a user-callable implementation is possible.) */ 652 extern void xthal_window_spill( void ); 653 654 655 /*---------------------------------------------------------------------- 656 Optional/Custom Processor State 657 ----------------------------------------------------------------------*/ 658 659 /* validate & invalidate the TIE register file */ 660 extern void xthal_validate_cp(int); 661 extern void xthal_invalidate_cp(int); 662 663 /* read and write cpenable register */ 664 extern void xthal_set_cpenable(unsigned); 665 extern unsigned xthal_get_cpenable(void); 666 667 668 /*---------------------------------------------------------------------- 669 Interrupts 670 ----------------------------------------------------------------------*/ 671 672 /* the number of interrupt levels */ 673 extern const unsigned char Xthal_num_intlevels; 674 /* the number of interrupts */ 675 extern const unsigned char Xthal_num_interrupts; 676 /* the highest level of interrupts masked by PS.EXCM */ 677 extern const unsigned char Xthal_excm_level; 678 679 /* mask for level of interrupts */ 680 extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS]; 681 /* mask for level 0 to N interrupts */ 682 extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS]; 683 684 /* level of each interrupt */ 685 extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS]; 686 687 /* type per interrupt */ 688 extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS]; 689 690 /* masks of each type of interrupt */ 691 extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES]; 692 693 /* interrupt numbers assigned to each timer interrupt */ 694 extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS]; 695 696 /* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */ 697 extern unsigned xthal_get_intenable( void ); 698 extern void xthal_set_intenable( unsigned ); 699 extern unsigned xthal_get_interrupt( void ); 700 #define xthal_get_intread xthal_get_interrupt /* backward compatibility */ 701 702 /* These two functions are deprecated. Use the newer functions 703 xthal_interrupt_trigger and xthal_interrupt_clear instead. */ 704 extern void xthal_set_intset( unsigned ); 705 extern void xthal_set_intclear( unsigned ); 706 707 708 /*---------------------------------------------------------------------- 709 Debug 710 ----------------------------------------------------------------------*/ 711 712 /* Number of instruction and data break registers: */ 713 extern const int Xthal_num_ibreak; 714 extern const int Xthal_num_dbreak; 715 716 717 /*---------------------------------------------------------------------- 718 Core Counter 719 ----------------------------------------------------------------------*/ 720 721 /* counter info */ 722 extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */ 723 extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */ 724 725 /* get CCOUNT register (if not present return 0) */ 726 extern unsigned xthal_get_ccount(void); 727 728 /* set and get CCOMPAREn registers (if not present, get returns 0) */ 729 extern void xthal_set_ccompare(int, unsigned); 730 extern unsigned xthal_get_ccompare(int); 731 732 733 /*---------------------------------------------------------------------- 734 Miscellaneous 735 ----------------------------------------------------------------------*/ 736 737 extern const unsigned char Xthal_have_prid; 738 extern const unsigned char Xthal_have_exceptions; 739 extern const unsigned char Xthal_xea_version; 740 extern const unsigned char Xthal_have_interrupts; 741 extern const unsigned char Xthal_have_highlevel_interrupts; 742 extern const unsigned char Xthal_have_nmi; 743 744 extern unsigned xthal_get_prid( void ); 745 746 747 /*---------------------------------------------------------------------- 748 Virtual interrupt prioritization (DEPRECATED) 749 ----------------------------------------------------------------------*/ 750 751 /* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */ 752 extern unsigned xthal_vpri_to_intlevel(unsigned vpri); 753 extern unsigned xthal_intlevel_to_vpri(unsigned intlevel); 754 755 /* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */ 756 /* These functions are deprecated. Use xthal_interrupt_enable and xthal_interrupt_disable instead. */ 757 extern unsigned xthal_int_enable(unsigned); 758 extern unsigned xthal_int_disable(unsigned); 759 760 /* Set/get virtual priority of an interrupt: */ 761 extern int xthal_set_int_vpri(int intnum, int vpri); 762 extern int xthal_get_int_vpri(int intnum); 763 764 /* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */ 765 extern void xthal_set_vpri_locklevel(unsigned intlevel); 766 extern unsigned xthal_get_vpri_locklevel(void); 767 768 /* Set/get current virtual interrupt priority: */ 769 extern unsigned xthal_set_vpri(unsigned vpri); 770 extern unsigned xthal_get_vpri(void); 771 extern unsigned xthal_set_vpri_intlevel(unsigned intlevel); 772 extern unsigned xthal_set_vpri_lock(void); 773 774 775 /*---------------------------------------------------------------------- 776 Generic Interrupt Trampolining Support (DEPRECATED) 777 ----------------------------------------------------------------------*/ 778 779 typedef void (XtHalVoidFunc)(void); 780 781 /* Bitmask of interrupts currently trampolining down: */ 782 extern unsigned Xthal_tram_pending; 783 784 /* 785 * Bitmask of which interrupts currently trampolining down synchronously are 786 * actually enabled; this bitmask is necessary because INTENABLE cannot hold 787 * that state (sync-trampolining interrupts must be kept disabled while 788 * trampolining); in the current implementation, any bit set here is not set 789 * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level 790 * one), its enable bit must be moved from here to INTENABLE: 791 */ 792 extern unsigned Xthal_tram_enabled; 793 794 /* Bitmask of interrupts configured for sync trampolining: */ 795 extern unsigned Xthal_tram_sync; 796 797 /* Trampoline support functions: */ 798 extern unsigned xthal_tram_pending_to_service( void ); 799 extern void xthal_tram_done( unsigned serviced_mask ); 800 extern int xthal_tram_set_sync( int intnum, int sync ); 801 extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn ); 802 803 804 /*---------------------------------------------------------------------- 805 Internal Memories 806 ----------------------------------------------------------------------*/ 807 808 extern const unsigned char Xthal_num_instrom; 809 extern const unsigned char Xthal_num_instram; 810 extern const unsigned char Xthal_num_datarom; 811 extern const unsigned char Xthal_num_dataram; 812 extern const unsigned char Xthal_num_xlmi; 813 814 /* Each of the following arrays contains at least one entry, 815 * or as many entries as needed if more than one: */ 816 extern const unsigned int Xthal_instrom_vaddr[]; 817 extern const unsigned int Xthal_instrom_paddr[]; 818 extern const unsigned int Xthal_instrom_size []; 819 extern const unsigned int Xthal_instram_vaddr[]; 820 extern const unsigned int Xthal_instram_paddr[]; 821 extern const unsigned int Xthal_instram_size []; 822 extern const unsigned int Xthal_datarom_vaddr[]; 823 extern const unsigned int Xthal_datarom_paddr[]; 824 extern const unsigned int Xthal_datarom_size []; 825 extern const unsigned int Xthal_dataram_vaddr[]; 826 extern const unsigned int Xthal_dataram_paddr[]; 827 extern const unsigned int Xthal_dataram_size []; 828 extern const unsigned int Xthal_xlmi_vaddr[]; 829 extern const unsigned int Xthal_xlmi_paddr[]; 830 extern const unsigned int Xthal_xlmi_size []; 831 832 833 /*---------------------------------------------------------------------- 834 Cache 835 ----------------------------------------------------------------------*/ 836 837 /* number of cache sets in log2(lines per way) */ 838 extern const unsigned char Xthal_icache_setwidth; 839 extern const unsigned char Xthal_dcache_setwidth; 840 /* cache set associativity (number of ways) */ 841 extern const unsigned int Xthal_icache_ways; 842 extern const unsigned int Xthal_dcache_ways; 843 /* cache features */ 844 extern const unsigned char Xthal_icache_line_lockable; 845 extern const unsigned char Xthal_dcache_line_lockable; 846 847 /* cache attribute register control (used by other HAL routines) */ 848 extern unsigned xthal_get_cacheattr( void ); 849 extern unsigned xthal_get_icacheattr( void ); 850 extern unsigned xthal_get_dcacheattr( void ); 851 extern void xthal_set_cacheattr( unsigned ); 852 extern void xthal_set_icacheattr( unsigned ); 853 extern void xthal_set_dcacheattr( unsigned ); 854 /* set cache attribute (access modes) for a range of memory */ 855 extern int xthal_set_region_attribute( void *addr, unsigned size, 856 unsigned cattr, unsigned flags ); 857 /* Bits of flags parameter to xthal_set_region_attribute(): */ 858 #define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */ 859 #define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */ 860 #define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */ 861 #define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */ 862 #define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */ 863 864 /* enable caches */ 865 extern void xthal_icache_enable( void ); /* DEPRECATED */ 866 extern void xthal_dcache_enable( void ); /* DEPRECATED */ 867 /* disable caches */ 868 extern void xthal_icache_disable( void ); /* DEPRECATED */ 869 extern void xthal_dcache_disable( void ); /* DEPRECATED */ 870 871 /* whole cache operations (privileged) */ 872 extern void xthal_icache_all_invalidate( void ); 873 extern void xthal_dcache_all_invalidate( void ); 874 extern void xthal_dcache_all_writeback( void ); 875 extern void xthal_dcache_all_writeback_inv( void ); 876 extern void xthal_icache_all_unlock( void ); 877 extern void xthal_dcache_all_unlock( void ); 878 879 /* address-range cache operations (privileged) */ 880 /* prefetch and lock specified memory range into cache */ 881 extern void xthal_icache_region_lock( void *addr, unsigned size ); 882 extern void xthal_dcache_region_lock( void *addr, unsigned size ); 883 /* unlock from cache */ 884 extern void xthal_icache_region_unlock( void *addr, unsigned size ); 885 extern void xthal_dcache_region_unlock( void *addr, unsigned size ); 886 887 /* huge-range cache operations (privileged) (EXPERIMENTAL) */ 888 extern void xthal_icache_hugerange_invalidate( void *addr, unsigned size ); 889 extern void xthal_icache_hugerange_unlock( void *addr, unsigned size ); 890 extern void xthal_dcache_hugerange_invalidate( void *addr, unsigned size ); 891 extern void xthal_dcache_hugerange_unlock( void *addr, unsigned size ); 892 extern void xthal_dcache_hugerange_writeback( void *addr, unsigned size ); 893 extern void xthal_dcache_hugerange_writeback_inv( void *addr, unsigned size ); 894 895 # ifndef XTHAL_USE_CACHE_MACROS 896 /* cache line operations (privileged) */ 897 extern void xthal_icache_line_lock(void *addr); 898 extern void xthal_dcache_line_lock(void *addr); 899 extern void xthal_icache_line_unlock(void *addr); 900 extern void xthal_dcache_line_unlock(void *addr); 901 # endif 902 903 904 905 /*---------------------------------------------------------------------- 906 Local Memory ECC/Parity 907 ----------------------------------------------------------------------*/ 908 909 /* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */ 910 extern void xthal_memep_inject_error(void *addr, int size, int flags); 911 912 913 914 /*---------------------------------------------------------------------- 915 Memory Management Unit 916 ----------------------------------------------------------------------*/ 917 918 extern const unsigned char Xthal_have_spanning_way; 919 extern const unsigned char Xthal_have_identity_map; 920 extern const unsigned char Xthal_have_mimic_cacheattr; 921 extern const unsigned char Xthal_have_xlt_cacheattr; 922 extern const unsigned char Xthal_have_cacheattr; 923 extern const unsigned char Xthal_have_tlbs; 924 925 extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */ 926 extern const unsigned char Xthal_mmu_asid_kernel; 927 extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */ 928 extern const unsigned char Xthal_mmu_ring_bits; 929 extern const unsigned char Xthal_mmu_sr_bits; 930 extern const unsigned char Xthal_mmu_ca_bits; 931 extern const unsigned int Xthal_mmu_max_pte_page_size; 932 extern const unsigned int Xthal_mmu_min_pte_page_size; 933 934 extern const unsigned char Xthal_itlb_way_bits; 935 extern const unsigned char Xthal_itlb_ways; 936 extern const unsigned char Xthal_itlb_arf_ways; 937 extern const unsigned char Xthal_dtlb_way_bits; 938 extern const unsigned char Xthal_dtlb_ways; 939 extern const unsigned char Xthal_dtlb_arf_ways; 940 941 /* Return error codes for hal functions */ 942 943 /* function sucessful, operation completed as expected */ 944 #define XTHAL_SUCCESS 0 945 /* XTHAL_CAFLAGS_NO_PARTIAL was specified, and no full region is 946 * covered by the address range. */ 947 #define XTHAL_NO_REGIONS_COVERED -1 948 /* The XTHAL_CAFLAGS_EXACT flag was given, but no exact mapping is possible. */ 949 #define XTHAL_INEXACT -2 950 /* The supplied address doesn't correspond to the start of a region. */ 951 #define XTHAL_INVALID_ADDRESS -3 952 /* This functionality is not available on this architecture. */ 953 #define XTHAL_UNSUPPORTED -4 954 /* Translation failed because vaddr and paddr were not aligned. */ 955 #define XTHAL_ADDRESS_MISALIGNED -5 956 /* There is mapping for the supplied address. */ 957 #define XTHAL_NO_MAPPING -6 958 /* The requested access rights are not supported */ 959 #define XTHAL_BAD_ACCESS_RIGHTS -7 960 /* The requested memory type is not supported */ 961 #define XTHAL_BAD_MEMORY_TYPE -8 962 /* The entries supplied are not properly aligned to the MPU's background map. */ 963 #define XTHAL_MAP_NOT_ALIGNED -9 964 /* There are not enough MPU entries available to do the requeste mapping. */ 965 #define XTHAL_OUT_OF_ENTRIES -10 966 /* The entries supplied are not properly ordered for the MPU. */ 967 #define XTHAL_OUT_OF_ORDER_MAP -11 968 /* an invalid argument such as a null pointer was supplied to the function */ 969 #define XTHAL_INVALID -12 970 /* specified region is of zero size, therefore no mapping is done. */ 971 #define XTHAL_ZERO_SIZED_REGION -13 972 /* specified range wraps around '0' */ 973 #define XTHAL_INVALID_ADDRESS_RANGE -14 974 975 /* 976 For backward compatibility we retain the following inconsistenly named 977 constants. Do not use them as they may be removed in a future release. 978 */ 979 #define XCHAL_SUCCESS XTHAL_SUCCESS 980 #define XCHAL_ADDRESS_MISALIGNED XTHAL_ADDRESS_MISALIGNED 981 #define XCHAL_INEXACT XTHAL_INEXACT 982 #define XCHAL_INVALID_ADDRESS XTHAL_INVALID_ADDRESS 983 #define XCHAL_UNSUPPORTED_ON_THIS_ARCH XTHAL_UNSUPPORTED 984 #define XCHAL_NO_PAGES_MAPPED XTHAL_NO_REGIONS_COVERED 985 986 987 /* Convert between virtual and physical addresses (through static maps only) 988 * WARNING: these two functions may go away in a future release; 989 * don't depend on them! 990 */ 991 extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp ); 992 extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached ); 993 994 extern int xthal_set_region_translation(void* vaddr, void* paddr, 995 unsigned size, unsigned cache_atr, unsigned flags); 996 extern int xthal_v2p(void*, void**, unsigned*, unsigned*); 997 extern int xthal_invalidate_region(void* addr); 998 extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr); 999 1000 /*------------------------------------------------------------------------ 1001 MPU (Memory Protection Unit) 1002 -------------------------------------------------------------------------*/ 1003 1004 /* 1005 * General notes on MPU (Memory Protection Unit): 1006 * 1007 * The MPU supports setting the access rights (read, write, execute) as 1008 * well as the memory type (cacheablity, ...) 1009 * for regions of memory. The granularity can be as small as 32 bytes. 1010 * (XCHAL_MPU_ALIGN specifies the granularity for any specific MPU config) 1011 * 1012 * The MPU doesn't support mapping between virtual and physical addresses. 1013 * 1014 * The MPU contains a fixed number of map changeable forground map entries, 1015 * and a background map which is fixed at configuration time. 1016 * 1017 * Each entry has a start address (up to 27 bits), valid flag, 1018 * access rights (4 bits), and memory type (9 bits); 1019 * 1020 */ 1021 1022 1023 /* 1024 MPU access rights constants: 1025 Only the combinations listed below are supported by the MPU. 1026 */ 1027 1028 #define XTHAL_AR_NONE 0 /* no access */ 1029 #define XTHAL_AR_R 4 /* Kernel read, User no access*/ 1030 #define XTHAL_AR_RX 5 /* Kernel read/execute, User no access */ 1031 #define XTHAL_AR_RW 6 /* Kernel read/write, User no access */ 1032 #define XTHAL_AR_RWX 7 /* Kernel read/write/execute, User no access */ 1033 #define XTHAL_AR_Ww 8 /* Kernel write, User write */ 1034 #define XTHAL_AR_RWrwx 9 /* Kernel read/write , User read/write/execute */ 1035 #define XTHAL_AR_RWr 10 /* Kernel read/write, User read */ 1036 #define XTHAL_AR_RWXrx 11 /* Kernel read/write/execute, User read/execute */ 1037 #define XTHAL_AR_Rr 12 /* Kernel read, User read */ 1038 #define XTHAL_AR_RXrx 13 /* Kernel read/execute, User read/execute */ 1039 #define XTHAL_AR_RWrw 14 /* Kernel read/write, User read/write */ 1040 #define XTHAL_AR_RWXrwx 15 /* Kernel read/write/execute, 1041 User read/write/execute */ 1042 1043 #define XTHAL_AR_WIDTH 4 /* # bits used to encode access rights */ 1044 1045 /* If the bit XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS is set in the accessRights 1046 * argument to xthal_mpu_set_region_attribute(), or to the cattr argument of 1047 * xthal_set_region_attribute() then the existing access rights for the first 1048 * byte of the region will be used as the access rights of the new region. 1049 */ 1050 #define XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS 0x00002000 1051 1052 /* If the bit XTHAL_MPU_USE_EXISTING_MEMORY_TYPE is set in the memoryType 1053 * argument to xthal_mpu_set_region_attribute(), or to the cattr argument of 1054 * xthal_set_region_attribute() then the existing memory type for the first 1055 * byte of the region will be used as the memory type of the new region. 1056 */ 1057 #define XTHAL_MPU_USE_EXISTING_MEMORY_TYPE 0x00004000 1058 1059 /* The following groups of constants are bit-wise or'd together to specify 1060 * the memory type as input to the macros and functions that accept an 1061 * unencoded memory type specifier: 1062 * XTHAL_ENCODE_MEMORY_TYPE, xthal_encode_memory_type, 1063 * xthal_mpu_set_region_attribute(), and xthal_set_region_attribute(). 1064 * 1065 * example: 1066 * XTHAL_MEM_DEVICE | XTHAL_MEM_INTERRUPTIBLE | XTHAL_MEM_SYSTEM_SHARABLE 1067 * 1068 * or 1069 * XTHAL_MEM_WRITEBACK | XTHAL_MEM_INNER_SHAREABLE 1070 * 1071 * If it is desired to specify different attributes for the system and 1072 * local cache, then macro XTHAL_MEM_PROC_CACHE is used: 1073 * 1074 * XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_WRITETHRU) 1075 * 1076 * indicates the shared cache is writeback, but the processor's local cache 1077 * is writethrough. 1078 * 1079 */ 1080 1081 /* The following group of constants are used to specify cache attributes of 1082 * an MPU entry. If the processors local cache and the system's shared cache 1083 * have the same attributes (or if there aren't distinct local and shared 1084 * caches) then the constant can be used directly. If different attributes 1085 * for the shared and local caches, then use these constants as the parameters 1086 * to the XTHAL_MEM_PROC_CACHE() macro. 1087 */ 1088 #define XTHAL_MEM_DEVICE 0x00008000 1089 #define XTHAL_MEM_NON_CACHEABLE 0x00090000 1090 #define XTHAL_MEM_WRITETHRU_NOALLOC 0x00080000 1091 #define XTHAL_MEM_WRITETHRU 0x00040000 1092 #define XTHAL_MEM_WRITETHRU_WRITEALLOC 0x00060000 1093 #define XTHAL_MEM_WRITEBACK_NOALLOC 0x00050000 1094 #define XTHAL_MEM_WRITEBACK 0x00070000 1095 1096 /* Indicates a read is interruptible. Only applicable to devices */ 1097 #define XTHAL_MEM_INTERRUPTIBLE 0x08000000 1098 1099 /* Indicates if writes to this memory are bufferable ... only applicable 1100 * to devices, and non-cacheable memory. 1101 */ 1102 #define XTHAL_MEM_BUFFERABLE 0x01000000 1103 1104 /* The following group of constants indicates the scope of the sharing of 1105 * the memory region. XTHAL_MEM_INNER_SHAREABLE and XTHAL_MEM_OUTER_SHARABLE are 1106 * only applicable to cacheable regions. XTHAL_MEM_SYSTEM_SHAREABLE is only 1107 * applicable to devices and non-cacheable regions. 1108 */ 1109 #define XTHAL_MEM_NON_SHAREABLE 0x00000000 1110 #define XTHAL_MEM_INNER_SHAREABLE 0x02000000 1111 #define XTHAL_MEM_OUTER_SHAREABLE 0x04000000 1112 #define XTHAL_MEM_SYSTEM_SHAREABLE 0x06000000 1113 1114 1115 /* 1116 * This macro is needed when the cache attributes are different for the shared 1117 * and processor's local caches. For example: 1118 * 1119 * XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_NON_CACHEABLE) 1120 * creates a memory type that is writeback cacheable in the system cache, and not 1121 * cacheable in the processor's local cache. 1122 */ 1123 #define XTHAL_MEM_PROC_CACHE(system, processor) \ 1124 (((system) & 0x000f0000) | (((processor) & 0x000f0000 ) << 4) | \ 1125 (((system) & XTHAL_MEM_DEVICE) | ((processor) & XTHAL_MEM_DEVICE))) 1126 1127 /* 1128 * This macro converts a bit-wise combination of the XTHAL_MEM_... constants 1129 * to the corresponding MPU memory type (9-bits). 1130 * 1131 * Unsupported combinations are mapped to the best available substitute. 1132 * 1133 * The same functionality plus error checking is available from 1134 * xthal_encode_memory_type(). 1135 */ 1136 #define XTHAL_ENCODE_MEMORY_TYPE(x) \ 1137 (((x) & 0xffffe000) ? \ 1138 (_XTHAL_MEM_IS_DEVICE((x)) ? _XTHAL_ENCODE_DEVICE((x)) : \ 1139 (_XTHAL_IS_SYSTEM_NONCACHEABLE((x)) ? \ 1140 _XTHAL_ENCODE_SYSTEM_NONCACHEABLE((x)) : \ 1141 _XTHAL_ENCODE_SYSTEM_CACHEABLE((x)))) : (x)) 1142 1143 /* 1144 * This structure is used to represent each MPU entry (both foreground and 1145 * background). The internal representation of the structure is subject to 1146 * change, so it should only be accessed by the XTHAL_MPU_ENTRY_... macros 1147 * below. 1148 */ 1149 typedef struct xthal_MPU_entry 1150 { 1151 uint32_t as; /* virtual start address, and valid bit */ 1152 uint32_t at; /* access rights, and memory type (and space for entry index) */ 1153 } xthal_MPU_entry; 1154 1155 extern const xthal_MPU_entry Xthal_mpu_bgmap[]; 1156 1157 1158 1159 1160 /* 1161 * XTHAL_MPU_ENTRY creates an MPU entry from its component values. It is 1162 * intended for initializing an MPU map. Example: 1163 * const struct xthal_MPU_entry mpumap[] = 1164 { XTHAL_MPU_ENTRY( 0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), 1165 XTHAL_MPU_ENTRY( 0xE0000000, 1, XTHAL_AR_RWXrwx, 1166 XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE), 1167 XTHAL_MPU_ENTRY( 0xF0000000, 1, XTHAL_AR_RWX, 1168 XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE) }; 1169 xthal_write_map(mpumap, sizeof(mpumap) / sizeof(struct xthal_MPU_entry)); 1170 * 1171 */ 1172 #define XTHAL_MPU_ENTRY(vaddr, valid, access, memtype) \ 1173 { (((vaddr) & 0xffffffe0) | ((valid & 0x1))), \ 1174 (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) << 12) | (((access) & 0xf) << 8)) } 1175 1176 /* 1177 * These macros get (or set) the specified field of the MPU entry. 1178 */ 1179 #define XTHAL_MPU_ENTRY_GET_VSTARTADDR(x) ((x).as & 0xffffffe0) 1180 1181 #define XTHAL_MPU_ENTRY_SET_VSTARTADDR(x, vaddr) (x).as = \ 1182 (((x).as) & 0x1) | ((vaddr) & 0xffffffe0) 1183 1184 #define XTHAL_MPU_ENTRY_GET_VALID(x) (((x).as & 0x1)) 1185 1186 #define XTHAL_MPU_ENTRY_SET_VALID(x, valid) (x).as = \ 1187 (((x).as & 0xfffffffe) | ((valid) & 0x1)) 1188 #define XTHAL_MPU_ENTRY_GET_ACCESS(x) ((((x).at) >> 8) & 0xf) 1189 1190 #define XTHAL_MPU_ENTRY_SET_ACCESS(x, accessRights) ((x).at = \ 1191 ((x).at & 0xfffff0ff) | (((accessRights) & 0xf) << 8)) 1192 1193 #define XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(x) ((((x).at) >> 12) & 0x1ff) 1194 1195 #define XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(x, memtype) ((x).at = \ 1196 ((x).at & 0xffe00fff) | (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) & 0x1ff) << 12)) 1197 1198 /* 1199 * These functions accept encoded access rights, and return 1 if the 1200 * supplied memory type has the property specified by the function name, 1201 * otherwise they return 0. 1202 */ 1203 extern int32_t xthal_is_kernel_readable(uint32_t accessRights); 1204 extern int32_t xthal_is_kernel_writeable(uint32_t accessRights); 1205 extern int32_t xthal_is_kernel_executable(uint32_t accessRights); 1206 extern int32_t xthal_is_user_readable(uint32_t accessRights); 1207 extern int32_t xthal_is_user_writeable (uint32_t accessRights); 1208 extern int32_t xthal_is_user_executable(uint32_t accessRights); 1209 1210 1211 /* 1212 * This function converts a bit-wise combination of the XTHAL_MEM_.. constants 1213 * to the corresponding MPU memory type (9-bits). 1214 * 1215 * If none of the XTHAL_MEM_.. bits are present in the argument, then 1216 * bits 4-12 (9-bits) are returned ... this supports using an already encoded 1217 * memoryType (perhaps obtained from an xthal_MPU_entry structure) as input 1218 * to xthal_set_region_attribute(). 1219 * 1220 * This function first checks that the supplied constants are a valid and 1221 * supported combination. If not, it returns XTHAL_BAD_MEMORY_TYPE. 1222 */ 1223 extern int xthal_encode_memory_type(uint32_t x); 1224 1225 /* 1226 * This function accepts a 9-bit memory type value (such as returned by 1227 * XTHAL_MEM_ENTRY_GET_MEMORY_TYPE() or xthal_encode_memory_type(). They 1228 * return 1 if the memoryType has the property specified in the function 1229 * name and 0 otherwise. 1230 */ 1231 extern int32_t xthal_is_cacheable(uint32_t memoryType); 1232 extern int32_t xthal_is_writeback(uint32_t memoryType); 1233 extern int32_t xthal_is_device(uint32_t memoryType); 1234 1235 /* 1236 * Copies the current MPU entry list into 'entries' which 1237 * must point to available memory of at least 1238 * sizeof(struct xthal_MPU_entry) * XCHAL_MPU_ENTRIES. 1239 * 1240 * This function returns XTHAL_SUCCESS. 1241 * XTHAL_INVALID, or 1242 * XTHAL_UNSUPPORTED. 1243 */ 1244 extern int32_t xthal_read_map(struct xthal_MPU_entry* entries); 1245 1246 /* 1247 * Writes the map pointed to by 'entries' to the MPU. Before updating 1248 * the map, it commits any uncommitted 1249 * cache writes, and invalidates the cache if necessary. 1250 * 1251 * This function does not check for the correctness of the map. Generally 1252 * xthal_check_map() should be called first to check the map. 1253 * 1254 * If n == 0 then the existing map is cleared, and no new map is written 1255 * (useful for returning to reset state) 1256 * 1257 * If (n > 0 && n < XCHAL_MPU_ENTRIES) then a new map is written with 1258 * (XCHAL_MPU_ENTRIES-n) padding entries added to ensure a properly ordered 1259 * map. The resulting foreground map will be equivalent to the map vector 1260 * fg, but the position of the padding entries should not be relied upon. 1261 * 1262 * If n == XCHAL_MPU_ENTRIES then the complete map as specified by fg is 1263 * written. 1264 * 1265 * The CACHEADRDIS register will be set to enable caching any 512MB region 1266 * that is overlapped by an MPU region with a cacheable memory type. 1267 * Caching will be disabled if none of the 512 MB region is cacheable. 1268 * 1269 * xthal_write_map() disables the MPU foreground map during the MPU 1270 * update and relies on the background map. 1271 * 1272 * As a result any interrupt that does not meet the following conditions 1273 * must be disabled before calling xthal_write_map(): 1274 * 1) All code and data needed for the interrupt must be 1275 * mapped by the background map with sufficient access rights. 1276 * 2) The interrupt code must not access the MPU. 1277 * 1278 */ 1279 extern void xthal_write_map(const struct xthal_MPU_entry* entries, uint32_t n); 1280 1281 /* 1282 * Checks if entry vector 'entries' of length 'n' is a valid MPU access map. 1283 * Returns: 1284 * XTHAL_SUCCESS if valid, 1285 * XTHAL_OUT_OF_ENTRIES 1286 * XTHAL_MAP_NOT_ALIGNED, 1287 * XTHAL_BAD_ACCESS_RIGHTS, 1288 * XTHAL_OUT_OF_ORDER_MAP, or 1289 * XTHAL_UNSUPPORTED if config doesn't have an MPU. 1290 */ 1291 extern int xthal_check_map(const struct xthal_MPU_entry* entries, uint32_t n); 1292 1293 /* 1294 * Returns the MPU entry that maps 'vaddr'. If 'infgmap' is non-NULL then 1295 * *infgmap is set to 1 if 'vaddr' is mapped by the foreground map, and 1296 * *infgmap is set to 0 if 'vaddr' is mapped by the background map. 1297 */ 1298 extern struct xthal_MPU_entry xthal_get_entry_for_address(void* vaddr, 1299 int32_t* infgmap); 1300 1301 /* 1302 * Scans the supplied MPU map and returns a value suitable for writing to 1303 * the CACHEADRDIS register: 1304 * Bits 0-7 -> 1 if there are no cacheable areas in the corresponding 512MB 1305 * region and 0 otherwise. 1306 * Bits 8-31 -> undefined. 1307 * This function can accept a partial memory map in the same manner 1308 * xthal_write_map() does, */ 1309 extern uint32_t 1310 xthal_calc_cacheadrdis(const struct xthal_MPU_entry* e, uint32_t n); 1311 1312 /* 1313 * This function is intended as an MPU specific version of 1314 * xthal_set_region_attributes(). xthal_set_region_attributes() calls 1315 * this function for MPU configurations. 1316 * 1317 * This function sets the attributes for the region [vaddr, vaddr+size) 1318 * in the MPU. 1319 * 1320 * Depending on the state of the MPU this function will require from 1321 * 0 to 3 unused MPU entries. 1322 * 1323 * This function typically will move, add, and subtract entries from 1324 * the MPU map during execution, so that the resulting map may 1325 * be quite different than when the function was called. 1326 * 1327 * This function does make the following guarantees: 1328 * 1) The MPU access map remains in a valid state at all times 1329 * during its execution. 1330 * 2) At all points during (and after) completion the memoryType 1331 * and accessRights remain the same for all addresses 1332 * that are not in the range [vaddr, vaddr+size). 1333 * 3) If XTHAL_SUCCESS is returned, then the range 1334 * [vaddr, vaddr+size) will have the accessRights and memoryType 1335 * specified. 1336 * 4) The CACHEADRDIS register will be set to enable caching any 512MB region 1337 * that is overlapped by an MPU region with a cacheable memory type. 1338 * Caching will be disabled if none of the 512 MB region is cacheable. 1339 * 1340 * The accessRights parameter should be either a 4-bit value corresponding 1341 * to an MPU access mode (as defined by the XTHAL_AR_.. constants), or 1342 * XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS. 1343 * 1344 * The memoryType parameter should be either a bit-wise or-ing of XTHAL_MEM_.. 1345 * constants that represent a valid MPU memoryType, a 9-bit MPU memoryType 1346 * value, or XTHAL_MPU_USE_EXISTING_MEMORY_TYPE. 1347 * 1348 * In addition to the error codes that xthal_set_region_attribute() 1349 * returns, this function can also return: XTHAL_BAD_ACCESS_RIGHTS 1350 * (if the access rights bits map to an unsupported combination), or 1351 * XTHAL_OUT_OF_MAP_ENTRIES (if there are not enough unused MPU entries) 1352 * 1353 * If this function is called with an invalid MPU map, then this function 1354 * will return one of the codes that is returned by xthal_check_map(). 1355 * 1356 * The flag, XTHAL_CAFLAG_EXPAND, is not supported 1357 * 1358 */ 1359 1360 extern int xthal_mpu_set_region_attribute(void* vaddr, size_t size, 1361 int32_t accessRights, int32_t memoryType, uint32_t flags); 1362 1363 /* The following are internal implementation macros. These should not 1364 * be directly used except by the hal code and headers. 1365 */ 1366 1367 /* 1368 * Layout of the MPU specifier for: XTHAL_ENCODE_MEMORY_TYPE(), 1369 * xthal_encode_memory_type(), xthal_set_region_attribute(), 1370 * and xthal_mpu_set_region_attribute(). THIS IS SUBJECT TO CHANGE: 1371 * 1372 * Bits 0-3 - reserved for pass through of accessRights 1373 * Bits 4-12 - reserved for pass through of memoryType bits 1374 * Bit 13 - indicates to use existing access rights of region 1375 * Bit 14 - indicates to use existing memory type of region 1376 * Bit 15 - indicates device 1377 * Bit 16-19- system cache properties 1378 * Bit 20-23- local cache properties 1379 * Bit 24 - indicates bufferable 1380 * Bit 25-26- encodes shareability (1=inner, 2=outer, 3=system) 1381 * Bit 27 - indicates interruptible 1382 * Bits 28-31- reserved for future use 1383 */ 1384 #define _XTHAL_SYSTEM_CACHE_BITS 0x000f0000 1385 #define _XTHAL_LOCAL_CACHE_BITS 0x00f00000 1386 #define _XTHAL_MEM_SYSTEM_RWC_MASK 0x00070000 1387 #define _XTHAL_MEM_LOCAL_RWC_MASK 0x00700000 1388 #define _XTHAL_SHIFT_RWC 16 1389 1390 #define _XTHAL_MEM_ANY_SHAREABLE(x) (((x) & XTHAL_MEM_SYSTEM_SHAREABLE) ? 1 : 0) 1391 1392 #define _XTHAL_MEM_INNER_SHAREABLE(x) ((((x) & XTHAL_MEM_SYSTEM_SHAREABLE) \ 1393 == XTHAL_MEM_INNER_SHAREABLE) ? 1 : 0) 1394 1395 #define _XTHAL_MEM_IS_BUFFERABLE(x) (((x) & XTHAL_MEM_BUFFERABLE) ? 1 : 0) 1396 1397 #define _XTHAL_MEM_IS_DEVICE(x) (((x) & XTHAL_MEM_DEVICE) ? 1 : 0) 1398 1399 #define _XTHAL_NON_CACHEABLE_DOMAIN(x) \ 1400 (_XTHAL_MEM_IS_DEVICE(x) || _XTHAL_MEM_ANY_SHAREABLE(x)? 0x3 : 0) 1401 1402 #define _XTHAL_CACHEABLE_DOMAIN(x) (_XTHAL_MEM_ANY_SHAREABLE(x) ? \ 1403 0x3 : 0x1) 1404 1405 #define _XTHAL_MEM_CACHE_MASK(x) ((x) & _XTHAL_SYSTEM_CACHE_BITS) 1406 1407 #define _XTHAL_IS_SYSTEM_NONCACHEABLE(x) \ 1408 (((_XTHAL_MEM_CACHE_MASK(x) & XTHAL_MEM_NON_CACHEABLE) == \ 1409 XTHAL_MEM_NON_CACHEABLE) ? 1 : 0) 1410 1411 #define _XTHAL_ENCODE_DEVICE(x) \ 1412 (((((x) & XTHAL_MEM_INTERRUPTIBLE) ? 1 : 0) << 3) | \ 1413 (_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) | _XTHAL_MEM_IS_BUFFERABLE(x)) 1414 1415 #define _XTHAL_ENCODE_SYSTEM_NONCACHEABLE(x) \ 1416 (0x18 | (_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) \ 1417 | _XTHAL_MEM_IS_BUFFERABLE(x)) 1418 1419 #define _XTHAL_ENCODE_SYSTEM_CACHEABLE(x) \ 1420 (((((((x) & _XTHAL_LOCAL_CACHE_BITS) >> 4) & XTHAL_MEM_NON_CACHEABLE) == \ 1421 XTHAL_MEM_NON_CACHEABLE) ? 1 : 0) ? \ 1422 (_XTHAL_CACHEABLE_DOMAIN(x) << 4) : \ 1423 _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x)) | \ 1424 ((_XTHAL_MEM_INNER_SHAREABLE(x) << 3) | \ 1425 (_XTHAL_MEM_CACHE_MASK(x) & _XTHAL_MEM_SYSTEM_RWC_MASK) \ 1426 >> _XTHAL_SHIFT_RWC) 1427 1428 #define _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x) \ 1429 ((_XTHAL_CACHEABLE_DOMAIN(x) << 7) | (((((x) & _XTHAL_LOCAL_CACHE_BITS) ? \ 1430 ((x) & _XTHAL_LOCAL_CACHE_BITS) : \ 1431 (_XTHAL_MEM_CACHE_MASK(x) << 4)) \ 1432 & (_XTHAL_MEM_LOCAL_RWC_MASK)) >> _XTHAL_SHIFT_RWC )) 1433 1434 /* End of internal macros */ 1435 1436 /* The functions and constants below here have been deprecated.*/ 1437 #define XTHAL_MEM_NON_CACHED XTHAL_MEM_NON_CACHEABLE 1438 #define XTHAL_MEM_NON_SHARED XTHAL_MEM_NON_SHAREABLE 1439 #define XTHAL_MEM_INNER_SHARED XTHAL_MEM_INNER_SHAREABLE 1440 #define XTHAL_MEM_OUTER_SHARED XTHAL_MEM_OUTER_SHAREABLE 1441 #define XTHAL_MEM_SYSTEM_SHARED XTHAL_MEM_SYSTEM_SHAREABLE 1442 #define XTHAL_MEM_SW_SHAREABLE 0 1443 1444 #define xthal_is_cached(memoryType) (xthal_is_cacheable((memoryType))) 1445 extern int32_t xthal_read_background_map(struct xthal_MPU_entry* entries); 1446 1447 /* end deprecated functions and constants */ 1448 1449 #ifdef __cplusplus 1450 } 1451 #endif 1452 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ 1453 1454 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 1455 1456 1457 1458 1459 /**************************************************************************** 1460 EXPERIMENTAL and DEPRECATED Definitions 1461 ****************************************************************************/ 1462 1463 1464 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 1465 #ifdef __cplusplus 1466 extern "C" { 1467 #endif 1468 1469 #ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE 1470 #define XTHAL_24_BIT_BREAK 0x80000000 1471 #define XTHAL_16_BIT_BREAK 0x40000000 1472 extern const unsigned short Xthal_ill_inst_16[16]; 1473 #define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */ 1474 #define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */ 1475 #define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */ 1476 #define XTHAL_RFW_INST 0x00000800 1477 #define XTHAL_RFUE_INST 0x00000400 1478 #define XTHAL_RFI_INST 0x00000200 1479 #define XTHAL_RFE_INST 0x00000100 1480 #define XTHAL_RET_INST 0x00000080 1481 #define XTHAL_BREAK_INST 0x00000040 1482 #define XTHAL_SYSCALL_INST 0x00000020 1483 #define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */ 1484 #define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */ 1485 #define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */ 1486 #define XTHAL_24_BIT_INST 0x00000002 1487 #define XTHAL_16_BIT_INST 0x00000001 1488 typedef struct xthal_state { 1489 unsigned pc; 1490 unsigned ar[16]; 1491 unsigned lbeg; 1492 unsigned lend; 1493 unsigned lcount; 1494 unsigned extra_ptr; 1495 unsigned cpregs_ptr[XTHAL_MAX_CPS]; 1496 } XTHAL_STATE; 1497 extern unsigned int xthal_inst_type(void *addr); 1498 extern unsigned int xthal_branch_addr(void *addr); 1499 extern unsigned int xthal_get_npc(XTHAL_STATE *user_state); 1500 #endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */ 1501 1502 #ifdef __cplusplus 1503 } 1504 #endif 1505 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ 1506 1507 #endif /*XTENSA_HAL_H*/ 1508
