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Searched defs:XSHAL_ISS_CACHEATTR_DEFAULT (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dsystem.h181 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dsystem.h181 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dsystem.h181 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dsystem.h198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dsystem.h187 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dsystem.h198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dsystem.h198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dsystem.h186 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dsystem.h187 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dsystem.h187 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dsystem.h202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dsystem.h202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dsystem.h202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK macro