1 /**
2 * @file xmc_i2s.c
3 * @date 2019-05-07
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-08-21:
40 * - Initial <br>
41 *
42 * 2015-09-01:
43 * - Modified XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() for supporting multiple events configuration<br>
44 *
45 * 2015-09-14:
46 * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length.
47 * - Removed parity configuration<br>
48 *
49 * 2015-09-28:
50 * - Fixed bugs in the XMC_I2S_CH_Init() and in the ASSERTs <br>
51 *
52 * 2015-11-04:
53 * - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_I2S_CH_Transmit() API <br>
54 *
55 * 2016-06-30:
56 * - Modified XMC_I2S_CH_Init:
57 * + change default passive level to 0
58 * + Call XMC_I2S_CH_SetSystemWordLength() to set the system frame length equal to the frame length.
59 * - Modified XMC_I2S_CH_SetBaudrate:
60 * + Optional Master clock output signal generated with a fixed phase relation to SCLK.
61 *
62 * 2019-05-07:
63 * - Added XMC_I2S_CH_SetBaudrateEx() which allows to select between baudrate generator normal divider and fractional divider mode
64 *
65 * @endcond
66 *
67 */
68 /**
69 *
70 * @brief I2S driver for XMC microcontroller family
71 *
72 */
73 /*********************************************************************************************************************
74 * HEADER FILES
75 ********************************************************************************************************************/
76
77 #include <xmc_scu.h>
78 #include <xmc_i2s.h>
79
80 /*********************************************************************************************************************
81 * MACROS
82 ********************************************************************************************************************/
83 /* To take into account the SCLK divider by 2 and the PPPEN divider (see Divider Mode Counter figure in RM) */
84 #define XMC_I2S_CH_OVERSAMPLING (4UL)
85
86 /*********************************************************************************************************************
87 * API IMPLEMENTATION
88 ********************************************************************************************************************/
89
90 /* Initializes the selected I2S channel with the config structure. */
XMC_I2S_CH_Init(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_CONFIG_t * const config)91 void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config)
92 {
93 XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(config->data_delayed_sclk_periods > 0U) &&
94 (config->data_delayed_sclk_periods < config->frame_length));
95 XMC_USIC_CH_Enable(channel);
96
97 if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER)
98 {
99 /* Configure baud rate */
100 (void)XMC_I2S_CH_SetBaudrateEx(channel, config->baudrate, config->normal_divider_mode);
101 }
102 /* Configuration of USIC Shift Control */
103 /* Transmission Mode (TRM) = 1 */
104 channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) |
105 (uint32_t)((config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos) |
106 (uint32_t)((config->data_bits - 1U) << USIC_CH_SCTR_WLE_Pos) |
107 USIC_CH_SCTR_SDIR_Msk;
108
109 /* Configuration of USIC Transmit Control/Status Register */
110 /* TBUF Data Enable (TDEN) = 1 */
111 /* TBUF Data Single Shot Mode (TDSSM) = 1 */
112 /* WA mode enabled(WAMD) = 1 */
113 channel->TCSR = (uint32_t)((channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk |
114 USIC_CH_TCSR_SELMD_Msk |
115 USIC_CH_TCSR_FLEMD_Msk |
116 USIC_CH_TCSR_HPCMD_Msk))) |
117 USIC_CH_TCSR_WAMD_Msk |
118 (0x01UL << USIC_CH_TCSR_TDEN_Pos) |
119 USIC_CH_TCSR_TDSSM_Msk);
120
121 if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER)
122 {
123 /* Configuration of Protocol Control Register */
124 channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk;
125 }
126
127 /* Configuration of Protocol Control Register */
128 channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk |
129 (uint32_t)config->wa_inversion) |
130 ((uint32_t)((uint32_t)config->data_delayed_sclk_periods - 1U) << USIC_CH_PCR_IISMode_TDEL_Pos);
131
132 XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length);
133
134 /* Clear protocol status */
135 channel->PSCR = 0xFFFFFFFFUL;
136 }
137
138
XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t * const channel,const uint32_t rate)139 XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate)
140 {
141 XMC_I2S_CH_STATUS_t status;
142
143 status = XMC_I2S_CH_STATUS_ERROR;
144
145 if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U))
146 {
147 if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK)
148 {
149 channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) |
150 (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) |
151 USIC_CH_BRG_PPPEN_Msk;
152
153 status = XMC_I2S_CH_STATUS_OK;
154 }
155
156 }
157 return status;
158 }
159
XMC_I2S_CH_SetBaudrateEx(XMC_USIC_CH_t * const channel,const uint32_t rate,bool normal_divider_mode)160 XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, bool normal_divider_mode)
161 {
162 XMC_USIC_CH_STATUS_t status;
163
164 if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U))
165 {
166 if (normal_divider_mode)
167 {
168 status = XMC_USIC_CH_SetBaudrateEx(channel, rate, XMC_I2S_CH_OVERSAMPLING);
169 }
170 else
171 {
172 status = XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING);
173 }
174
175 if (status == XMC_USIC_CH_STATUS_OK)
176 {
177 channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) |
178 (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) |
179 USIC_CH_BRG_PPPEN_Msk;
180 }
181 }
182 else
183 {
184 status = XMC_USIC_CH_STATUS_ERROR;
185 }
186
187 return (XMC_I2S_CH_STATUS_t)status;
188 }
189
XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t * const channel,uint32_t sclk_cycles_system_word_length)190 void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length)
191 {
192 uint32_t sclk_cycles_system_word_length_temp;
193 uint8_t dctq_temp;
194 uint8_t pctq_temp;
195 uint8_t dctq = 1U;
196 uint8_t pctq = 1U;
197 uint8_t best_error = 64U;
198 uint8_t error;
199 XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(sclk_cycles_system_word_length > 0U) && (sclk_cycles_system_word_length < 65U));
200
201
202 for (dctq_temp =1U; dctq_temp < 33U ; dctq_temp++)
203 {
204 for (pctq_temp =1U; pctq_temp < 5U ; pctq_temp++)
205 {
206 sclk_cycles_system_word_length_temp = ((uint32_t)dctq_temp) * ((uint32_t)pctq_temp);
207 if(sclk_cycles_system_word_length_temp == sclk_cycles_system_word_length)
208 {
209 dctq = dctq_temp;
210 pctq = pctq_temp;
211 break;
212 }
213 if (sclk_cycles_system_word_length_temp > sclk_cycles_system_word_length)
214 {
215 error = (uint8_t)(sclk_cycles_system_word_length_temp - sclk_cycles_system_word_length);
216 }
217 else
218 {
219 error = (uint8_t)(sclk_cycles_system_word_length - sclk_cycles_system_word_length_temp);
220 }
221
222 if(error < best_error)
223 {
224 best_error = error;
225 dctq = dctq_temp;
226 pctq = pctq_temp;
227 }
228 }
229 }
230 channel->BRG = (uint32_t)((channel->BRG & ~((uint32_t)(USIC_CH_BRG_DCTQ_Msk |
231 USIC_CH_BRG_PCTQ_Msk))) |
232 (uint32_t)((uint32_t)((uint32_t)((uint32_t)dctq- 1U) << USIC_CH_BRG_DCTQ_Pos) |
233 (uint32_t)((uint32_t)((uint32_t)pctq- 1U) << USIC_CH_BRG_PCTQ_Pos)));
234 }
235
236 /* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */
XMC_I2S_CH_Transmit(XMC_USIC_CH_t * const channel,const uint16_t data,const XMC_I2S_CH_CHANNEL_t channel_number)237 void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number)
238 {
239 /* Check FIFO size */
240 if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
241 {
242 while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
243 {
244 }
245
246 XMC_I2S_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
247
248 channel->TBUF[(uint32_t)channel_number << 4] = data;
249 }
250 else
251 {
252 channel->IN[(uint32_t)channel_number << 4] = data;
253 }
254 }
255
256 /* Reads the data from the buffers based on the FIFO mode selection. */
XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t * const channel)257 uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
258 {
259 uint16_t retval;
260
261 /* Check FIFO size */
262 if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
263 {
264 retval = (uint16_t)channel->RBUF;
265 }
266 else
267 {
268 retval = (uint16_t)channel->OUTR;
269 }
270
271 return retval;
272 }
273
XMC_I2S_CH_Stop(XMC_USIC_CH_t * const channel)274 XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel)
275 {
276 XMC_I2S_CH_STATUS_t status = XMC_I2S_CH_STATUS_OK;
277
278 if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
279 {
280 status = XMC_I2S_CH_STATUS_BUSY;
281 }
282 else
283 {
284 /* USIC channel in IDLE mode */
285 XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
286 }
287
288 return status;
289 }
290
XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)291 void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
292 {
293 channel->CCR |= (event&0x1fc00U);
294 channel->PCR_IISMode |= ((event >> 2U) & 0x8070U);
295 }
296
XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)297 void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
298 {
299 channel->CCR &= (uint32_t)~(event&0x1fc00U);
300 channel->PCR_IISMode &= (uint32_t)~((event >> 2U) & 0x8070U);
301 }
302
