1 /**
2 * @file xmc_i2s.h
3 * @date 2019-05-07
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-08-21:
40 * - Initial <br>
41 *
42 * 2015-08-24:
43 * - Added APIs for enabling/disabling delay compensation XMC_I2S_CH_DisableDelayCompensation() and
44 * XMC_I2S_CH_EnableDelayCompensation() <br>
45 *
46 * 2015-09-01:
47 * - Modified XMC_I2S_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
48 * - Modified XMC_I2S_CH_EVENT_t enum for supporting XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() <br>
49 * for supporting multiple events configuration <br>
50 *
51 * 2015-09-14:
52 * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length<br>
53 *
54 * 2016-05-20:
55 * - Added XMC_I2S_CH_EnableDataTransmission() and XMC_I2S_CH_DisableDataTransmission()
56 *
57 * 2016-06-30:
58 * - Documentation updates.
59 *
60 * 2019-05-07:
61 * - Added normal_divider_mode to XMC_I2S_CH_CONFIG_t configuration structure.
62 * It selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection
63 * - Added XMC_I2S_CH_SetBaudrateEx()
64 *
65 *
66 * @endcond
67 *
68 */
69
70 #ifndef XMC_I2S_H_
71 #define XMC_I2S_H_
72
73 /**********************************************************************************************************************
74 * HEADER FILES
75 *********************************************************************************************************************/
76 #include "xmc_usic.h"
77
78 /**
79 * @addtogroup XMClib XMC Peripheral Library
80 * @{
81 */
82
83 /**
84 * @addtogroup I2S
85 * @brief (IIS) driver for the XMC microcontroller family.
86 *
87 * USIC IIS Features: <br>
88 * @{
89 */
90
91 /*******************************************************************************
92 * MACROS
93 *******************************************************************************/
94
95 #if defined(USIC0)
96 #define XMC_I2S0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
97 #define XMC_I2S0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
98 #endif
99
100 #if defined(USIC1)
101 #define XMC_I2S1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
102 #define XMC_I2S1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
103 #endif
104
105 #if defined(USIC2)
106 #define XMC_I2S2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
107 #define XMC_I2S2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
108 #endif
109 /*******************************************************************************
110 * ENUMS
111 *******************************************************************************/
112
113 /**
114 * @brief I2S Status
115 */
116 typedef enum XMC_I2S_CH_STATUS
117 {
118 XMC_I2S_CH_STATUS_OK, /**< Status OK */
119 XMC_I2S_CH_STATUS_ERROR, /**< Status ERROR */
120 XMC_I2S_CH_STATUS_BUSY /**< Status BUSY */
121 } XMC_I2S_CH_STATUS_t;
122
123 /**
124 * @brief I2S status flag
125 */
126 typedef enum XMC_I2S_CH_STATUS_FLAG
127 {
128 XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS = USIC_CH_PSR_IISMode_WA_Msk, /**< Word Address status */
129 XMC_I2S_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_IISMode_DX2S_Msk, /**< Status of WA input(DX2) signal*/
130 XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_IISMode_DX2TEV_Msk, /**< Status for WA input signal transition */
131 XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT = USIC_CH_PSR_IISMode_WAFE_Msk, /**< Falling edge of the WA output
132 signal has been generated */
133 XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT = USIC_CH_PSR_IISMode_WARE_Msk, /**< Rising edge of the WA output
134 signal has been generated */
135 XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END = USIC_CH_PSR_IISMode_END_Msk, /**< The WA generation has ended */
136 XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IISMode_RSIF_Msk, /**< Receive start indication status */
137 XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IISMode_DLIF_Msk, /**< Data lost indication status */
138 XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IISMode_TSIF_Msk, /**< Transmit shift indication status */
139 XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IISMode_TBIF_Msk, /**< Transmit buffer indication status */
140 XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_RIF_Msk, /**< Receive indication status */
141 XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_AIF_Msk, /**< Alternate receive indication status */
142 XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IISMode_BRGIF_Msk /**< Baud rate generator indication status */
143 } XMC_I2S_CH_STATUS_FLAG_t;
144
145 /**
146 * @brief I2S Baudrate Generator shift clock output
147 */
148 typedef enum XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT
149 {
150 XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/
151 XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/
152 } XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t;
153
154 /**
155 * @brief I2S channel interrupt node pointers
156 */
157 typedef enum XMC_I2S_CH_INTERRUPT_NODE_POINTER
158 {
159 XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
160 XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
161 XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
162 XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
163 XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
164 } XMC_I2S_CH_INTERRUPT_NODE_POINTER_t;
165
166 /**
167 * @brief I2S events
168 */
169 typedef enum XMC_I2S_CH_EVENT
170 {
171 XMC_I2S_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
172 XMC_I2S_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
173 XMC_I2S_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
174 XMC_I2S_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
175 XMC_I2S_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
176 XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
177 XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
178
179 XMC_I2S_CH_EVENT_WA_FALLING_EDGE = USIC_CH_PCR_IISMode_WAFEIEN_Msk << 2U, /**< WA falling edge event */
180 XMC_I2S_CH_EVENT_WA_RISING_EDGE = USIC_CH_PCR_IISMode_WAREIEN_Msk << 2U, /**< WA rising edge event */
181 XMC_I2S_CH_EVENT_WA_GENERATION_END = USIC_CH_PCR_IISMode_ENDIEN_Msk << 2U, /**< END event */
182 XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_IISMode_DX2TIEN_Msk << 2U /**< WA input signal transition event*/
183 } XMC_I2S_CH_EVENT_t;
184
185 /**
186 * @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.
187 */
188 typedef enum XMC_I2S_CH_WA_POLARITY
189 {
190 XMC_I2S_CH_WA_POLARITY_DIRECT = 0x0UL, /**< The SELO outputs have the same polarity
191 as the WA signal (active high) */
192 XMC_I2S_CH_WA_POLARITY_INVERTED = 0x1UL << USIC_CH_PCR_IISMode_SELINV_Pos /**< The SELO outputs have the inverted
193 polarity to the WA signal (active low)*/
194 } XMC_I2S_CH_WA_POLARITY_t;
195
196 /**
197 * @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.
198 */
199 typedef enum XMC_I2S_CH_CHANNEL
200 {
201 XMC_I2S_CH_CHANNEL_1_LEFT = 0U, /**< Channel 1 (left) */
202 XMC_I2S_CH_CHANNEL_2_RIGHT = 1U /**< Channel 2 (right) */
203 } XMC_I2S_CH_CHANNEL_t;
204
205 /**
206 * @brief I2S input stage selection
207 */
208 typedef enum XMC_I2S_CH_INPUT
209 {
210 XMC_I2S_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */
211 XMC_I2S_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */
212 XMC_I2S_CH_INPUT_SLAVE_WA = 2UL, /**< WA input stage */
213 #if UC_FAMILY == XMC1
214 XMC_I2S_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */
215 XMC_I2S_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */
216 XMC_I2S_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */
217 #endif
218 } XMC_I2S_CH_INPUT_t;
219
220 /**
221 * @brief Defines the I2S bus mode
222 */
223 typedef enum XMC_I2S_CH_BUS_MODE
224 {
225 XMC_I2S_CH_BUS_MODE_MASTER, /**< I2S Master */
226 XMC_I2S_CH_BUS_MODE_SLAVE /**< I2S Slave */
227 } XMC_I2S_CH_BUS_MODE_t;
228
229 /*******************************************************************************
230 * DATA STRUCTURES
231 *******************************************************************************/
232 /**
233 * @brief I2S_CH configuration structure
234 */
235 typedef struct XMC_I2S_CH_CONFIG
236 {
237 uint32_t baudrate; /**< Module baud rate for communication */
238 bool normal_divider_mode; /**< Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection */
239 uint8_t data_bits; /**< Data word length. A data frame can consists of several data words. \n
240 Value configured as USIC channel word length. \n
241 \b Range: minimum= 1, maximum= 16*/
242 uint8_t frame_length; /**< Number of data bits transferred after a change of signal WA (data frame). \n
243 Configured as USIC channel frame length. \n
244 \b Range: minimum= 1, maximum= 63*/
245 uint8_t data_delayed_sclk_periods; /**< Data delay defined in sclk periods */
246 XMC_I2S_CH_WA_POLARITY_t wa_inversion; /**< Enable inversion of Slave select signal relative to the internal WA */
247 XMC_I2S_CH_BUS_MODE_t bus_mode; /**< Bus mode MASTER/SLAVE */
248 } XMC_I2S_CH_CONFIG_t;
249
250 /*******************************************************************************
251 * API PROTOTYPES
252 *******************************************************************************/
253
254 #ifdef __cplusplus
255 extern "C" {
256 #endif
257
258 /**
259 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
260 * \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
261 * @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t.
262 * @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n
263 * \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n
264 * @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed.
265 *
266 * \par<b>Description</b><br>
267 * Initializes the USIC channel for I2S protocol.\n\n
268 * During the initialization, USIC channel is enabled and baudrate is configured.
269 * After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length).
270 * The number of data bits transferred after a change of signal WA is defined by config->frame_length.
271 * A data frame can consist of several data words with a data word length defined by config->data_bits.
272 * The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA.
273 * The system word length is set by default to the frame length defined by config->frame_length.
274 *
275 * XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel.
276 *
277 * \par<b>Related APIs:</b><BR>
278 * XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n
279 */
280 void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config);
281
282 /**
283 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
284 *
285 * @return None
286 *
287 * \par<b>Description:</b><br>
288 * Set the selected USIC channel to operate in I2S mode, by setting CCR.MODE bits.\n\n
289 * It should be executed after XMC_I2S_CH_Init() during initialization. By invoking XMC_I2S_CH_Stop(), the MODE is set
290 * to IDLE state. Call XMC_I2S_CH_Start() to set the I2S mode again, as needed later in the program.
291 *
292 * \par<b>Related APIs:</b><BR>
293 * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()
294 */
XMC_I2S_CH_Start(XMC_USIC_CH_t * const channel)295 __STATIC_INLINE void XMC_I2S_CH_Start(XMC_USIC_CH_t *const channel)
296 {
297 /* USIC channel in I2S mode */
298 XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2S);
299 }
300
301 /**
302 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
303 *
304 * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for stopping is processed. \n
305 * XMC_I2S_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n
306 * XMC_I2S_CH_STATUS_BUSY- If the USIC channel is busy transmitting data.
307 *
308 * \par<b>Description:</b><br>
309 * Set the selected I2S channel to IDLE mode, by clearing CCR.MODE bits.\n\n
310 * After calling XMC_I2S_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_I2S_CH_Start() has to be
311 * invoked to start the communication again.
312 *
313 * \par<b>Related APIs:</b><BR>
314 * XMC_I2S_CH_Start()
315 */
316 XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel);
317
318 /**
319 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
320 * @param rate Bus speed in bits per second
321 *
322 * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed. \n
323 * XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed. \n
324 * XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range.
325 *
326 * \par<b>Description:</b><br>
327 * Sets the bus speed in bits per second
328 *
329 * \par<b>Related APIs:</b><BR>
330 * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()
331 */
332 XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
333
334 /**
335 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
336 * @param rate Bus speed in bits per second
337 * @param normal_divider_mode Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection
338 *
339 * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed. \n
340 * XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed. \n
341 * XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range.
342 *
343 * \par<b>Description:</b><br>
344 * Sets the bus speed in bits per second
345 *
346 * \par<b>Related APIs:</b><BR>
347 * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()
348 */
349 XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, bool normal_divider_mode);
350
351 /**
352 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
353 * @param sclk_cycles_system_word_length system word length in terms of sclk clock cycles.
354 *
355 * @return None
356 *
357 * \par<b>Description:</b><br>
358 * Configures the system word length by setting BRG.DCTQ bit field.\n\n
359 * This value has to be always higher than 1U and lower than the data with (SCTR.FLE)
360 *
361 */
362 void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length);
363
364 /**
365 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
366 * @param data Data to be transmitted
367 * @param channel_number Communication output channel of the I2S, based on this channel selection TCI(Transmit control information)is updated.\n
368 * Refer @ref XMC_I2S_CH_CHANNEL_t for valid values.
369 *
370 * @return None
371 *
372 * \par<b>Description:</b><br>
373 * Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n
374 * TCI(Transmit Control Information) allows dynamic control of output channel during data transfers. To support this auto
375 * update, TCSR.WAMD(Automatic WA mode) will be enabled during the initialization using XMC_I2S_CH_Init() for all modes.
376 *
377 *
378 * \par<b>Related APIs:</b><BR>
379 * XMC_I2S_CH_Receive()
380 */
381 void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number);
382
383 /**
384 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
385 * @param channel_number Communication output channel of the I2S, based on this mode TCI(Transmit control information)is updated.\n
386 * Refer @ref XMC_I2S_CH_CHANNEL_t for valid values.
387 *
388 * @return None
389 *
390 * \par<b>Description:</b><br>
391 * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n
392 * XMC_I2S_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data
393 * XMC_I2S_CH_GetReceivedData() can be invoked to read the data from the buffers.
394 *
395 * \par<b>Related APIs:</b><BR>
396 * XMC_I2S_CH_GetReceivedData()
397 */
XMC_I2S_CH_Receive(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_CHANNEL_t channel_number)398 __STATIC_INLINE void XMC_I2S_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t channel_number)
399 {
400 /* Transmit dummy data */
401 XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU , channel_number);
402 }
403
404 /**
405 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
406 *
407 * @return uint16_t Data read from the receive buffer.
408 *
409 * \par<b>Description:</b><br>
410 * Reads data from the receive buffer based on the FIFO selection.\n\n
411 * Invocation of XMC_I2S_CH_Receive() receives the data and place it into receive buffer. After receiving the data
412 * XMC_I2S_CH_GetReceivedData() can be used to read the data from the buffer.
413 *
414 * \par<b>Related APIs:</b><BR>
415 * XMC_I2S_CH_Receive()
416 */
417 uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
418
419 /**
420 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
421 *
422 * @return None
423 *
424 * \par<b>Description:</b><br>
425 * Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n
426 * This is typically based on the slave settings. Invoke XMC_I2S_CH_SetBitOrderLsbFirst() to set direction as needed in
427 * the program.
428 *
429 * \par<b>Related APIs:</b><BR>
430 * XMC_I2S_CH_SetBitOrderMsbFirst()
431 */
XMC_I2S_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t * const channel)432 __STATIC_INLINE void XMC_I2S_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel)
433 {
434 channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk;
435 }
436
437 /**
438 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
439 *
440 * @return None
441 *
442 * \par<b>Description:</b><br>
443 * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n
444 * This is typically based on the slave settings. This is not set during XMC_I2S_CH_Init().
445 * Invoke XMC_I2S_CH_SetBitOrderMsbFirst() to set direction as needed in the program.
446 *
447 * \par<b>Related APIs:</b><BR>
448 * XMC_I2S_CH_SetBitOrderLsbFirst()
449 */
XMC_I2S_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t * const channel)450 __STATIC_INLINE void XMC_I2S_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel)
451 {
452 channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk;
453 }
454
455 /**
456 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
457 * @param event Protocol events which have to be enabled.
458 * Refer @ XMC_I2S_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum items can be used
459 * as input.
460 *
461 * @return None
462 *
463 * \par<b>Description:</b><br>
464 * Enables the I2S protocol specific events, by configuring PCR register.\n\n
465 * Events can be enabled as needed using XMC_I2S_CH_EnableEvent().
466 * XMC_I2S_CH_DisableEvent() can be used to disable the events.
467 *
468 * \par<b>Related APIs:</b><BR>
469 * XMC_I2S_CH_DisableEvent()
470 */
471 void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
472
473 /**
474 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
475 * @param event Protocol events which have to be disabled.
476 * Refer @ XMC_I2S_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum item can be used
477 * as input.
478 *
479 * @return None
480 *
481 * \par<b>Description:</b><br>
482 * Disables the I2S protocol specific events, by configuring PCR register.\n\n
483 * After disabling the events, XMC_I2S_CH_EnableEvent() has to be invoked to re-enable the events.
484 *
485 * \par<b>Related APIs:</b><BR>
486 * XMC_I2S_CH_EnableEvent()
487 */
488 void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
489
490 /**
491 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
492 *
493 * @return uint32_t Status of I2S protocol events.
494 *
495 * \par<b>Description:</b><br>
496 * Returns the status of the events, by reading PSR register.\n\n
497 * This indicates the status of the all the events, for I2S communication.
498 *
499 * \par<b>Related APIs:</b><BR>
500 * XMC_I2S_CH_ClearStatusFlag()
501 */
XMC_I2S_CH_GetStatusFlag(XMC_USIC_CH_t * const channel)502 __STATIC_INLINE uint32_t XMC_I2S_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
503 {
504 return channel->PSR_IISMode;
505 }
506
507 /**
508 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
509 * @param flag Protocol event status to be cleared for detection of next occurence.
510 * Refer @ XMC_I2S_CH_STATUS_FLAG_t for valid values. <b>OR</b> combinations of these enum item can be used
511 * as input.
512 * @return None
513 *
514 * \par<b>Description:</b><br>
515 * Clears the events specified, by setting PSCR register.\n\n
516 * During communication the events occurred have to be cleared to detect their next occurence.\n
517 * e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This
518 * event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized.
519 *
520 * \par<b>Related APIs:</b><BR>
521 * XMC_I2S_CH_GetStatusFlag()
522 */
XMC_I2S_CH_ClearStatusFlag(XMC_USIC_CH_t * const channel,const uint32_t flag)523 __STATIC_INLINE void XMC_I2S_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag)
524 {
525 channel->PSCR |= flag;
526 }
527
528 /**
529 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
530 *
531 * @return None
532 *
533 * \par<b>Description:</b><br>
534 * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n
535 * This clock can be used as a clock reference for external devices. This is not enabled during initialization in
536 * XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by
537 * XMC_I2S_CH_DisableMasterClock().
538 *
539 * \par<b>Related APIs:</b><BR>
540 * XMC_I2S_CH_DisableMasterClock()
541 */
XMC_I2S_CH_EnableMasterClock(XMC_USIC_CH_t * const channel)542 __STATIC_INLINE void XMC_I2S_CH_EnableMasterClock(XMC_USIC_CH_t *const channel)
543 {
544 channel->PCR_IISMode |= (uint32_t)USIC_CH_PCR_IISMode_MCLK_Msk;
545 }
546
547 /**
548 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
549 *
550 * @return None
551 *
552 * \par<b>Description:</b><br>
553 * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n
554 * This clock can be enabled by invoking XMC_I2S_CH_EnableMasterClock() as needed in the program.
555 *
556 * \par<b>Related APIs:</b><BR>
557 * XMC_I2S_CH_EnableMasterClock()
558 */
XMC_I2S_CH_DisableMasterClock(XMC_USIC_CH_t * const channel)559 __STATIC_INLINE void XMC_I2S_CH_DisableMasterClock(XMC_USIC_CH_t *const channel)
560 {
561 channel->PCR_IISMode &= (uint32_t)~USIC_CH_PCR_IISMode_MCLK_Msk;
562 }
563
564 /**
565 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
566 * @param clock_output shift clock source.\n
567 * Refer @ref XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs.
568 *
569 * @return None
570 *
571 * \par<b>Description:</b><br>
572 * Configures the shift clock source by setting BRG.SCLKOSEL.\n\n
573 * In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available
574 * for external slave devices by SCLKOUT signal.\n
575 * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n
576 */
XMC_I2S_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)577 __STATIC_INLINE void XMC_I2S_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel,
578 const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)
579 {
580 XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)0U,
581 (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output);
582 }
583
584 /**
585 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
586 * @param word_length Number of bits to be configured for a data word. \n
587 * \b Range: 1 to 16.
588 *
589 * @return None
590 *
591 * \par<b>Description</b><br>
592 * Defines the data word length.\n\n
593 * Sets the number of bits to represent a data word. Frame length should be a multiple of word length.
594 *
595 * \par<b>Related APIs:</b><BR>
596 * XMC_I2S_CH_SetFrameLength()
597 */
XMC_I2S_CH_SetWordLength(XMC_USIC_CH_t * const channel,const uint8_t word_length)598 __STATIC_INLINE void XMC_I2S_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
599 {
600 XMC_USIC_CH_SetWordLength(channel, word_length);
601 }
602
603 /**
604 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
605 * @param frame_length Number of bits in a frame. \n
606 * \b Range: 1 to 64.
607 *
608 * @return None
609 *
610 * \par<b>Description</b><br>
611 * Define the data frame length.\n\n
612 * Set the number of bits to be serially transmitted in a frame.
613 * The frame length should be multiples of word length.
614 *
615 * \par<b>Related APIs:</b><BR>
616 * XMC_USIC_CH_SetWordLength()
617 */
XMC_I2S_CH_SetFrameLength(XMC_USIC_CH_t * const channel,const uint8_t frame_length)618 __STATIC_INLINE void XMC_I2S_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
619 {
620 XMC_USIC_CH_SetFrameLength(channel, frame_length);
621 }
622
623 /**
624 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
625 * @param input I2S channel input stage.\n
626 * Refer @ref XMC_I2S_CH_INPUT_t for valid values
627 * @param source Input source select for the input stage.
628 * Range : [0 to 7]
629 *
630 * @return None
631 *
632 * \par<b>Description</b><br>
633 * Selects the data source for I2S input stage, by configuring DXCR.DSEL bits.\n\n
634 * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the
635 * input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting
636 * the I2S communication.
637 */
XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_INPUT_t input,const uint8_t source)638 __STATIC_INLINE void XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t *const channel,
639 const XMC_I2S_CH_INPUT_t input,
640 const uint8_t source)
641 {
642 channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk;
643 XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
644 }
645
646 /**
647 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
648 * @param wa_inversion Polarity of the word address signal.\n
649 * Refer @ref XMC_I2S_CH_WA_POLARITY_t for valid values
650 *
651 * @return None
652 *
653 * \par<b>Description</b><br>
654 * Set the polarity of the word address signal, by configuring PCR.SELINV bit.\n\n
655 * Normally WA signal is active low level signal. This is configured
656 * in XMC_I2S_CH_Init() during initialization. Invoke XMC_I2S_CH_WordAddressSignalPolarity() with desired settings as
657 * needed later in the program.
658 */
XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_WA_POLARITY_t wa_inversion)659 __STATIC_INLINE void XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t *const channel,
660 const XMC_I2S_CH_WA_POLARITY_t wa_inversion)
661 {
662 /* Configuration of Protocol Control Register */
663 channel->PCR_IISMode = (uint32_t)((channel->PCR_IISMode & (~USIC_CH_PCR_IISMode_SELINV_Msk)) | (uint32_t)wa_inversion);
664 }
665
666 /**
667 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
668 * @param input I2S channel input stage.\n
669 * Refer @ref XMC_I2S_CH_INPUT_t for valid inputs.
670 *
671 * @return None
672 *
673 * \par<b>Description</b><br>
674 * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n
675 * This is not set in XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableInputInversion() as needed later in the program. To
676 * disable the inversion XMC_I2S_CH_DisableInputInversion() can be invoked.
677 *
678 * \par<b>Related APIs:</b><BR>
679 * XMC_I2S_CH_DisableInputInversion()
680 */
XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_INPUT_t input)681 __STATIC_INLINE void XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t *const channel,
682 const XMC_I2S_CH_INPUT_t input)
683 {
684 XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
685 }
686
687 /**
688 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
689 * @param input I2S channel input stage.\n
690 * Refer @ref XMC_I2S_CH_INPUT_t for valid inputs.
691 *
692 * @return None
693 *
694 * \par<b>Description</b><br>
695 * Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n
696 * Resets the input data polarity. Invoke XMC_I2S_CH_EnableInputInversion() to apply inversion.
697 *
698 * \par<b>Related APIs:</b><BR>
699 * XMC_I2S_CH_EnableInputInversion()
700 */
XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_INPUT_t input)701 __STATIC_INLINE void XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t *const channel,
702 const XMC_I2S_CH_INPUT_t input)
703 {
704 XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
705 }
706
707 /**
708 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
709 * @param service_request Service request number.
710 Range: [0 to 5]
711 *
712 * @return None
713 *
714 * \par<b>Description</b><br>
715 * Sets the interrupt node for I2S channel events.\n\n
716 * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
717 * The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_I2S_CH_Init() during
718 * initialization.
719 *
720 * \par<b>Note::</b><BR>
721 * 1. NVIC node should be separately enabled to generate the interrupt.
722 *
723 * \par<b>Related APIs:</b><BR>
724 * XMC_USIC_CH_EnableEvent()
725 */
XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t * const channel,const uint8_t service_request)726 __STATIC_INLINE void XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
727 const uint8_t service_request)
728 {
729 XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request);
730 }
731
732
733 /**
734 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
735 * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
736 * @param interrupt_node Interrupt node pointer to be configured. \n
737 * \b Range: @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
738 * @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
739 * @param service_request Service request number.\n
740 * \b Range: 0 to 5.
741 * @return None
742 *
743 * \par<b>Description</b><br>
744 * Sets the interrupt node for USIC channel events. \n\n
745 * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
746 * The NVIC node gets linked to the interrupt event by doing so.<br>
747 * Note: NVIC node should be separately enabled to generate the interrupt.
748 *
749 * \par<b>Related APIs:</b><BR>
750 * XMC_I2S_CH_EnableEvent() \n\n\n
751 */
XMC_I2S_CH_SelectInterruptNodePointer(XMC_USIC_CH_t * const channel,const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node,const uint32_t service_request)752 __STATIC_INLINE void XMC_I2S_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
753 const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
754 const uint32_t service_request)
755 {
756 XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
757 (uint32_t)service_request);
758 }
759
760 /**
761 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
762 * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
763 * @param service_request_line service request number of the event to be triggered. \n
764 * \b Range: 0 to 5.
765 * @return None
766 *
767 * \par<b>Description</b><br>
768 * Trigger a I2S interrupt service request.\n\n
769 * When the I2S service request is triggered, the NVIC interrupt associated with it will be
770 * generated if enabled.
771 *
772 * \par<b>Related APIs:</b><BR>
773 * XMC_I2S_CH_SelectInterruptNodePointer() \n\n\n
774 */
XMC_I2S_CH_TriggerServiceRequest(XMC_USIC_CH_t * const channel,const uint32_t service_request_line)775 __STATIC_INLINE void XMC_I2S_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
776 {
777 XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
778 }
779
780 /**
781 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
782 * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
783 * @return None
784 *
785 * \par<b>Description</b><br>
786 * Enables delay compensation. \n\n
787 *
788 * Delay compensation can be applied to the receive path.
789 * \par<b>Related APIs:</b><BR>
790 * XMC_I2S_CH_DisableDelayCompensation()\n\n\n
791 */
XMC_I2S_CH_EnableDelayCompensation(XMC_USIC_CH_t * const channel)792 __STATIC_INLINE void XMC_I2S_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel)
793 {
794 XMC_USIC_CH_EnableDelayCompensation(channel);
795 }
796
797 /**
798 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
799 * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
800 * @return None
801 *
802 * \par<b>Description</b><br>
803 * Disables delay compensation.. \n\n
804 *
805 * \par<b>Related APIs:</b><BR>
806 * XMC_I2S_CH_EnableDelayCompensation()\n\n\n
807 */
XMC_I2S_CH_DisableDelayCompensation(XMC_USIC_CH_t * const channel)808 __STATIC_INLINE void XMC_I2S_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel)
809 {
810 XMC_USIC_CH_DisableDelayCompensation(channel);
811 }
812
813 /**
814 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
815 * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
816 * @return None
817 *
818 * \par<b>Description</b><br>
819 * Enable data transmission.\n\n
820 * Use this function in combination with XMC_I2S_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
821 * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
822 * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
823 *
824 * \par<b>Related APIs:</b><BR>
825 * XMC_I2S_CH_DisableDataTransmission()\n\n\n
826 */
XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t * const channel)827 __STATIC_INLINE void XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
828 {
829 XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
830 }
831
832 /**
833 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
834 * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
835 * @return None
836 *
837 * \par<b>Description</b><br>
838 * Disable data transmission.\n\n
839 * Use this function in combination with XMC_I2S_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
840 * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
841 *
842 * \par<b>Related APIs:</b><BR>
843 * XMC_I2S_CH_EnableDataTransmission()\n\n\n
844 */
XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t * const channel)845 __STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
846 {
847 XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
848 }
849
850 #ifdef __cplusplus
851 }
852 #endif
853
854 /**
855 * @}
856 */
857
858 /**
859 * @}
860 */
861 #endif /* XMC_I2S_H_ */
862
