1 /**
2 * @file xmc_bccu.h
3 * @date 2015-06-20
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-19:
40 * - Initial draft<br>
41 * - Documentation improved <br>
42 *
43 * 2015-05-08:
44 * - Minor bug fix in XMC_BCCU_ClearEventFlag().
45 * - New APIs are added: XMC_BCCU_DIM_ReadDimDivider(), XMC_BCCU_DIM_GetDimCurve(), XMC_BCCU_IsDitherEnable()<br>
46 *
47 * 2015-06-20:
48 * - Removed version macros and declaration of GetDriverVersion API
49 *
50 * <b>Detailed description of file:</b><br>
51 * APIs for the functional blocks of BCCU have been defined:<br>
52 * -- GLOBAL configuration <br>
53 * -- Clock configuration, Function/Event configuration, Interrupt configuration <br>
54 *
55 * @endcond
56 *
57 */
58
59 #ifndef XMC_BCCU_H
60 #define XMC_BCCU_H
61
62 /*********************************************************************************************************************
63 * HEADER FILES
64 ********************************************************************************************************************/
65 #include <xmc_common.h>
66
67 /**
68 * @addtogroup XMClib XMC Peripheral Library
69 * @{
70 */
71
72 /**
73 * @addtogroup BCCU
74 * @brief Brightness and Color Control Unit (BCCU) driver for the XMC1 microcontroller family.
75 *
76 * The Brightness and Color Control Unit (BCCU) is a dimming control peripheral for LED lighting applications. The BCCU
77 * module can be used to control multiple LED channels. Every channel generates one-bit sigma-delta bit stream with a
78 * user adjustable 12-bit average value. The dimming engine changes the brightness gradually (exponential curve) to appear
79 * natural to the human eye. It supports color control by adjusting the relative intensity of selected channels using a
80 * linear walk scheme for smooth color changes. It also supports high-power multi-channel LED lamps by optionally packing
81 * the bitstream. The optional packer which decreases the average rate of output switching by enforcing a defined on-time.
82 * The BCCU module generates two trigger signals to the ADC (BCCU_TRIGOUT0 and BCCU_TRIGOU1) to start conversions in a
83 * synchronized manner. The module can also be used as a multi-channel digital-analog converter with low-pass filters on the
84 * outputs. The BCCU module supports 3 independent dimming engines, 9 independent channels, Trap functions and 2 ADC
85 * triggering modes.
86 *
87 * The driver is divided into global control (BCCU), channel control (BCCU_CH) and dimming control (BCCU_DIM).
88 *
89 * BCCU features:
90 * -# Configuration structure XMC_BCCU_GLOBAL_CONFIG_t and initialization function XMC_BCCU_GlobalInit()
91 * -# Allows configuring of clock settings (Fast clock, Bit clock and Dimming clock). XMC_BCCU_SetFastClockPrescaler(),
92 * -# XMC_BCCU_SelectBitClock(), XMC_BCCU_SetDimClockPrescaler().
93 * -# Allows configuring global trigger settings. XMC_BCCU_ConfigGlobalTrigger()
94 * -# Allows enabling multiple channels together. XMC_BCCU_ConcurrentEnableChannels()
95 * -# Allows enabling single channel. XMC_BCCU_EnableChannel()
96 * -# Allows configuring global dimming level. XMC_BCCU_SetGlobalDimmingLevel()
97 * -# Starts linear walk for multiple channels together. XMC_BCCU_ConcurrentStartLinearWalk().
98 * -# Starts linear walk for single channel. XMC_BCCU_StartLinearWalk().
99 * -# Starts dimming for multiple dimming engines together. XMC_BCCU_ConcurrentStartDimming().
100 * -# Starts dimming for single dimming engine. XMC_BCCU_StartDimming().
101 *
102 * BCCU_CH features:
103 * -# Configuration structure (XMC_BCCU_CH_t and initialization function XMC_BCCU_CH_Init()
104 * -# Allows selecting dimming engine. XMC_BCCU_CH_SelectDimEngine().
105 * -# Allows setting target channel intensity. XMC_BCCU_CH_SetTargetIntensity().
106 * -# Allows knowing the status of linear walk completion. XMC_BCCU_IsLinearWalkComplete()
107 * -# Allows setting flicker watchdog. XMC_BCCU_CH_EnableFlickerWatchdog().
108 * -# Allows configuring packer settings. XMC_BCCU_CH_EnablePacker(), XMC_BCCU_CH_SetPackerThreshold(),
109 * XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOffCounte(), XMC_BCCU_CH_SetPackerOnCounter()
110 * -# Allows selecting dimming bypass. XMC_BCCU_CH_DisableDimmingBypass()
111 *
112 * BCCU_DIM features:
113 * -# Configuration structure (XMC_BCCU_DIM_t and initialization function XMC_BCCU_DIM_Init()
114 * -# Allows setting target dimming engine intensity. XMC_BCCU_DIM_SetTargetDimmingLevel().
115 * XMC_BCCU_DIM_SetTargetDimmingLevel
116 * -# Allows knowing the status of dimming completion. XMC_BCCU_IsDimmingFinished()
117 * -# Allows configuring dimming divider. XMC_BCCU_DIM_SetDimDivider()
118 * -# Allows configuring dimming curve. XMC_BCCU_DIM_ConfigDimCurve()
119 *
120 * <b> Recommended programming sequence: </b>
121 * -# Set output passive and active levels using XMC_BCCU_ConcurrentSetOutputPassiveLevel() or XMC_BCCU_SetOutputPassiveLevel()
122 * -# Initializes global features using XMC_BCCU_GlobalInit()
123 * -# Initializes channel features using XMC_BCCU_CH_Init()
124 * -# Initializes dimming engine using XMC_BCCU_DIM_Init()
125 * -# Enable channels using XMC_BCCU_ConcurrentEnableChannels() or XMC_BCCU_EnableChannel()
126 * -# Enable dimming engines using XMC_BCCU_ConcurrentEnableDimmingEngine() or XMC_BCCU_EnableDimmingEngine()
127 * -# Configure channel linear walk prescaler using XMC_BCCU_CH_SetLinearWalkPrescaler()
128 * -# Configure dimming divider using XMC_BCCU_DIM_SetDimDivider()
129 * -# Set target intensities of channels using XMC_BCCU_CH_SetTargetIntensity()
130 * -# Set target dim levels of dimming engines using XMC_BCCU_DIM_SetTargetDimmingLevel()
131 * -# Start linear walk of the channels using XMC_BCCU_ConcurrentStartLinearWalk() or XMC_BCCU_StartLinearWalk()
132 * -# Start dimming of the dimming engines using XMC_BCCU_ConcurrentStartDimming() or XMC_BCCU_StartDimming()
133 * -# Check the status of linear walk completion using XMC_BCCU_IsLinearWalkComplete()
134 * -# Check the status of dimming completion XMC_BCCU_IsDimmingFinished()
135 * @{
136 */
137
138 #if defined (BCCU0)
139
140 /*********************************************************************************************************************
141 * MACROS
142 ********************************************************************************************************************/
143
144 /*********************************************************************************************************************
145 * ENUMS
146 ********************************************************************************************************************/
147 /**
148 * Defines the status of BCCU driver, to verify the related API calls. Use type \a XMC_BCCU_STATUS_t for this enum.
149 */
150 typedef enum {
151 XMC_BCCU_STATUS_SUCCESS = 0U, /**< Operation completed successfully */
152 XMC_BCCU_STATUS_ERROR = 1U, /**< Operation has some errors */
153 } XMC_BCCU_STATUS_t;
154
155 /**
156 * Provides the options to select bit clock mode.
157 */
158 typedef enum {
159 XMC_BCCU_BCLK_MODE_NORMAL = 0U, /**< Normal Mode: Bit clock runs at 1/4 of fast clock */
160 XMC_BCCU_BCLK_MODE_FAST = 1U, /**< Fast Mode: Bit clock runs at same as fast clock */
161 } XMC_BCCU_BCLK_MODE_t;
162
163 /**
164 * Provides the options to select trigger mode.
165 */
166 typedef enum {
167 XMC_BCCU_TRIGMODE0 = 0U, /**< Mode0: Trigger on Any Channel using OR logic */
168 XMC_BCCU_TRIGMODE1 = 1U, /**< Mode1: Trigger on Active channel using round-robin*/
169 } XMC_BCCU_TRIGMODE_t;
170
171 /**
172 * Provides the options to select trigger delay, and only be used if Bit clock in Normal mode
173 */
174 typedef enum {
175 XMC_BCCU_TRIGDELAY_NO_DELAY = 0U, /**< BCCU trigger occurs on channel trigger(without delay) */
176 XMC_BCCU_TRIGDELAY_QUARTER_BIT = 1U, /**< BCCU trigger occurs on 1/4 bit time delayed after channel trigger */
177 XMC_BCCU_TRIGDELAY_HALF_BIT = 2U, /**< BCCU trigger occurs on 1/2 bit time delayed after channel trigger */
178 } XMC_BCCU_TRIGDELAY_t;
179
180 /**
181 * Provides the options to select suspend mode
182 */
183 typedef enum {
184 XMC_BCCU_SUSPEND_MODE_IGNORE = 0U, /**< Request ignored, and module cannot get suspended */
185 XMC_BCCU_SUSPEND_MODE_FREEZE = 1U, /**< All running channels gets stopped, and freeze into a last state (without safe stop)
186 */
187 XMC_BCCU_SUSPEND_MODE_SAFE_FREEZE = 2U, /**< All running channels gets stopped, and freeze into a last state (with safe
188 stop) */
189 } XMC_BCCU_SUSPEND_MODE_t;
190
191 /**
192 * Provides the options to select trap edge
193 */
194 typedef enum {
195 XMC_BCCU_TRAPEDGE_RISING = 0U, /**< Trap on rising edge of the BCCU.TRAPL signal */
196 XMC_BCCU_TRAPEDGE_FALLING = 1U, /**< Trap on falling edge of the BCCU.TRAPL signal */
197 } XMC_BCCU_TRAPEDGE_t;
198
199 /**
200 * Provides the options to enable/disable the events.
201 * The members can be combined using 'OR' operator for multiple selection.<br>
202 */
203 typedef enum {
204 XMC_BCCU_EVENT_TRIGGER0 = 0x1U, /**< Trigger 0 event */
205 XMC_BCCU_EVENT_TRIGGER1 = 0x2U, /**< Trigger 1 event */
206 XMC_BCCU_EVENT_FIFOFULL = 0x4U, /**< FIFO Full event */
207 XMC_BCCU_EVENT_FIFOEMPTY = 0x8U, /**< FIFO Empty event */
208 XMC_BCCU_EVENT_TRAP = 0x10U, /**< Trap event */
209 } XMC_BCCU_EVENT_t;
210
211 /**
212 * Provides the options to know the status of the event flags.
213 * The members can be combined using 'OR' operator for multiple selection.<br>
214 */
215 typedef enum {
216 XMC_BCCU_EVENT_STATUS_TRIGGER0 = 0x1U, /**< Trigger 0 Event flag status */
217 XMC_BCCU_EVENT_STATUS_TRIGGER1 = 0x2U, /**< Trigger 1 Event flag status */
218 XMC_BCCU_EVENT_STATUS_FIFOFULL = 0x4U, /**< FIFO Full Event flag status */
219 XMC_BCCU_EVENT_STATUS_FIFOEMPTY = 0x8U, /**< FIFO Empty Event flag status */
220 XMC_BCCU_EVENT_STATUS_TRAP = 0x10U, /**< Trap Event flag status (Without Trap Set) */
221 XMC_BCCU_EVENT_STATUS_TRAP_STATE = 0x40U, /**< Trap state flag status */
222 } XMC_BCCU_EVENT_STATUS_t;
223
224 /**
225 * Provides the options to know the status of trap occurrence
226 */
227 typedef enum {
228 XMC_BCCU_TRAP_STATUS_DEACTIVE = 0x0U, /**< BCCU module is not in a Trap State */
229 XMC_BCCU_TRAP_STATUS_ACTIVE = 0x1U, /**< BCCU module is in a Trap State */
230 } XMC_BCCU_TRAP_STATUS_t;
231
232 /**
233 * Provides the options to know the current level of trap
234 */
235 typedef enum {
236 XMC_BCCU_TRAP_LEVEL_LOW = 0x0U, /**< BCCU.TRAPL is Low */
237 XMC_BCCU_TRAP_LEVEL_HIGH = 0x1U, /**< BCCU.TRAPL is High */
238 } XMC_BCCU_TRAP_LEVEL_t;
239
240 /**
241 * Provides the options to select flicker watchdog enable/disable
242 */
243 typedef enum {
244 XMC_BCCU_CH_FLICKER_WD_DS = 0U, /**< Disable: No control over a sigma-delta modulator output */
245 XMC_BCCU_CH_FLICKER_WD_EN = 1U, /**< Enable: Limit consecutive zeros at sigma-delta modulator output */
246 } XMC_BCCU_CH_FLICKER_WD_t;
247
248 /**
249 * Provides the options to select gating functionality enable/disable, and be used for peak-current control
250 */
251 typedef enum {
252 XMC_BCCU_CH_GATING_FUNC_DISABLE = 0U, /**< Disable: No control over a BCCU module output */
253 XMC_BCCU_CH_GATING_FUNC_ENABLE = 1U, /**< Enable: External gating signal which controls BCCU module output */
254 } XMC_BCCU_CH_GATING_FUNC_t;
255
256 /**
257 * Provides the options to bypass dimming engine
258 */
259 typedef enum {
260 XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_DISABLE = 0U, /**< Disable: Brightness = Dimming Level * Intensity */
261 XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_ENABLE = 1U, /**< Enable: Brightness = Intensity */
262 } XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t;
263
264 /**
265 * Provides the options to select passive level of the channel output
266 */
267 typedef enum{
268 XMC_BCCU_CH_ACTIVE_LEVEL_HIGH = 0U, /**< Default passive level of the channel is low */
269 XMC_BCCU_CH_ACTIVE_LEVEL_LOW = 1U, /**< Default passive level of the channel is high */
270 } XMC_BCCU_CH_ACTIVE_LEVEL_t;
271
272 /**
273 * Provides the options to select trigger edge
274 */
275 typedef enum
276 {
277 XMC_BCCU_CH_TRIG_EDGE_PASS_TO_ACT = 0U, /**< Trigger on output transition from passive to active */
278 XMC_BCCU_CH_TRIG_EDGE_ACT_TO_PASS = 1U, /**< Trigger on output transition from active to passive */
279 } XMC_BCCU_CH_TRIG_EDGE_t;
280
281 /**
282 * Provides the options to select source of trap input
283 */
284 typedef enum
285 {
286 XMC_BCCU_CH_TRAP_INA = 0x0U, /**< Trap INA */
287 XMC_BCCU_CH_TRAP_INB = 0x1U, /**< Trap INB */
288 XMC_BCCU_CH_TRAP_INC = 0x2U, /**< Trap INC */
289 XMC_BCCU_CH_TRAP_IND = 0x3U, /**< Trap IND */
290 XMC_BCCU_CH_TRAP_INE = 0x4U, /**< Trap INE */
291 XMC_BCCU_CH_TRAP_INF = 0x5U, /**< Trap INF */
292 XMC_BCCU_CH_TRAP_ING = 0x6U, /**< Trap ING */
293 XMC_BCCU_CH_TRAP_INH = 0x7U, /**< Trap INH */
294 XMC_BCCU_CH_TRAP_INI = 0x8U, /**< Trap INI */
295 XMC_BCCU_CH_TRAP_INJ = 0x9U, /**< Trap INJ */
296 XMC_BCCU_CH_TRAP_INK = 0xAU, /**< Trap INK */
297 XMC_BCCU_CH_TRAP_INL = 0xBU, /**< Trap INL */
298 XMC_BCCU_CH_TRAP_INM = 0xCU, /**< Trap INM */
299 XMC_BCCU_CH_TRAP_INN = 0xDU, /**< Trap INN */
300 XMC_BCCU_CH_TRAP_INO = 0xEU, /**< Trap INO */
301 XMC_BCCU_CH_TRAP_INP = 0xFU, /**< Trap INP */
302 } XMC_BCCU_CH_TRAP_IN_t;
303
304 /**
305 * Provides the options to select edge for trap occurrence
306 */
307 typedef enum
308 {
309 XMC_BCCU_CH_TRAP_EDGE_RISING = 0U, /**< Trap on rising edge of the BCCU.TRAPL signal */
310 XMC_BCCU_CH_TRAP_EDGE_FALLING = 1U /**< Trap on falling edge of the BCCU.TRAPL signal */
311 } XMC_BCCU_CH_TRAP_EDGE_t;
312
313 /**
314 * Provides the options to select trigger output, and only be used in XMC_BCCU_TRIGMODE1
315 */
316 typedef enum {
317 XMC_BCCU_CH_TRIGOUT0 = 0U, /**< Trigger occurrence on BCCU_TRIGOUT0 signal */
318 XMC_BCCU_CH_TRIGOUT1 = 1U, /**< Trigger occurrence on BCCU_TRIGOUT1 signal */
319 } XMC_BCCU_CH_TRIGOUT_t;
320
321 /**
322 * Provides the options to select dimming source of the channel
323 */
324 typedef enum {
325 XMC_BCCU_CH_DIMMING_SOURCE_GLOBAL = 7U, /**< Global Dimming Engine */
326 XMC_BCCU_CH_DIMMING_SOURCE_DE0 = 0U, /**< Dimming Engine 0 */
327 XMC_BCCU_CH_DIMMING_SOURCE_DE1 = 1U, /**< Dimming Engine 1 */
328 XMC_BCCU_CH_DIMMING_SOURCE_DE2 = 2U, /**< Dimming Engine 2 */
329 } XMC_BCCU_CH_DIMMING_SOURCE_t;
330
331 /**
332 * Provides the options to select exponential dimming curve
333 */
334 typedef enum {
335 XMC_BCCU_DIM_CURVE_COARSE = 0U, /**< Coarse curve: Slope of the linear pieces doubles every time, when it passes specific
336 thresholds of 16, 32, 64, 128, 256, 512, 1024, 2048 */
337 XMC_BCCU_DIM_CURVE_FINE = 1U, /**< Fine Curve: More pieces and different line slopes */
338 } XMC_BCCU_DIM_CURVE_t;
339
340 /*********************************************************************************************************************
341 * DATA STRUCTURES
342 ********************************************************************************************************************/
343 /**
344 * Redefinition of BCCU module structure; pointer to bccu module base address
345 */
346 typedef BCCU_Type XMC_BCCU_t;
347
348 /**
349 * Redefinition of BCCU module channel structure; pointer to bccu module channel Base address
350 */
351 typedef BCCU_CH_Type XMC_BCCU_CH_t;
352
353 /**
354 * Redefinition of BCCU module dimming engine structure; pointer to bccu module dimming engine base address
355 */
356 typedef BCCU_DE_Type XMC_BCCU_DIM_t;
357
358 /*Anonymous structure/union guard start*/
359 #if defined(__CC_ARM)
360 #pragma push
361 #pragma anon_unions
362 #elif defined(__TASKING__)
363 #pragma warning 586
364 #endif
365
366 /**
367 * Configures a global setting of the BCCU module.
368 */
369 typedef struct XMC_BCCU_GLOBAL_CONFIG
370 {
371 union{
372 struct{
373 uint32_t trig_mode:1; /**< Selects trigger Mode. Use type @ref XMC_BCCU_TRIGMODE_t */
374 uint32_t : 1;
375 uint32_t trig_delay:2; /**< Selects trigger delay between channel & module trigger. \n Use type @ref
376 XMC_BCCU_TRIGDELAY_t */
377 uint32_t : 12;
378 uint32_t maxzero_at_output:12; /**< Configures maximum 0's allowed at modulator output */
379 };
380 uint32_t globcon; /* Not to use */
381 };
382 union{
383 struct{
384 uint32_t fclk_ps:12; /**< Configures the ratio between fast clock and module clock */
385 uint32_t : 3;
386 uint32_t bclk_sel:1; /**< Selects the bit clock. Use type @ref XMC_BCCU_BCLK_MODE_t */
387 uint32_t dclk_ps:12; /**< Configures the ratio between dimmer clock and module clock */
388 };
389 uint32_t globclk; /* Not to use */
390 };
391 uint32_t global_dimlevel; /**< Configures global dimming engine dimming level */
392 } XMC_BCCU_GLOBAL_CONFIG_t;
393
394
395 /**
396 * Configures global trigger settings of the BCCU module.
397 */
398 typedef struct XMC_BCCU_TRIG_CONFIG
399 {
400 XMC_BCCU_TRIGMODE_t mode; /**< Selects global trigger mode which decides when to occur BCCU trigger */
401 XMC_BCCU_TRIGDELAY_t delay; /**< Selects global trigger delay between channel trigger & BCCU trigger */
402 uint16_t mask_chans; /**< Channel mask to configure trigger settings for multiple channels <b>For example:</b>
403 If channel 0 and 7, wants to configure then the channel mask is 01000 0001 = 0x81\n*/
404 uint16_t mask_trig_lines; /**< Trigger line mask */
405 } XMC_BCCU_TRIG_CONFIG_t;
406
407 /**
408 * Configures channel settings of the BCCU module.
409 */
410 #ifdef DOXYGEN
411 typedef struct XMC_BCCU_CH_CONFIG
412 {
413 uint32_t pack_thresh:3; /**< Configures packer threshold value of FIFO */
414 uint32_t pack_en:1; /**< Enables a packed output bitstream */
415 uint32_t dim_sel:3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t */
416 uint32_t dim_bypass:1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */
417 uint32_t gate_en:1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */
418 uint32_t flick_wd_en:1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */
419 uint32_t trig_edge:1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */
420 uint32_t force_trig_en:1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n for
421 256 bclk cycles */
422 uint32_t pack_offcmp_lev:8; /**< Configures a packer off-time compare level. When the off-time counter reaches this, the
423 measured on & off time counters are stored into FIFO */
424 uint32_t pack_oncmp_lev:8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\n
425 the measured on & off time counters are stored into FIFO */
426 uint32_t pack_offcnt_val:8; /**< Configures an initial packer off-time counter level, only if channel is disabled. <br>
427 Controls phase shift of the modulator output */
428 uint32_t pack_oncnt_val:8; /**< Configures an initial packer on-time counter level, only if channel is disabled. <br>
429 Controls phase shift of the modulator output */
430 }XMC_BCCU_CH_CONFIG_t;
431 #endif
432
433 typedef struct XMC_BCCU_CH_CONFIG
434 {
435 union{
436 struct{
437 uint32_t pack_thresh:3; /**< Configures packer threshold value of FIFO */
438 uint32_t pack_en:1; /**< Enables a packed output bitstream */
439 uint32_t dim_sel:3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t
440 */
441 uint32_t dim_bypass:1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */
442 uint32_t gate_en:1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */
443 uint32_t flick_wd_en:1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */
444 uint32_t trig_edge:1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */
445 uint32_t force_trig_en:1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n
446 for 256 bclk cycles */
447 };
448 uint32_t chconfig; /* Not to use */
449 };
450 union{
451 struct{
452 uint32_t pack_offcmp_lev:8; /**< Configures a packer off-time compare level. When the off-time counter reaches \n
453 this, the measured on & off time counters are stored into FIFO */
454 uint32_t : 8;
455 uint32_t pack_oncmp_lev:8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\n
456 the measured on & off time counters are stored into FIFO */
457 };
458 uint32_t pkcmp; /* Not to use */
459 };
460 union{
461 struct{
462 uint32_t pack_offcnt_val:8; /**< Configures an initial packer off-time counter level, only if channel is disabled. <br>
463 Controls phase shift of the modulator output */
464 uint32_t : 8;
465 uint32_t pack_oncnt_val:8; /**< Configures an initial packer on-time counter level, only if channel is disabled. <br>
466 Controls phase shift of the modulator output */
467 };
468 uint32_t pkcntr; /* Not to use */
469 };
470 }XMC_BCCU_CH_CONFIG_t;
471
472 /**
473 * Configures dimming engine settings of the BCCU module.
474 */
475 #ifdef DOXYGEN
476 typedef struct XMC_BCCU_DIM_CONFIG
477 {
478 uint32_t dim_div:10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level <br>
479 as same as target dimming level on shadow transfer */
480 uint32_t dither_en:1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */
481 uint32_t cur_sel:1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither <br>
482 enabled, the configuration is being ignored */
483 }XMC_BCCU_DIM_CONFIG_t;
484 #endif
485
486 typedef struct XMC_BCCU_DIM_CONFIG
487 {
488 union{
489 struct{
490 uint32_t dim_div:10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level <br>
491 as same as target dimming level on shadow transfer */
492 uint32_t : 6;
493 uint32_t dither_en:1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */
494 uint32_t cur_sel:1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither <br>
495 enabled, the configuration is being ignored */
496 };
497 uint32_t dtt; /* Not to use */
498 };
499 }XMC_BCCU_DIM_CONFIG_t;
500
501 /*Anonymous structure/union guard end*/
502 #if defined(__CC_ARM)
503 #pragma pop
504 #elif defined(__TASKING__)
505 #pragma warning restore
506 #endif
507 /*********************************************************************************************************************
508 * API PROTOTYPES
509 ********************************************************************************************************************/
510 #ifdef __cplusplus
511 extern "C" {
512 #endif
513
514 /**
515 *
516 * @param bccu Base address of the bccu module. \b Range: BCCU0
517 * @param config Pointer to constant bccu global configuration data structure. Use type @ref XMC_BCCU_GLOBAL_CONFIG_t.
518 *
519 * @return None
520 *
521 * \par<b>Description:</b><br>
522 * Initializes three main clocks (fast clock, bit clock, dimmer clock) by using \a fclk_ps \a bclk_sel \a dclk_ps parameters
523 * and writing into a GLOBCLK register.\n
524 * And also configures a trigger mode, trigger delay, maximum 0's allowed at modulator output by writing into a GLOBCON
525 * register.\n\n
526 *
527 * \par<b>Related APIs:</b><BR>
528 * XMC_BCCU_CH_Init(), XMC_BCCU_DIM_Init()\n\n\n
529 */
530 void XMC_BCCU_GlobalInit (XMC_BCCU_t *const bccu, const XMC_BCCU_GLOBAL_CONFIG_t *const config);
531
532 /**
533 *
534 * @param bccu Base address of the bccu module. \b Range: BCCU0
535 * @param mode Trigger mode selection. \b Range: XMC_BCCU_TRIGMODE0, XMC_BCCU_TRIGMODE1.\n
536 * 1. XMC_BCCU_TRIGMODE0 - Trigger on Any Channel
537 * 2. XMC_BCCU_TRIGMODE1 - Trigger on Active channel
538 * @param delay Delay to avoid sampling during switching noise. Use type @ref XMC_BCCU_TRIGDELAY_t. \n
539 * \b Range: XMC_BCCU_NO_DELAY, XMC_BCCU_QUARTER_BIT_DELAY, XMC_BCCU_HALF_BIT_DELAY.
540 *
541 * @return None
542 *
543 * \par<b>Description:</b><br>
544 * Configures trigger mode and trigger delay by writing register bits GLOBCON.TM, GLOBCON.TRDEL. \a mode and \a delay
545 * parameters which decides when to trigger a conversion of vadc module for voltage measurement. \n\n
546 *
547 * \par<b>Related APIs:</b><BR>
548 * XMC_BCCU_EnableChannelTrigger(), XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(), XMC_BCCU_GlobalInit(),
549 * XMC_BCCU_ReadLastTrigChanNr(), XMC_BCCU_GetChannelOutputLvlAtLastTrigger(), XMC_BCCU_CH_ConfigTrigger()\n\n\n
550 */
551 void XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay);
552
553 /**
554 *
555 * @param bccu Base address of the bccu module. \b Range: BCCU0
556 *
557 * @return Source of Trigger mode. \b Range: 0 or 1 \n
558 * 0 - Trigger mode 0 (Trigger on Any Channel) \n
559 * 1 - Trigger mode 1 (Trigger on Active Channel)\n\n
560 * \par<b>Description:</b><br>
561 * Retrieves global trigger mode of the BCCU module by reading the register bit GLOBCON_TM. Use XMC_BCCU_TRIGMODE_t type to
562 * validate a returned value.\n\n
563 *
564 * \par<b>Related APIs:</b><BR>
565 * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(), XMC_BCCU_GlobalInit()\n\n\n
566 */
XMC_BCCU_ReadGlobalTrigger(XMC_BCCU_t * const bccu)567 __STATIC_INLINE uint32_t XMC_BCCU_ReadGlobalTrigger (XMC_BCCU_t *const bccu)
568 {
569 return (uint32_t)(bccu->GLOBCON & BCCU_GLOBCON_TM_Msk);
570 }
571
572 /**
573 *
574 * @param bccu Base address of the bccu module. \b Range: BCCU0
575 * @param input Trap input selection. Use type @ref XMC_BCCU_TRIGDELAY_t.
576 * \b Range: XMC_BCCU_TRIGDELAY_NO_DELAY, XMC_BCCU_TRIGDELAY_QUARTER_BIT, XMC_BCCU_TRIGDELAY_HALF_BIT.
577 *
578 * @return None
579 *
580 * \par<b>Description:</b><br>
581 * Selects input of trap functionality by writing register bit GLOBCON_TRAPIS. The trap functionality is used to switch
582 * off the connected power devices when trap input becomes active.\n\n
583 *
584 * \par<b>Related APIs:</b><BR>
585 * XMC_BCCU_SetTrapEdge(), XMC_BCCU_ReadTrapInput(), XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentEnableTrap()\n\n\n
586 */
587 void XMC_BCCU_SelectTrapInput (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_IN_t input);
588
589 /**
590 *
591 * @param bccu Base address of the bccu module. \b Range: BCCU0
592 *
593 * @return Source of trap input. \b Range: 0 to 15 \n
594 * 0 - TRAPINA \n
595 * 1 - TRAPINB and so on. \n
596 * \par<b>Description:</b><br>
597 * Retrieves trap input of the channel by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_CH_TRAP_IN_t type to
598 * validate a returned value.\n\n
599 *
600 * \par<b>Related APIs:</b><BR>
601 * XMC_BCCU_SelectTrapInput()\n\n\n
602 */
XMC_BCCU_ReadTrapInput(XMC_BCCU_t * const bccu)603 __STATIC_INLINE uint32_t XMC_BCCU_ReadTrapInput (XMC_BCCU_t *const bccu)
604 {
605 return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPIS_Msk) >> BCCU_GLOBCON_TRAPIS_Pos);
606 }
607
608 /**
609 *
610 * @param bccu Base address of the bccu module. \b Range: BCCU0
611 * @param edge Trap edge selection. Use type @ref XMC_BCCU_CH_TRAP_EDGE_t. \n
612 * \b Range: XMC_BCCU_CH_TRAP_EDGE_RISING, XMC_BCCU_CH_TRAP_EDGE_FALLING.
613 *
614 * @return None
615 *
616 * \par<b>Description:</b><br>
617 * Selects active edge which detects trap on TRAPL signal by writing register bit GLOBCON_TRAPED.\n\n
618 *
619 * \par<b>Related APIs:</b><BR>
620 * XMC_BCCU_SelectTrapInput(), XMC_BCCU_ReadTrapEdge(), XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentEnableTrap()\n\n\n
621 */
622 void XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge);
623
624 /**
625 *
626 * @param bccu Base address of the bccu module. \b Range: BCCU0
627 *
628 * @return Trap edge selection. \b Range: 0 or 1 \n
629 * 0 - XMC_BCCU_CH_TRAP_EDGE_RISING \n
630 * 1 - XMC_BCCU_CH_TRAP_EDGE_FALLING. \n
631 * \par<b>Description:</b><br>
632 * Retrieves trap edge by reading the register bit GLOBCON_TRAPED. Use XMC_BCCU_CH_TRAP_EDGE_t type to
633 * validate a returned value.\n\n
634 *
635 * \par<b>Related APIs:</b><BR>
636 * XMC_BCCU_SetTrapEdge()\n\n\n
637 */
XMC_BCCU_ReadTrapEdge(XMC_BCCU_t * const bccu)638 __STATIC_INLINE uint32_t XMC_BCCU_ReadTrapEdge (XMC_BCCU_t *const bccu)
639 {
640 return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPED_Msk) >> BCCU_GLOBCON_TRAPED_Pos);
641 }
642
643 /**
644 *
645 * @param bccu Base address of the bccu module. \b Range: BCCU0
646 * @param mode Suspend mode selection. Use type @ref XMC_BCCU_SUSPEND_MODE_t. \n
647 * \b Range: XMC_BCCU_SUSPEND_MODE_IGNORE, XMC_BCCU_SUSPEND_MODE_FREEZE, XMC_BCCU_USPEND_MODE_SAFE_FREEZE. \n
648 *
649 * @return None
650 *
651 * \par<b>Description:</b><br>
652 * Configures suspend mode by writing register bit GLOBCON_SUSCFG.\n\n
653 *
654 * \par<b>Related APIs:</b><BR>
655 * XMC_BCCU_ReadSuspendMode()\n\n\n
656 */
657 void XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t mode);
658
659 /**
660 *
661 * @param bccu Base address of the bccu module. \b Range: BCCU0
662 *
663 * @return Trap edge selection. \b Range: 0, 1, 2 \n
664 * 0 - XMC_BCCU_SUSPEND_MODE_IGNORE \n
665 * 1 - XMC_BCCU_SUSPEND_MODE_FREEZE. \n
666 * 2 - XMC_BCCU_USPEND_MODE_SAFE_FREEZE. \n
667 * \par<b>Description:</b><br>
668 * Retrieves the state of suspend mode by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_SUSPEND_MODE_t type to
669 * validate a returned value.\n\n
670 *
671 * \par<b>Related APIs:</b><BR>
672 * XMC_BCCU_ConfigSuspendMode()\n\n\n
673 */
XMC_BCCU_ReadSuspendMode(XMC_BCCU_t * const bccu)674 __STATIC_INLINE uint32_t XMC_BCCU_ReadSuspendMode (XMC_BCCU_t *const bccu)
675 {
676 return (uint32_t)( ((bccu->GLOBCON) & BCCU_GLOBCON_SUSCFG_Msk) >> BCCU_GLOBCON_SUSCFG_Pos);
677 }
678
679 /**
680 *
681 * @param bccu Base address of the bccu module. \b Range: BCCU0
682 *
683 * @return Last triggered channel number. \b Range: 0 to 8\n
684 * 0 - BCCU Channel 0\n
685 * 1 - BCCU Channel 1 and so on.\n
686 * \par<b>Description:</b><br>
687 * Retrieves last triggered channel number of a BCCU module by reading the register bit GLOBCON_LTRS.\n\n
688 *
689 * \par<b>Related APIs:</b><BR>
690 * XMC_BCCU_GetChannelOutputLvlAtLastTrigger(), XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(),
691 * XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_GlobalInit()\n\n\n
692 */
XMC_BCCU_ReadLastTrigChanNr(XMC_BCCU_t * const bccu)693 __STATIC_INLINE uint32_t XMC_BCCU_ReadLastTrigChanNr (XMC_BCCU_t *const bccu)
694 {
695 return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_LTRS_Msk) >> BCCU_GLOBCON_LTRS_Pos);
696 }
697
698 /**
699 *
700 * @param bccu Base address of the bccu module. \b Range: BCCU0
701 * @param threshold_no Number of consecutive zeroes at modulator output. \b Range: 0 to 4095.
702 *
703 * @return None
704 *
705 * \par<b>Description:</b><br>
706 * Configures number of consecutive zeroes allowed at modulator output (flicker watch-dog number) by writing register
707 * bit GLOBCON_WDMBN.\n\n
708 *
709 * \par<b>Related APIs:</b><BR>
710 * XMC_BCCU_CH_EnableFlickerWatchdog(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), XMC_BCCU_CH_DisableFlickerWatchdog()\n\n\n
711 */
712 void XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_no);
713
714 /**
715 *
716 * @param bccu Base address of the bccu module. \b Range: BCCU0
717 *
718 * @return Number of consecutive zeroes at modulator output. \b Range: 0 to 4095 \n
719 * \par<b>Description:</b><br>
720 * Retrieves number of consecutive zeroes at modulator output (flicker watchdog number) by reading the register bit
721 * GLOBCON_WDMBN.\n\n
722 *
723 * \par<b>Related APIs:</b><BR>
724 * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_CH_EnableFlickerWatchdog(), XMC_BCCU_CH_Init(), XMC_BCCU_CH_DisableFlickerWatchdog()\n\n\n
725 */
XMC_BCCU_ReadFlickerWDThreshold(XMC_BCCU_t * const bccu)726 __STATIC_INLINE uint32_t XMC_BCCU_ReadFlickerWDThreshold (XMC_BCCU_t *const bccu)
727 {
728 return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_WDMBN_Msk) >> BCCU_GLOBCON_WDMBN_Pos);
729 }
730
731 /**
732 *
733 * @param bccu Base address of the bccu module. \b Range: BCCU0
734 * @param div Prescaler factor. \b Range: 0 to 4095.
735 *
736 * @return None
737 *
738 * \par<b>Description:</b><br>
739 * Configures trigger functionality clock prescaler factor of a BCCU module by writing register bit GLOBCLK_FCLK_PS.\n\n
740 *
741 * \par<b>Related APIs:</b><BR>
742 * XMC_BCCU_SetDimClockPrescaler(), XMC_BCCU_SelectBitClock(), XMC_BCCU_ReadFastClock()\n\n\n
743 */
744 void XMC_BCCU_SetFastClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div);
745
746 /**
747 *
748 * @param bccu Base address of the bccu module. \b Range: BCCU0
749 *
750 * @return Prescaler factor. \b Range: 0 to 4095
751 * \par<b>Description:</b><br>
752 * Retrieves fast clock prescaler factor of a BCCU module by reading the register bit GLOBCLK_FCLK_PS. The fast clock is
753 * derived from the bccu clock by prescaler factor i.e. fdclk = fbccu_clk / prescaler factor.\n\n
754 *
755 * \par<b>Related APIs:</b><BR>
756 * XMC_BCCU_SetFastClockPrescaler(), XMC_BCCU_ReadBitClock(), XMC_BCCU_ReadDimClock()\n\n\n
757 */
XMC_BCCU_ReadFastClock(XMC_BCCU_t * const bccu)758 __STATIC_INLINE uint32_t XMC_BCCU_ReadFastClock (XMC_BCCU_t *const bccu)
759 {
760 return (uint32_t)(((bccu->GLOBCLK) & BCCU_GLOBCLK_FCLK_PS_Msk) >> BCCU_GLOBCLK_FCLK_PS_Pos);
761 }
762
763 /**
764 *
765 * @param bccu Base address of the bccu module. \b Range: BCCU0
766 * @param div Prescaler factor. \b Range: 0 to 4095.
767 *
768 * @return None
769 *
770 * \par<b>Description:</b><br>
771 * Configures dimmer clock prescaler factor of a BCCU module by writing register bit GLOBCLK_DCLK_PS.\n\n
772 *
773 * \par<b>Related APIs:</b><BR>
774 * XMC_BCCU_DIM_SetDimDivider(), XMC_BCCU_SetFastClockPrescaler(), XMC_BCCU_SelectBitClock(), XMC_BCCU_ReadDimClock()\n\n\n
775 */
776 void XMC_BCCU_SetDimClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div);
777
778 /**
779 *
780 * @param bccu Base address of the bccu module. \b Range: BCCU0
781 *
782 * @return Prescaler factor. \b Range: 0 to 4095
783 * \par<b>Description:</b><br>
784 * Retrieves dimmer clock prescaler factor of a BCCU module by reading the register bit GLOBCLK_DCLK_PS. The dim clock is
785 * derived from the bccu clock by prescaler factor. \n i.e. <b> fdclk = fbccu_clk / prescaler factor.</b>\n\n
786 *
787 * \par<b>Related APIs:</b><BR>
788 * XMC_BCCU_SetDimClockPrescaler(), XMC_BCCU_ReadBitClock(), XMC_BCCU_ReadFastClock()\n\n\n
789 */
XMC_BCCU_ReadDimClock(XMC_BCCU_t * const bccu)790 __STATIC_INLINE uint32_t XMC_BCCU_ReadDimClock (XMC_BCCU_t *const bccu)
791 {
792 return (uint32_t)(((bccu->GLOBCLK) & BCCU_GLOBCLK_DCLK_PS_Msk) >> BCCU_GLOBCLK_DCLK_PS_Pos);
793 }
794
795 /**
796 *
797 * @param bccu Base address of the bccu module. \b Range: BCCU0
798 * @param div Prescaler factor. Use type @ref XMC_BCCU_BCLK_MODE_t. \n
799 * \b Range: XMC_BCCU_BCLK_MODE_NORMAL or XMC_BCCU_BCLK_MODE_FAST. \n
800 * @return None
801 *
802 * \par<b>Description:</b><br>
803 * Configures modulator output (bit-time) clock prescaler factor of a BCCU module by writing register bit GLOBCLK_BCS.\n\n
804 *
805 * \par<b>Related APIs:</b><BR>
806 * XMC_BCCU_SetFastClockPrescaler(), XMC_BCCU_SetDimClockPrescaler(), XMC_BCCU_ReadBitClock()\n\n\n
807 */
808 void XMC_BCCU_SelectBitClock (XMC_BCCU_t *const bccu, XMC_BCCU_BCLK_MODE_t div);
809
810 /**
811 *
812 * @param bccu Base address of the bccu module. \b Range: BCCU0
813 *
814 * @return Prescaler factor. \b Range: 0 or 1 \n
815 * 0 - XMC_BCCU_BCLK_MODE_NORMAL \n
816 * 1 - XMC_BCCU_BCLK_MODE_FAST \n
817 * \par<b>Description:</b><br>
818 * Retrieves modulator output (bit-time) clock prescaler factor of a BCCU module by reading the register bit GLOBCLK_BCS.
819 * Use XMC_BCCU_BCLK_MODE_t type to validate a returned value.\n\n
820 *
821 * \par<b>Related APIs:</b><BR>
822 * XMC_BCCU_SelectBitClock(), XMC_BCCU_ReadDimClock(), XMC_BCCU_ReadFastClock()\n\n\n
823 */
XMC_BCCU_ReadBitClock(XMC_BCCU_t * const bccu)824 __STATIC_INLINE uint32_t XMC_BCCU_ReadBitClock (XMC_BCCU_t *const bccu)
825 {
826 return (uint32_t)(((bccu->GLOBCLK) & BCCU_GLOBCLK_BCS_Msk) >> BCCU_GLOBCLK_BCS_Pos);
827 }
828
829 /**
830 *
831 * @param bccu Base address of the bccu module. \b Range: BCCU0
832 * @param mask Channel mask to enable multiple channels.\n
833 * <b>For example:</b> If channel 0, channel 7, channel 1 wants to enable at a same time, \n
834 * then channel mask is 01000 0011 = 0x83\n
835 * ------------------------------------------------------------------------------------------------------\n
836 * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\n
837 * ------------------------------------------------------------------------------------------------------\n
838 *
839 * @return None
840 *
841 * \par<b>Description:</b><br>
842 * Enables multiple channels at a same time using \a mask by writing a register CHEN.\n\n
843 *
844 * \par<b>Related APIs:</b><BR>
845 * XMC_BCCU_EnableChannel(), XMC_BCCU_ConcurrentDisableChannels()\n\n\n
846 */
847 void XMC_BCCU_ConcurrentEnableChannels (XMC_BCCU_t *const bccu, uint32_t mask);
848
849 /**
850 *
851 * @param bccu Base address of the bccu module. \b Range: BCCU0
852 * @param mask Channel mask to disable multiple channels.\n
853 * <b>For example:</b> If channel 0, channel 7, channel 1 wants to disable at a same time, \n
854 * then channel mask is 01000 0011 = 0x83\n
855 * ------------------------------------------------------------------------------------------------------\n
856 * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\n
857 * ------------------------------------------------------------------------------------------------------\n
858 *
859 * @return None
860 *
861 * \par<b>Description:</b><br>
862 * Disables multiple channels at a same time using \a mask by writing a register CHEN.\n\n
863 *
864 * \par<b>Related APIs:</b><BR>
865 * XMC_BCCU_ConcurrentEnableChannels(), XMC_BCCU_DisableChannel()\n\n\n
866 */
867 void XMC_BCCU_ConcurrentDisableChannels (XMC_BCCU_t *const bccu, uint32_t mask);
868
869 /**
870 *
871 * @param bccu Base address of the bccu module. \b Range: BCCU0
872 * @param chan_mask Channel mask to enable multiple channels.\n
873 * <b>For example:</b> If channel 0, channel 7, channel 1 wants to enable at a same time, \n
874 * then channel mask is 01000 0011 = 0x83\n
875 * ------------------------------------------------------------------------------------------------------\n
876 * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\n
877 * ------------------------------------------------------------------------------------------------------\n
878 * @param level Passive level selection. Use type @ref XMC_BCCU_CH_ACTIVE_LEVEL_t.\n
879 * \b Range: XMC_BCCU_CH_ACTIVE_LEVEL_HIGH or XMC_BCCU_CH_ACTIVE_LEVEL_LOW
880 *
881 * @return None
882 *
883 * \par<b>Description:</b><br>
884 * Configures passive levels of multiple channels at a same time using \a mask by writing a register bit CHOCON_CHyOP.\n\n
885 *
886 * \par<b>Related APIs:</b><BR>
887 * XMC_BCCU_SetOutputPassiveLevel()\n\n\n
888 */
889 void XMC_BCCU_ConcurrentSetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level);
890
891 /**
892 *
893 * @param bccu Base address of the bccu module. \b Range: BCCU0
894 * @param mask Channel mask to enable multiple channels trap functionality.\n
895 * <b>For example:</b> If channel 0, channel 7, channel 1 wants to enable a trap functionality at a same time, \n
896 * then channel mask is 01000 0011 = 0x83\n
897 * ------------------------------------------------------------------------------------------------------\n
898 * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\n
899 * ------------------------------------------------------------------------------------------------------\n
900 *
901 * @return None
902 *
903 * \par<b>Description:</b><br>
904 * Enables multiple channels trap functionality at the same time using \a mask by writing a register bit CHOCON_CHyTPE.\n\n
905 *
906 * \par<b>Related APIs:</b><BR>
907 * XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentDisableTrap(), XMC_BCCU_SelectTrapInput(), XMC_BCCU_SetTrapEdge()\n\n\n
908 */
909 void XMC_BCCU_ConcurrentEnableTrap (XMC_BCCU_t *const bccu, uint32_t mask);
910
911 /**
912 *
913 * @param bccu Base address of the bccu module. \b Range: BCCU0
914 * @param mask Channel mask to disable multiple channels trap functionality.
915 * <b>For example:</b> If channel 0, channel 7, channel 1 wants to disable a trap functionality at a same time, \n
916 * then channel mask is 01000 0011 = 0x83\n
917 * ------------------------------------------------------------------------------------------------------\n
918 * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\n
919 * ------------------------------------------------------------------------------------------------------\n
920 *
921 * @return None
922 *
923 * \par<b>Description:</b><br>
924 * Disables multiple channels trap functionality at the same time using \a mask by writing a register bit CHOCON_CHyTPE.\n\n
925 *
926 * \par<b>Related APIs:</b><BR>
927 * XMC_BCCU_DisableTrap(), XMC_BCCU_ConcurrentEnableTrap()\n\n\n
928 */
929 void XMC_BCCU_ConcurrentDisableTrap (XMC_BCCU_t *const bccu, uint32_t mask);
930
931 /**
932 *
933 * @param bccu Base address of the bccu module. \b Range: BCCU0
934 * @param trig Pointer to a trigger configuration data structure. Use type @ref XMC_BCCU_TRIG_CONFIG_t.
935 *
936 * @return None
937 *
938 * \par<b>Description:</b><br>
939 * Configures global trigger settings: trigger mode, trigger delay, individual trigger lines and channel mask by writing a \n
940 * registers GLOBCON and CHTRIG. Trigger mode decides when to generate a BCCU trigger, trigger delay postpones the channel \n
941 * trigger by 1/4, or 1/2 bclk cycles\n\n
942 *
943 * \par<b>Related APIs:</b><BR>
944 * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ReadLastTrigChanNr(), XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_GlobalInit()\n\n\n
945 */
946 void XMC_BCCU_ConcurrentConfigTrigger (XMC_BCCU_t *const bccu, XMC_BCCU_TRIG_CONFIG_t *trig);
947
948 /**
949 *
950 * @param bccu Base address of the bccu module. \b Range: BCCU0
951 * @param mask Channel mask to start a linear walk for multiple channels at a same time.\n
952 * <b>For example:</b> If channel 0, channel 7, channel 1 wants to start a linear walk at a same time, \n
953 * then channel mask is 01000 0011 = 0x83\n
954 * ------------------------------------------------------------------------------------------------------\n
955 * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\n
956 * ------------------------------------------------------------------------------------------------------\n
957 *
958 * @return None
959 *
960 * \par<b>Description:</b><br>
961 * After channel initialization, the outcome of executing the API starts changing the color smoothly towards to target \n
962 * for multiple channels at a same time using \a mask by writing a register CHSTRCON.\n\n
963 *
964 * \par<b>Related APIs:</b><BR>
965 * XMC_BCCU_StartLinearWalk(), XMC_BCCU_ConcurrentAbortLinearWalk()\n\n\n
966 */
967 void XMC_BCCU_ConcurrentStartLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask);
968
969 /**
970 *
971 * @param bccu Base address of the bccu module. \b Range: BCCU0
972 * @param mask Channel mask to stop a linear walk for multiple channels at a same time.\n
973 * <b>For example:</b> If channel 0, channel 7, channel 1 wants to abort a linear walk at a same time, \n
974 * then channel mask is 01000 0011 = 0x83\n
975 * ------------------------------------------------------------------------------------------------------\n
976 * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\n
977 * ------------------------------------------------------------------------------------------------------\n
978 *
979 * @return None
980 *
981 * \par<b>Description:</b><br>
982 * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change)
983 * immediately for multiple channels at a same time using \a mask by writing a register CHSTRCON.\n\n
984 *
985 * \par<b>Related APIs:</b><BR>
986 * XMC_BCCU_AbortLinearWalk(), XMC_BCCU_ConcurrentStartLinearWalk()\n\n\n
987 */
988 void XMC_BCCU_ConcurrentAbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask);
989
990 /**
991 *
992 * @param bccu Base address of the bccu module. \b Range: BCCU0
993 * @param mask Dimming engine mask to enable multiple dimming engine at a same time.\n
994 * <b>For example:</b> If dimming engine 0, channel 2 wants to enable a dimming at a same time,
995 * then dimming engine mask is 0101 = 0x03\n
996 * --------------------------\n
997 * | DE2 | DE1 | DE0 |\n
998 * --------------------------\n
999 *
1000 * @return None
1001 *
1002 * \par<b>Description:</b><br>
1003 * Enables multiple dimming engines at a same time using \a mask by writing a register DEEN.\n\n
1004 *
1005 * \par<b>Related APIs:</b><BR>
1006 * XMC_BCCU_EnableDimmingEngine(), XMC_BCCU_ConcurrentDisableDimmingEngine()\n\n\n
1007 */
1008 void XMC_BCCU_ConcurrentEnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask);
1009
1010 /**
1011 *
1012 * @param bccu Base address of the bccu module. \b Range: BCCU0
1013 * @param mask Dimming engine mask to disable multiple dimming engine at a same time.\n
1014 * <b>For example:</b> If dimming engine 0, channel 2 wants to disable a dimming at a same time,
1015 * then dimming engine mask is 0101 = 0x03\n
1016 * --------------------------\n
1017 * | DE2 | DE1 | DE0 |\n
1018 * --------------------------\n
1019 *
1020 * @return None
1021 *
1022 * \par<b>Description:</b><br>
1023 * Disables multiple dimming engines at a same time using \a mask by writing a register DEEN.\n\n
1024 *
1025 * \par<b>Related APIs:</b><BR>
1026 * XMC_BCCU_DisableDimmingEngine(), XMC_BCCU_ConcurrentEnableDimmingEngine()\n\n\n
1027 */
1028 void XMC_BCCU_ConcurrentDisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask);
1029
1030 /**
1031 *
1032 * @param bccu Base address of the bccu module. \b Range: BCCU0
1033 * @param mask Dimming engine mask to start a dimming for multiple dimming engines at a same time.\n
1034 * <b>For example:</b> If dimming engine 0, channel 2 wants to start a dimming at a same time,
1035 * then dimming engine mask is 0101 = 0x03\n
1036 * --------------------------\n
1037 * | DE2 | DE1 | DE0 |\n
1038 * --------------------------\n
1039 *
1040 * @return None
1041 *
1042 * \par<b>Description:</b><br>
1043 * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target
1044 * for multiple dimming engines at a same time using \a mask by writing a register DESTRCON.\n\n
1045 *
1046 * \par<b>Related APIs:</b><BR>
1047 * XMC_BCCU_StartDimming(), XMC_BCCU_ConcurrentAbortDimming()\n\n\n
1048 */
1049 void XMC_BCCU_ConcurrentStartDimming (XMC_BCCU_t *const bccu, uint32_t mask);
1050
1051 /**
1052 *
1053 * @param bccu Base address of the bccu module. \b Range: BCCU0
1054 * @param mask Dimming engine mask to abort a dimming for multiple dimming engines at a same time.\n
1055 * <b>For example:</b> If dimming engine 0, channel 2 wants to abort a dimming at a same time,
1056 * then dimming engine mask is 0101 = 0x03\n
1057 * --------------------------\n
1058 * | DE2 | DE1 | DE0 |\n
1059 * --------------------------\n
1060 *
1061 * @return None
1062 *
1063 * \par<b>Description:</b><br>
1064 * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading)
1065 * immediately for specific dimming engine number \a dim_no by writing a register DESTRCON.\n\n
1066 *
1067 * \par<b>Related APIs:</b><BR>
1068 * XMC_BCCU_AbortDimming(), XMC_BCCU_ConcurrentStartDimming()\n\n\n
1069 */
1070 void XMC_BCCU_ConcurrentAbortDimming (XMC_BCCU_t *const bccu, uint32_t mask);
1071
1072 /**
1073 *
1074 * @param bccu Base address of the bccu module. \b Range: BCCU0
1075 * @param level Dimming level of global dimming engine. \b Range: 0 to 4095\n
1076 *
1077 * @return None
1078 *
1079 * \par<b>Description:</b><br>
1080 * Configures a global dimming level by writing a register GLOBDIM. This is useful only if global dimming engine selected.
1081 * Otherwise the configuration is ignored. \n\n
1082 *
1083 * \par<b>Related APIs:</b><BR>
1084 * XMC_BCCU_DIM_SetTargetDimmingLevel()\n\n\n
1085 */
1086 void XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level);
1087
1088 /**
1089 *
1090 * @param bccu Base address of the bccu module. \b Range: BCCU0
1091 * @param event Event mask to enable multiple events at a time using ORed values of @ref XMC_BCCU_EVENT_t.\n
1092 * <b>For example:</b> If XMC_BCCU_EVENT_TRIGGER0, XMC_BCCU_EVENT_TRIGGER1, XMC_BCCU_EVENT_FIFOEMPTY wants to enable
1093 * at a same time,\n then event mask is = <b>(XMC_BCCU_EVENT_TRIGGER0 | XMC_BCCU_EVENT_TRIGGER1 |
1094 * XMC_BCCU_EVENT_FIFOEMPTY) </b> \n
1095 *
1096 * @return None
1097 *
1098 * \par<b>Description:</b><br>
1099 * Enables multiple interrupt events at a same time using ORed values of @ref XMC_BCCU_EVENT_t by writing a register EVIER.\n\n
1100 *
1101 * \par<b>Related APIs:</b><BR>
1102 * XMC_BCCU_DisableInterrupt()\n\n\n
1103 */
XMC_BCCU_EnableInterrupt(XMC_BCCU_t * const bccu,uint32_t event)1104 __STATIC_INLINE void XMC_BCCU_EnableInterrupt (XMC_BCCU_t *const bccu, uint32_t event)
1105 {
1106 bccu->EVIER |= event;
1107 }
1108
1109 /**
1110 *
1111 * @param bccu Base address of the bccu module. \b Range: BCCU0
1112 * @param event Event mask to disable multiple events at a time using ORed values of @ref XMC_BCCU_EVENT_t.\n
1113 * <b>For example:</b> If XMC_BCCU_EVENT_TRIGGER0, XMC_BCCU_EVENT_TRIGGER1, XMC_BCCU_EVENT_FIFOEMPTY wants to disable\n
1114 * at a same time, then event mask is = <b>(XMC_BCCU_EVENT_TRIGGER0 | XMC_BCCU_EVENT_TRIGGER1 |
1115 * XMC_BCCU_EVENT_FIFOEMPTY)</b> \n
1116 *
1117 * @return None
1118 *
1119 * \par<b>Description:</b><br>
1120 * Disables multiple interrupt events at a same time using ORed values of @ref XMC_BCCU_EVENT_t by writing a register EVIER.\n\n
1121 *
1122 * \par<b>Related APIs:</b><BR>
1123 * XMC_BCCU_EnableInterrupt()\n\n\n
1124 */
XMC_BCCU_DisableInterrupt(XMC_BCCU_t * const bccu,uint32_t event)1125 __STATIC_INLINE void XMC_BCCU_DisableInterrupt (XMC_BCCU_t *const bccu, uint32_t event)
1126 {
1127 bccu->EVIER &= (uint32_t)~(event);
1128 }
1129
1130 /**
1131 *
1132 * @param bccu Base address of the bccu module. \b Range: BCCU0
1133 *
1134 * @return Interrupt events flags at a same time using ORed values of @ref XMC_BCCU_EVENT_t.
1135 * \par<b>Description:</b><br>
1136 * Retrieves interrupt event flags at the same time using ORed values of @ref XMC_BCCU_EVENT_t by reading the register \n
1137 * EVFR. \n\n
1138 *
1139 * \par<b>Related APIs:</b><BR>
1140 * XMC_BCCU_SetEventFlag()\n\n\n
1141 */
XMC_BCCU_ReadEventFlag(XMC_BCCU_t * const bccu)1142 __STATIC_INLINE uint32_t XMC_BCCU_ReadEventFlag (XMC_BCCU_t *const bccu)
1143 {
1144 return (bccu->EVFR);
1145 }
1146
1147 /**
1148 *
1149 * @param bccu Base address of the bccu module. \b Range: BCCU0
1150 * @param flag_type Event flag mask to configure multiple events at a time using ORed values of @ref
1151 * XMC_BCCU_EVENT_STATUS_t.\n
1152 * <b>For example:</b> If XMC_BCCU_EVENT_STATUS_TRIGGER0, XMC_BCCU_EVENT_STATUS_TRIGGER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY
1153 * wants to configure at a same time, then event mask is = <b>(XMC_BCCU_EVENT_STATUS_TRIGGER0 | XMC_BCCU_EVENT_STATUS_TRIGGER1 |
1154 * XMC_BCCU_EVENT_STATUS_FIFOEMPTY)</b> \n
1155 *
1156 * @return None
1157 *
1158 * \par<b>Description:</b><br>
1159 * Configures multiple interrupt event flags at a same time using ORed values of @ref XMC_BCCU_EVENT_STATUS_t by writing a register EVFSR.\n\n
1160 *
1161 * \par<b>Related APIs:</b><BR>
1162 * XMC_BCCU_ClearEventFlag(), XMC_BCCU_ReadEventFlag()\n\n\n
1163 */
XMC_BCCU_SetEventFlag(XMC_BCCU_t * const bccu,uint32_t flag_type)1164 __STATIC_INLINE void XMC_BCCU_SetEventFlag (XMC_BCCU_t *const bccu, uint32_t flag_type)
1165 {
1166 bccu->EVFSR = flag_type;
1167 }
1168
1169 /**
1170 *
1171 * @param bccu Base address of the bccu module. \b Range: BCCU0
1172 * @param flag_type event flag mask to clear multiple events at a time using ORed values of @ref
1173 * XMC_BCCU_EVENT_STATUS_t.\n
1174 * <b>For example:</b> If XMC_BCCU_EVENT_STATUS_TRIGGER0, XMC_BCCU_EVENT_STATUS_TRIGGER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY
1175 * wants to clear at a same time, then event mask is = <b>(XMC_BCCU_EVENT_STATUS_TRIGGER0 | XMC_BCCU_EVENT_STATUS_TRIGGER1 |
1176 * XMC_BCCU_EVENT_STATUS_FIFOEMPTY)</b> \n
1177 *
1178 * @return None
1179 *
1180 * \par<b>Description:</b><br>
1181 * Clears multiple interrupt event flags at a same time using ORed values of @ref XMC_BCCU_EVENT_STATUS_t by writing a
1182 * register EVFSR.\n\n
1183 *
1184 * \par<b>Related APIs:</b><BR>
1185 * XMC_BCCU_SetEventFlag()\n\n\n
1186 */
XMC_BCCU_ClearEventFlag(XMC_BCCU_t * const bccu,uint32_t flag_type)1187 __STATIC_INLINE void XMC_BCCU_ClearEventFlag (XMC_BCCU_t *const bccu, uint32_t flag_type)
1188 {
1189 bccu->EVFCR = flag_type;
1190 }
1191
1192 /**
1193 *
1194 * @param bccu Base address of the bccu module. \b Range: BCCU0
1195 * @param chan_no Specific channel number to enable. \b Range: 0 to 8\n
1196 *
1197 * @return None
1198 *
1199 * \par<b>Description:</b><br>
1200 * Enables a specific channel number using \a chan_no by writing a register CHEN.\n\n
1201 *
1202 * \par<b>Related APIs:</b><BR>
1203 * XMC_BCCU_ConcurrentEnableChannels(), XMC_BCCU_DisableChannel()\n\n\n
1204 */
1205 void XMC_BCCU_EnableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no);
1206
1207 /**
1208 *
1209 * @param bccu Base address of the bccu module. \b Range: BCCU0
1210 * @param chan_no Specific channel number to disable. \b Range: 0 to 8\n
1211 *
1212 * @return None
1213 *
1214 * \par<b>Description:</b><br>
1215 * Disables a specific channel number using \a chan_no by writing a register CHEN.\n\n
1216 *
1217 * \par<b>Related APIs:</b><BR>
1218 * XMC_BCCU_ConcurrentDisableChannels(), XMC_BCCU_EnableChannel()\n\n\n
1219 */
1220 void XMC_BCCU_DisableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no);
1221
1222 /**
1223 *
1224 * @param bccu Base address of the bccu module. \b Range: BCCU0
1225 * @param chan_no Specific channel number to enable specific channel. \b Range: 0 to 8\n
1226 * @param level Passive level selection. Use type @ref XMC_BCCU_CH_ACTIVE_LEVEL_t.\n
1227 * \b Range: XMC_BCCU_CH_ACTIVE_LEVEL_HIGH or XMC_BCCU_CH_ACTIVE_LEVEL_LOW
1228 *
1229 * @return None
1230 *
1231 * \par<b>Description:</b><br>
1232 * Configures passive level of specific channel using \a chan_no by writing a register bit CHOCON_CHyOP.\n\n
1233 *
1234 * \par<b>Related APIs:</b><BR>
1235 * XMC_BCCU_ConcurrentSetOutputPassiveLevel()\n\n\n
1236 */
1237 void XMC_BCCU_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level);
1238
1239 /**
1240 *
1241 * @param bccu Base address of the bccu module. \b Range: BCCU0
1242 * @param chan_no Channel number to enable specific channel trap functionality. \b Range: 0 to 8
1243 *
1244 * @return None
1245 *
1246 * \par<b>Description:</b><br>
1247 * Enables specific channel trap functionality using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n
1248 *
1249 * \par<b>Related APIs:</b><BR>
1250 * XMC_BCCU_DisableTrap(), XMC_BCCU_ConcurrentEnableTrap(), XMC_BCCU_SelectTrapInput(), XMC_BCCU_SetTrapEdge()\n\n\n
1251 */
1252 void XMC_BCCU_EnableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no);
1253
1254 /**
1255 *
1256 * @param bccu Base address of the bccu module. \b Range: BCCU0
1257 * @param chan_no Channel number to disable specific channel trap functionality. \b Range: 0 to 8
1258 *
1259 * @return None
1260 *
1261 * \par<b>Description:</b><br>
1262 * Disables specific channel trap functionality using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n
1263 *
1264 * \par<b>Related APIs:</b><BR>
1265 * XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentDisableTrap()\n\n\n
1266 */
1267 void XMC_BCCU_DisableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no);
1268
1269 /**
1270 *
1271 * @param bccu Base address of the bccu module. \b Range: BCCU0
1272 * @param chan_no Channel number to trigger a specific channel. \b Range: 0 to 8
1273 * @param trig_line Trigger line number to trigger a vadc. Use type @ref XMC_BCCU_CH_TRIGOUT_t.\n
1274 * \b Range: XMC_BCCU_CH_TRIGOUT0 or XMC_BCCU_CH_TRIGOUT1
1275 *
1276 * @return None
1277 *
1278 * \par<b>Description:</b><br>
1279 * Enables specific channel trigger using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n
1280 *
1281 * \par<b>Related APIs:</b><BR>
1282 * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_DisableChannelTrigger(), XMC_BCCU_CH_ConfigTrigger()\n\n\n
1283 */
1284 void XMC_BCCU_EnableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_TRIGOUT_t trig_line);
1285
1286 /**
1287 *
1288 * @param bccu Base address of the bccu module. \b Range: BCCU0
1289 * @param chan_no Channel number to trigger a specific channel. \b Range: 0 to 8
1290 *
1291 * @return None
1292 *
1293 * \par<b>Description:</b><br>
1294 * Disables specific channel trigger using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n
1295 *
1296 * \par<b>Related APIs:</b><BR>
1297 * XMC_BCCU_EnableChannelTrigger()\n\n\n
1298 */
1299 void XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no);
1300
1301 /**
1302 *
1303 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1304 * @param config Pointer to constant bccu channel configuration data structure. Use type @ref XMC_BCCU_CH_CONFIG_t.
1305 *
1306 * @return None
1307 *
1308 * \par<b>Description:</b><br>
1309 * Configures dimming engine source, dimming bypass selection, channel trigger edge, flicker watchdog selection and force
1310 * trigger selection by using \a dim_sel, \a dim_bypass, \a trig_edge, \a flick_wd_en, \a force_trig_en by writing into a
1311 * CHCONFIG register. And also configures packer settings: threshold, off and on compare levels, initial values of off & on
1312 * counters, by writing into a CHCONFIG, PKCMP and PKCNTR registers.\n\n
1313 *
1314 * \par<b>Related APIs:</b><BR>
1315 * XMC_BCCU_GlobalInit(), XMC_BCCU_DIM_Init()\n\n\n
1316 */
1317 void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config);
1318
1319 /**
1320 *
1321 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1322 * @param edge Output transition selection. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t. \n
1323 * \b Range: XMC_BCCU_CH_TRIG_EDGE_PASS_TO_ACT or XMC_BCCU_CH_TRIG_EDGE_ACT_TO_PASS\n
1324 * @param force_trig_en Forcing a trigger at output. \b Range: 0 or 1\n
1325 * Generates a trigger if modulator output do not change for 256 bclk cycles\n
1326 *
1327 * @return None
1328 *
1329 * \par<b>Description:</b><br>
1330 * Configures global trigger settings: trigger edge, force trigger enable by writing a register CHCONFIG.
1331 * And also configures force trigger enable, generates a trigger if modulator output do not change for 256 bclk cycles
1332 *
1333 * \par<b>Related APIs:</b><BR>
1334 * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_EnableChannelTrigger()\n\n\n
1335 */
1336 void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_t force_trig_en);
1337
1338 /**
1339 *
1340 * @param bccu Base address of the bccu module. \b Range: BCCU0
1341 * @param chan_no Specific channel number to start color change \b Range: 0 to 8\n
1342 *
1343 * @return None
1344 *
1345 * \par<b>Description:</b><br>
1346 * After channel initialization, the outcome of executing the API starts changing the color smoothly towards to target
1347 * by writing a register bit CHSTRCON_CHyS.\n\n
1348 *
1349 * \par<b>Related APIs:</b><BR>
1350 * XMC_BCCU_AbortLinearWalk(), XMC_BCCU_CH_SetTargetIntensity(), XMC_BCCU_IsLinearWalkComplete(),
1351 * XMC_BCCU_ConcurrentStartLinearWalk()\n\n\n
1352 */
XMC_BCCU_StartLinearWalk(XMC_BCCU_t * const bccu,uint32_t chan_no)1353 __STATIC_INLINE void XMC_BCCU_StartLinearWalk (XMC_BCCU_t *const bccu, uint32_t chan_no)
1354 {
1355 bccu->CHSTRCON |= (uint32_t)(BCCU_CHSTRCON_CH0S_Msk << chan_no);
1356 }
1357
1358 /**
1359 *
1360 * @param bccu Base address of the bccu module. \b Range: BCCU0
1361 * @param chan_no Specific channel number to stop color change \b Range: 0 to 8\n
1362 *
1363 * @return None
1364 *
1365 * \par<b>Description:</b><br>
1366 * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change)
1367 * immediately for specific channels number using \a mask by writing a register CHSTRCON_CHyA.\n\n
1368 *
1369 * \par<b>Related APIs:</b><BR>
1370 * XMC_BCCU_StartLinearWalk(), XMC_BCCU_ConcurrentAbortLinearWalk()\n\n\n
1371 */
XMC_BCCU_AbortLinearWalk(XMC_BCCU_t * const bccu,uint32_t chan_no)1372 __STATIC_INLINE void XMC_BCCU_AbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t chan_no)
1373 {
1374 bccu->CHSTRCON |= (uint32_t)(BCCU_CHSTRCON_CH0A_Msk << chan_no);
1375 }
1376
1377 /**
1378 *
1379 * @param bccu Base address of the bccu module. \b Range: BCCU0
1380 * @param chan_no Specific channel number to get an output level on last trigger. \b Range: 0 to 8\n
1381 *
1382 * @return Trap channel output level. \b Range: 0 or 1
1383 * \par<b>Description:</b><br>
1384 * Retrieves output level of specific channel number when last trigger occurred by reading the register bit LTCHOL_LTOLy. \n\n
1385 *
1386 * \par<b>Related APIs:</b><BR>
1387 * XMC_BCCU_ReadLastTrigChanNr(), XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(),
1388 * XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_GlobalInit()\n\n\n
1389 */
XMC_BCCU_GetChannelOutputLvlAtLastTrigger(XMC_BCCU_t * const bccu,uint32_t chan_no)1390 __STATIC_INLINE uint32_t XMC_BCCU_GetChannelOutputLvlAtLastTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no)
1391 {
1392 return (uint32_t)((bccu->LTCHOL & (BCCU_LTCHOL_LTOL0_Msk << chan_no)) >> chan_no);
1393 }
1394
1395 /**
1396 *
1397 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1398 * @param clk_div Prescaler factor. \b Range: 0 to 1023
1399 *
1400 * @return None
1401 *
1402 * \par<b>Description:</b><br>
1403 * configure the linear walker clock prescaler factor by writing register bit CHCONFIG_LINPRES.\n\n
1404 *
1405 */
1406 void XMC_BCCU_CH_SetLinearWalkPrescaler (XMC_BCCU_CH_t *const channel, uint32_t clk_div);
1407
1408 /**
1409 *
1410 * @param bccu Base address of the bccu module. \b Range: BCCU0
1411 * @param chan_no Channel number to know the linear walk completion status. \b Range: 0 to 8\n
1412 *
1413 * @return Linear walk completion status. \b Range: 0-Completed or 1-intensity start changing towards the target
1414 * \par<b>Description:</b><br>
1415 * Retrieves linear walk completion status for specific channel using \a chan_no by reading the register bit CHSTRCON_CHyS. \n\n
1416 *
1417 * \par<b>Related APIs:</b><BR>
1418 * XMC_BCCU_CH_SetTargetIntensity(), XMC_BCCU_StartLinearWalk()\n\n\n
1419 */
XMC_BCCU_IsLinearWalkComplete(XMC_BCCU_t * const bccu,uint32_t chan_no)1420 __STATIC_INLINE uint32_t XMC_BCCU_IsLinearWalkComplete (XMC_BCCU_t *const bccu, uint32_t chan_no)
1421 {
1422 return (uint32_t)((bccu->CHSTRCON & (BCCU_CHSTRCON_CH0S_Msk << chan_no)) >> chan_no);
1423 }
1424
1425 /**
1426 *
1427 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1428 * @param ch_int Target channel intensity. \b Range: 0 to 4095
1429 *
1430 * @return None
1431 *
1432 * \par<b>Description:</b><br>
1433 * Configures target channel intensity by writing register INTS, only be written if no shadow transfer of linear walk.
1434 * Use XMC_BCCU_IsLinearWalkComplete() to know shadow transfer finished \n\n
1435 *
1436 * \par<b>Related APIs:</b><BR>
1437 * XMC_BCCU_IsLinearWalkComplete(), XMC_BCCU_StartLinearWalk(), XMC_BCCU_CH_ReadIntensity()\n\n\n
1438 */
1439 void XMC_BCCU_CH_SetTargetIntensity (XMC_BCCU_CH_t *const channel, uint32_t ch_int);
1440
1441 /**
1442 *
1443 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1444 *
1445 * @return Current channel intensity. \b Range: 0 or 4095
1446 * \par<b>Description:</b><br>
1447 * Retrieves current channel intensity by reading the register INT.\n\n
1448 *
1449 * \par<b>Related APIs:</b><BR>
1450 * XMC_BCCU_CH_SetTargetIntensity()\n\n\n
1451 */
1452 uint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel);
1453
1454 /**
1455 *
1456 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1457 * @param thresh Packer threshold value of FIFO. It defines number of queue stages must be filled before output generator
1458 * starts generating the pulses. Until that, only off-bits are generated at the output.\n
1459 * @param off_comp Packer off-time compare level. When the off-time counter reaches this, the measured on off time
1460 * counters are stored into FIFO
1461 * @param on_comp Packer on-time compare level. When the on-time counter reaches this, the measured on & off time
1462 * counters are stored into FIFO
1463 *
1464 * @return None
1465 *
1466 * \par<b>Description:</b><br>
1467 * Enables packer by writing register bit CHCONFIG_PEN. And also configures packer threshold, off and on compare levels
1468 * by writing register PKCMP. The main purpose of the packer is to decrease the average rate of switching of the output
1469 * signal, to decrease the load on external switching circuits and improve EMC behavior\n\n
1470 *
1471 * \par<b>Related APIs:</b><BR>
1472 * XMC_BCCU_CH_DisablePacker(), XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCompare\n\n\n
1473 */
1474 void XMC_BCCU_CH_EnablePacker (XMC_BCCU_CH_t *const channel, uint32_t thresh, uint32_t off_comp, uint32_t on_comp);
1475
1476 /**
1477 *
1478 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1479 * @param val Packer threshold value of FIFO
1480 *
1481 * @return None
1482 *
1483 * \par<b>Description:</b><br>
1484 * Configures packer threshold by writing register bit CHCONFIG_PKTH\n\n
1485 *
1486 * \par<b>Related APIs:</b><BR>
1487 * XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCompare, XMC_BCCU_CH_ReadPackerThreshold()\n\n\n
1488 */
1489 void XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val);
1490
1491 /**
1492 *
1493 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1494 * @param level Packer off-time compare level. When the off-time counter reaches this, the measured on & off time counters
1495 * are stored into FIFO
1496 *
1497 * @return None
1498 *
1499 * \par<b>Description:</b><br>
1500 * Configures packer off compare level by writing register bit PKCMP_OFFCMP\n\n
1501 *
1502 * \par<b>Related APIs:</b><BR>
1503 * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOnCompare(), XMC_BCCU_CH_SetPackerOffCounter(),
1504 * XMC_BCCU_CH_ReadPackerOffCompare()\n\n\n
1505 */
1506 void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level);
1507
1508 /**
1509 *
1510 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1511 * @param level Packer on-time compare level. When the on-time counter reaches this, the measured on & off time counters
1512 * are stored into FIFO
1513 *
1514 * @return None
1515 *
1516 * \par<b>Description:</b><br>
1517 * Configures packer on compare level by writing register bit PKCMP_ONCMP\n\n
1518 *
1519 * \par<b>Related APIs:</b><BR>
1520 * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCounter(),
1521 * XMC_BCCU_CH_ReadPackerOnCompare()\n\n\n
1522 */
1523 void XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level);
1524
1525 /**
1526 *
1527 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1528 *
1529 * @return Packer threshold value of FIFO
1530 * \par<b>Description:</b><br>
1531 * Retrieves packer threshold value by reading the register bit CHCONFIG_PKTH.\n\n
1532 *
1533 * \par<b>Related APIs:</b><BR>
1534 * XMC_BCCU_CH_SetPackerThreshold()\n\n\n
1535 */
XMC_BCCU_CH_ReadPackerThreshold(XMC_BCCU_CH_t * const channel)1536 __STATIC_INLINE uint32_t XMC_BCCU_CH_ReadPackerThreshold (XMC_BCCU_CH_t *const channel)
1537 {
1538 return (uint32_t)((channel->CHCONFIG) & BCCU_CH_CHCONFIG_PKTH_Msk);
1539 }
1540
1541 /**
1542 *
1543 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1544 *
1545 * @return Packer off-time compare level. When the off-time counter reaches this, the measured on & off time counters
1546 * are stored into FIFO
1547 * \par<b>Description:</b><br>
1548 * Retrieves packer off compare level by reading the register bit PKCMP_OFFCMP.\n\n
1549 *
1550 * \par<b>Related APIs:</b><BR>
1551 * XMC_BCCU_CH_SetPackerOffCompare()\n\n\n
1552 */
XMC_BCCU_CH_ReadPackerOffCompare(XMC_BCCU_CH_t * const channel)1553 __STATIC_INLINE uint32_t XMC_BCCU_CH_ReadPackerOffCompare (XMC_BCCU_CH_t *const channel)
1554 {
1555 return (uint32_t)((channel->PKCMP) & BCCU_CH_PKCMP_OFFCMP_Msk);
1556 }
1557
1558 /**
1559 *
1560 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1561 *
1562 * @return Packer on-time compare level. When the on-time counter reaches this, <br>
1563 * the measured on & off time counters are stored into FIFO
1564 * \par<b>Description:</b><br>
1565 * Retrieves packer on compare level by reading the register bit PKCMP_ONCMP.\n\n
1566 *
1567 * \par<b>Related APIs:</b><BR>
1568 * XMC_BCCU_CH_SetPackerOnCompare()\n\n\n
1569 */
XMC_BCCU_CH_ReadPackerOnCompare(XMC_BCCU_CH_t * const channel)1570 __STATIC_INLINE uint32_t XMC_BCCU_CH_ReadPackerOnCompare (XMC_BCCU_CH_t *const channel)
1571 {
1572 return (uint32_t)(((channel->PKCMP) & BCCU_CH_PKCMP_ONCMP_Msk) >> BCCU_CH_PKCMP_ONCMP_Pos);
1573 }
1574
1575 /**
1576 *
1577 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1578 *
1579 * @return None
1580 *
1581 * \par<b>Description:</b><br>
1582 * Disables packer by clearing writing register bit CHCONFIG_PEN. \n\n
1583 *
1584 * \par<b>Related APIs:</b><BR>
1585 * XMC_BCCU_CH_EnablePacker()\n\n\n
1586 */
1587 void XMC_BCCU_CH_DisablePacker (XMC_BCCU_CH_t *const channel);
1588
1589 /**
1590 *
1591 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1592 * @param cnt_val Configures an initial packer off-time counter level, only if channel is disabled. Controls phase
1593 * shift of the modulator output
1594 *
1595 * @return None
1596 *
1597 * \par<b>Description:</b><br>
1598 * Configures packer initial off counter value by writing register bit PKCNTR_OFFCNTVAL\n
1599 * Note: Shall only be called if channel disabled.\n\n
1600 *
1601 * \par<b>Related APIs:</b><BR>
1602 * XMC_BCCU_CH_SetPackerOnCounter(), XMC_BCCU_CH_SetPackerOffCompare()\n\n\n
1603 */
1604 void XMC_BCCU_CH_SetPackerOffCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val);
1605
1606 /**
1607 *
1608 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1609 * @param cnt_val Configures an initial packer on-time counter level, only if channel is disabled. Controls phase shift
1610 * of the modulator output
1611 *
1612 * @return None
1613 *
1614 * \par<b>Description:</b><br>
1615 * Configures packer initial on counter value by writing register bit PKCNTR_ONCNTVAL\n
1616 * Note: Shall only be called if channel disabled.\n\n
1617 *
1618 * \par<b>Related APIs:</b><BR>
1619 * XMC_BCCU_CH_SetPackerOffCounter(), XMC_BCCU_CH_SetPackerOnCompare()\n\n\n
1620 */
1621 void XMC_BCCU_CH_SetPackerOnCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val);
1622
1623 /**
1624 *
1625 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1626 * @param sel Selects a dimming engine source of the channel. Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t
1627 *
1628 * @return None
1629 *
1630 * \par<b>Description:</b><br>
1631 * Configures dimming engine source by writing register bit CHCONFIG_DSEL\n\n
1632 *
1633 * \par<b>Related APIs:</b><BR>
1634 * XMC_BCCU_CH_EnableDimmingBypass()\n\n\n
1635 */
1636 void XMC_BCCU_CH_SelectDimEngine (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_DIMMING_SOURCE_t sel);
1637
1638 /**
1639 *
1640 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1641 *
1642 * @return None
1643 *
1644 * \par<b>Description:</b><br>
1645 * Enables dimming engine bypass by writing register bit CHCONFIG_DBP. \n\n
1646 *
1647 * \par<b>Related APIs:</b><BR>
1648 * XMC_BCCU_CH_SelectDimEngine(), XMC_BCCU_CH_DisableDimmingBypass()\n\n\n
1649 */
1650 void XMC_BCCU_CH_EnableDimmingBypass (XMC_BCCU_CH_t *const channel);
1651
1652 /**
1653 *
1654 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1655 *
1656 * @return None
1657 *
1658 * \par<b>Description:</b><br>
1659 * Disables dimming engine bypass by clearing register bit CHCONFIG_DBP. \n\n
1660 *
1661 * \par<b>Related APIs:</b><BR>
1662 * XMC_BCCU_CH_EnableDimmingBypass()\n\n\n
1663 */
1664 void XMC_BCCU_CH_DisableDimmingBypass (XMC_BCCU_CH_t *const channel);
1665
1666 /**
1667 *
1668 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1669 *
1670 * @return None
1671 *
1672 * \par<b>Description:</b><br>
1673 * Enables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable fast control schemes,
1674 * such as peak-current control and this has been controlled by Analog Comparator module.\n\n
1675 *
1676 * \par<b>Related APIs:</b><BR>
1677 * XMC_BCCU_CH_DisableGating()\n\n\n
1678 */
XMC_BCCU_CH_EnableGating(XMC_BCCU_CH_t * const channel)1679 __STATIC_INLINE void XMC_BCCU_CH_EnableGating (XMC_BCCU_CH_t *const channel)
1680 {
1681 channel->CHCONFIG |= (uint32_t)(BCCU_CH_CHCONFIG_GEN_Msk);
1682 }
1683
1684 /**
1685 *
1686 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1687 *
1688 * @return None
1689 *
1690 * \par<b>Description:</b><br>
1691 * Disables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable/disable fast control
1692 * schemes, such as peak-current control and this has been controlled by Analog Comparator module. \n\n
1693 *
1694 * \par<b>Related APIs:</b><BR>
1695 * XMC_BCCU_CH_EnableGating()\n\n\n
1696 */
XMC_BCCU_CH_DisableGating(XMC_BCCU_CH_t * const channel)1697 __STATIC_INLINE void XMC_BCCU_CH_DisableGating (XMC_BCCU_CH_t *const channel)
1698 {
1699 channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_GEN_Msk);
1700 }
1701
1702 /**
1703 *
1704 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1705 *
1706 * @return None
1707 *
1708 * \par<b>Description:</b><br>
1709 * Enables flicker watchdog by writing register bit CHCONFIG_WEN. And limits the sigma-delta modulator output\n
1710 * according to Watchdog threshold\n\n
1711 *
1712 * \par<b>Related APIs:</b><BR>
1713 * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(),
1714 * XMC_BCCU_CH_DisableFlickerWatchdog()\n\n\n
1715 */
XMC_BCCU_CH_EnableFlickerWatchdog(XMC_BCCU_CH_t * const channel)1716 __STATIC_INLINE void XMC_BCCU_CH_EnableFlickerWatchdog (XMC_BCCU_CH_t *const channel)
1717 {
1718 channel->CHCONFIG |= (uint32_t)(BCCU_CH_CHCONFIG_WEN_Msk);
1719 }
1720
1721 /**
1722 *
1723 * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..
1724 *
1725 * @return None
1726 *
1727 * \par<b>Description:</b><br>
1728 * Disables flicker watchdog by writing register bit CHCONFIG_WEN. No limits the sigma-delta modulator output
1729 * according to Watchdog threshold\n\n
1730 *
1731 * \par<b>Related APIs:</b><BR>
1732 * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(),
1733 * XMC_BCCU_CH_EnableFlickerWatchdog()\n\n\n
1734 */
XMC_BCCU_CH_DisableFlickerWatchdog(XMC_BCCU_CH_t * const channel)1735 __STATIC_INLINE void XMC_BCCU_CH_DisableFlickerWatchdog (XMC_BCCU_CH_t *const channel)
1736 {
1737 channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_WEN_Msk);
1738 }
1739
1740 /**
1741 *
1742 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1743 * @param config Pointer to constant dimming engine configuration data structure. Use type @ref XMC_BCCU_DIM_CONFIG_t.
1744 *
1745 * @return None
1746 *
1747 * \par<b>Description:</b><br>
1748 * Configures dimming clock divider to adjust the fade rate, dither selection and exponential curve selection using \a
1749 * dim_div, \a dither_en, \a cur_sel parameters and by writing into a DTT register.\n\n
1750 *
1751 * \par<b>Related APIs:</b><BR>
1752 * XMC_BCCU_GlobalInit(), XMC_BCCU_CH_Init()\n\n\n
1753 */
1754 void XMC_BCCU_DIM_Init (XMC_BCCU_DIM_t *const dim_engine, const XMC_BCCU_DIM_CONFIG_t *const config);
1755
1756 /**
1757 *
1758 * @param bccu Base address of the bccu module. \b Range: BCCU0
1759 * @param dim_no Specific dimming engine number to enable. \b Range: 0 to 2\n
1760 *
1761 * @return None
1762 *
1763 * \par<b>Description:</b><br>
1764 * Enables a specific dimming engine number using \a dim_no by writing a register bit DEEN_EDEy.\n\n
1765 *
1766 * \par<b>Related APIs:</b><BR>
1767 * XMC_BCCU_DisableDimmingEngine(), XMC_BCCU_ConcurrentEnableDimmingEngine()\n\n\n
1768 */
XMC_BCCU_EnableDimmingEngine(XMC_BCCU_t * const bccu,uint32_t dim_no)1769 __STATIC_INLINE void XMC_BCCU_EnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t dim_no)
1770 {
1771 bccu->DEEN |= (uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no);
1772 }
1773
1774 /**
1775 *
1776 * @param bccu Base address of the bccu module. \b Range: BCCU0
1777 * @param dim_no Specific dimming engine number to disable. \b Range: 0 to 2\n
1778 *
1779 * @return None
1780 *
1781 * \par<b>Description:</b><br>
1782 * Disables a specific dimming engine number using \a dim_no by clearing a register bit DEEN_EDEy.\n\n
1783 *
1784 * \par<b>Related APIs:</b><BR>
1785 * XMC_BCCU_EnableDimmingEngine(), XMC_BCCU_ConcurrentDisableDimmingEngine()\n\n\n
1786 */
XMC_BCCU_DisableDimmingEngine(XMC_BCCU_t * const bccu,uint32_t dim_no)1787 __STATIC_INLINE void XMC_BCCU_DisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t dim_no)
1788 {
1789 bccu->DEEN &= ~(uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no);
1790 }
1791
1792 /**
1793 *
1794 * @param bccu Base address of the bccu module. \b Range: BCCU0
1795 * @param dim_no Specific dimming engine number to start dimming process \b Range: 0 to 2\n
1796 *
1797 * @return None
1798 *
1799 * \par<b>Description:</b><br>
1800 * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target
1801 * by writing a register bit DESTRCON_DEyS.\n\n
1802 *
1803 * \par<b>Related APIs:</b><BR>
1804 * XMC_BCCU_AbortDimming(), XMC_BCCU_ConcurrentStartDimming()\n\n\n
1805 */
XMC_BCCU_StartDimming(XMC_BCCU_t * const bccu,uint32_t dim_no)1806 __STATIC_INLINE void XMC_BCCU_StartDimming (XMC_BCCU_t *const bccu, uint32_t dim_no)
1807 {
1808 bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0S_Msk << dim_no);
1809 }
1810
1811 /**
1812 *
1813 * @param bccu Base address of the bccu module. \b Range: BCCU0
1814 * @param dim_no Specific dimming engine number to stop dimming process \b Range: 0 to 2\n
1815 *
1816 * @return None
1817 *
1818 * \par<b>Description:</b><br>
1819 * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading)
1820 * immediately for specific dimming engine number \a dim_no by writing a register bit DESTRCON_DEyA.\n\n
1821 *
1822 * \par<b>Related APIs:</b><BR>
1823 * XMC_BCCU_StartDimming(), XMC_BCCU_ConcurrentAbortDimming()\n\n\n
1824 */
XMC_BCCU_AbortDimming(XMC_BCCU_t * const bccu,uint32_t dim_no)1825 __STATIC_INLINE void XMC_BCCU_AbortDimming (XMC_BCCU_t *const bccu, uint32_t dim_no)
1826 {
1827 bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0A_Msk << dim_no);
1828 }
1829
1830 /**
1831 *
1832 * @param bccu Base address of the bccu module. \b Range: BCCU0
1833 * @param dim_no Specific dimming engine number to know the dimming status. \b Range: 0 to 2\n
1834 *
1835 * @return Dimming completion status. \b Range: 0-Completed or 1-start change towards the target
1836 * \par<b>Description:</b><br>
1837 * Retrieves dimming completion status for specific dimming engine number using \a dim_no by reading the register bit
1838 * DESTRCON_DEyS. \n\n
1839 *
1840 * \par<b>Related APIs:</b><BR>
1841 * XMC_BCCU_DIM_SetTargetDimmingLevel(), XMC_BCCU_StartDimming()\n\n\n
1842 */
XMC_BCCU_IsDimmingFinished(XMC_BCCU_t * const bccu,uint32_t dim_no)1843 __STATIC_INLINE uint32_t XMC_BCCU_IsDimmingFinished (XMC_BCCU_t *const bccu, uint32_t dim_no)
1844 {
1845 return (uint32_t)((bccu->DESTRCON & (BCCU_DESTRCON_DE0S_Msk << dim_no)) >> dim_no);
1846 }
1847
1848 /**
1849 *
1850 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1851 * @param level Target dimming level. \b Range: 0 to 4095
1852 *
1853 * @return None
1854 *
1855 * \par<b>Description:</b><br>
1856 * Configures target dimming level by writing register DLS, only be written if no shadow transfer of dimming.
1857 * Use XMC_BCCU_IsDimmingFinished() to know shadow transfer finished \n\n
1858 *
1859 * \par<b>Related APIs:</b><BR>
1860 * XMC_BCCU_StartDimming(), XMC_BCCU_IsDimmingFinished(), XMC_BCCU_SetGlobalDimmingLevel(), \n
1861 * XMC_BCCU_DIM_ReadDimmingLevel()\n\n\n
1862 */
1863 void XMC_BCCU_DIM_SetTargetDimmingLevel (XMC_BCCU_DIM_t *const dim_engine, uint32_t level);
1864
1865 /**
1866 *
1867 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1868 *
1869 * @return Current dimming level. \b Range: 0 or 4095
1870 * \par<b>Description:</b><br>
1871 * Retrieves current dimming level by reading the register DE_DL_DLEV.\n\n
1872 *
1873 * \par<b>Related APIs:</b><BR>
1874 * XMC_BCCU_DIM_SetTargetDimmingLevel()\n\n\n
1875 */
XMC_BCCU_DIM_ReadDimmingLevel(XMC_BCCU_DIM_t * const dim_engine)1876 __STATIC_INLINE uint32_t XMC_BCCU_DIM_ReadDimmingLevel (XMC_BCCU_DIM_t *const dim_engine)
1877 {
1878 return (uint32_t)(dim_engine->DL & BCCU_DE_DL_DLEV_Msk);
1879 }
1880
1881 /**
1882 *
1883 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1884 * @param div Dimming clock divider, used to adjust the fade rate. If 0, the dimming level
1885 as same as target dimming level on shadow transfer\n
1886 *
1887 * @return None
1888 *
1889 * \par<b>Description:</b><br>
1890 * Configures dimming clock divider by writing register bit DE_DTT_DIMDIV.\n\n
1891 *
1892 * \par<b>Related APIs:</b><BR>
1893 * XMC_BCCU_SetDimClockPrescaler(), XMC_BCCU_DIM_ReadDimDivider()\n\n\n
1894 */
1895 void XMC_BCCU_DIM_SetDimDivider (XMC_BCCU_DIM_t *const dim_engine, uint32_t div);
1896
1897 /**
1898 *
1899 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1900 *
1901 * @return Dimming clock divider value. \b Range: 0 to 1023
1902 * \par<b>Description:</b><br>
1903 * Retrieves dimming clock divider value by reading the register BCCU_DE_DTT_DIMDIV.\n\n
1904 *
1905 * \par<b>Related APIs:</b><BR>
1906 * XMC_BCCU_DIM_SetDimDivider()\n\n\n
1907 */
XMC_BCCU_DIM_ReadDimDivider(XMC_BCCU_DIM_t * const dim_engine)1908 __STATIC_INLINE uint32_t XMC_BCCU_DIM_ReadDimDivider(XMC_BCCU_DIM_t *const dim_engine)
1909 {
1910 return (uint32_t)(dim_engine->DTT & BCCU_DE_DTT_DIMDIV_Msk);
1911 }
1912
1913 /**
1914 *
1915 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1916 * @param dither_en Dither enable. Dithering added for every dimming step if dimming level < 128. <br>
1917 * @param sel Type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. Note: If dither
1918 enabled, the configuration is being ignored\n
1919 *
1920 * @return None
1921 *
1922 * \par<b>Description:</b><br>
1923 * Configures dimming clock curve by writing register bit DE_DTT_CSEL.\n\n
1924 *
1925 * \par<b>Related APIs:</b><BR>
1926 * XMC_BCCU_DIM_Init()\n\n\n
1927 */
1928 void XMC_BCCU_DIM_ConfigDimCurve (XMC_BCCU_DIM_t *const dim_engine, uint32_t dither_en, XMC_BCCU_DIM_CURVE_t sel);
1929
1930 /**
1931 *
1932 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1933 *
1934 * @return Type of exponential curve \b Range: XMC_BCCU_DIM_CURVE_COARSE or XMC_BCCU_DIM_CURVE_FINE
1935 * \par<b>Description:</b><br>
1936 * Retrieves exponential curve type by reading the register bit BCCU_DE_DTT_CSEL. \n\n
1937 *
1938 * \par<b>Related APIs:</b><BR>
1939 * XMC_BCCU_DIM_ConfigDimCurve(), XMC_BCCU_IsDitherEnable()\n\n\n
1940 */
XMC_BCCU_DIM_GetDimCurve(XMC_BCCU_DIM_t * const dim_engine)1941 __STATIC_INLINE XMC_BCCU_DIM_CURVE_t XMC_BCCU_DIM_GetDimCurve (XMC_BCCU_DIM_t *const dim_engine)
1942 {
1943 return (XMC_BCCU_DIM_CURVE_t)((dim_engine->DTT & BCCU_DE_DTT_CSEL_Msk) >> BCCU_DE_DTT_CSEL_Pos);
1944 }
1945
1946 /**
1947 *
1948 * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2
1949 *
1950 * @return Dither enable status. \b Range: 1-Enabled or 0-Disabled
1951 * \par<b>Description:</b><br>
1952 * Retrieves dither enable status by reading the register bit BCCU_DE_DTT_DTEN. \n\n
1953 *
1954 * \par<b>Related APIs:</b><BR>
1955 * XMC_BCCU_DIM_ConfigDimCurve(), XMC_BCCU_DIM_GetDimCurve()\n\n\n
1956 */
XMC_BCCU_IsDitherEnable(XMC_BCCU_DIM_t * const dim_engine)1957 __STATIC_INLINE uint32_t XMC_BCCU_IsDitherEnable(XMC_BCCU_DIM_t *const dim_engine)
1958 {
1959 return (uint32_t)((dim_engine->DTT & BCCU_DE_DTT_DTEN_Msk) >> BCCU_DE_DTT_DTEN_Pos);
1960 }
1961
1962 /**
1963 * @}
1964 */
1965
1966 /**
1967 * @}
1968 */
1969
1970 #ifdef __cplusplus
1971 }
1972 #endif
1973
1974 #endif /* BCCU0 */
1975
1976 #endif /* XMC_BCCU_H */
1977
