1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _ADDRESSMAP_H 9 #define _ADDRESSMAP_H 10 11 /** 12 * \file rp2040/addressmap.h 13 */ 14 15 #include "hardware/platform_defs.h" 16 17 // Register address offsets for atomic RMW aliases 18 #define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) 19 #define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) 20 #define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) 21 #define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) 22 23 #define ROM_BASE _u(0x00000000) 24 #define XIP_BASE _u(0x10000000) 25 #define XIP_MAIN_BASE _u(0x10000000) 26 #define XIP_NOALLOC_BASE _u(0x11000000) 27 #define XIP_NOCACHE_BASE _u(0x12000000) 28 #define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000) 29 #define XIP_CTRL_BASE _u(0x14000000) 30 #define XIP_SRAM_BASE _u(0x15000000) 31 #define XIP_SRAM_END _u(0x15004000) 32 #define XIP_SSI_BASE _u(0x18000000) 33 #define SRAM_BASE _u(0x20000000) 34 #define SRAM_STRIPED_BASE _u(0x20000000) 35 #define SRAM_STRIPED_END _u(0x20040000) 36 #define SRAM4_BASE _u(0x20040000) 37 #define SRAM5_BASE _u(0x20041000) 38 #define SRAM_END _u(0x20042000) 39 #define SRAM0_BASE _u(0x21000000) 40 #define SRAM1_BASE _u(0x21010000) 41 #define SRAM2_BASE _u(0x21020000) 42 #define SRAM3_BASE _u(0x21030000) 43 #define SYSINFO_BASE _u(0x40000000) 44 #define SYSCFG_BASE _u(0x40004000) 45 #define CLOCKS_BASE _u(0x40008000) 46 #define RESETS_BASE _u(0x4000c000) 47 #define PSM_BASE _u(0x40010000) 48 #define IO_BANK0_BASE _u(0x40014000) 49 #define IO_QSPI_BASE _u(0x40018000) 50 #define PADS_BANK0_BASE _u(0x4001c000) 51 #define PADS_QSPI_BASE _u(0x40020000) 52 #define XOSC_BASE _u(0x40024000) 53 #define PLL_SYS_BASE _u(0x40028000) 54 #define PLL_USB_BASE _u(0x4002c000) 55 #define BUSCTRL_BASE _u(0x40030000) 56 #define UART0_BASE _u(0x40034000) 57 #define UART1_BASE _u(0x40038000) 58 #define SPI0_BASE _u(0x4003c000) 59 #define SPI1_BASE _u(0x40040000) 60 #define I2C0_BASE _u(0x40044000) 61 #define I2C1_BASE _u(0x40048000) 62 #define ADC_BASE _u(0x4004c000) 63 #define PWM_BASE _u(0x40050000) 64 #define TIMER_BASE _u(0x40054000) 65 #define WATCHDOG_BASE _u(0x40058000) 66 #define RTC_BASE _u(0x4005c000) 67 #define ROSC_BASE _u(0x40060000) 68 #define VREG_AND_CHIP_RESET_BASE _u(0x40064000) 69 #define TBMAN_BASE _u(0x4006c000) 70 #define DMA_BASE _u(0x50000000) 71 #define USBCTRL_DPRAM_BASE _u(0x50100000) 72 #define USBCTRL_BASE _u(0x50100000) 73 #define USBCTRL_REGS_BASE _u(0x50110000) 74 #define PIO0_BASE _u(0x50200000) 75 #define PIO1_BASE _u(0x50300000) 76 #define XIP_AUX_BASE _u(0x50400000) 77 #define SIO_BASE _u(0xd0000000) 78 #define PPB_BASE _u(0xe0000000) 79 80 #endif // _ADDRESSMAP_H 81 82
