1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30 #include "EmbeddedTypes.h"
31 #include "fsl_device_registers.h"
32 #include "fsl_common.h"
33 #include "fsl_xcvr.h"
34 #include "fsl_xcvr_trim.h"
35 #include <math.h>
36 #include "ifr_radio.h"
37
38 /*******************************************************************************
39 * Definitions
40 ******************************************************************************/
41 #define channelMapTableSize (128U)
42 #define gPllDenom_c 0x02000000U /* Denominator is a constant value */
43 #define ABS(x) ((x) > 0 ? (x) : -(x))
44
45 #ifndef TRUE
46 #define TRUE (true)
47 #endif
48
49 #ifndef FALSE
50 #define FALSE (false)
51 #endif
52 #define RF_OSCILLATOR_STAYS_ON (false) /* Control whether RF_OSC can be left on all the time. */
53 #define RF_OSCILLATOR_READY ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U)
54
55 #ifndef EXTERNAL_CLOCK_GEN
56 #define EXTERNAL_CLOCK_GEN 0
57 #endif
58
59 #define ANT_A 1
60 #define ANT_B 0
61
62 #ifndef XCVR_COEX_RF_ACTIVE_PIN
63 #define XCVR_COEX_RF_ACTIVE_PIN ANT_B
64 #endif /* XCVR_COEX_RF_ACTIVE_PIN */
65
66 typedef struct xcvr_pllChannel_tag
67 {
68 unsigned int integer;
69 unsigned int numerator;
70 } xcvr_pllChannel_t;
71
72 /*******************************************************************************
73 * Prototypes
74 ******************************************************************************/
75 void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address);
76 void rf_osc_startup(void);
77 void rf_osc_shutdown(void);
78 extern double trunc (double);
79 extern double round (double);
80
81 /*******************************************************************************
82 * Variables
83 ******************************************************************************/
84 static panic_fptr s_PanicFunctionPtr = NULL;
85 const xcvr_pllChannel_t mapTable [channelMapTableSize] =
86 {
87 {0x00000025, 0x07C00000}, /* 0 */
88 {0x00000025, 0x07C80000}, /* 1 */
89 {0x00000025, 0x07D00000}, /* 2 */
90 {0x00000025, 0x07D80000}, /* 3 */
91 {0x00000025, 0x07E00000}, /* 4 */
92 {0x00000025, 0x07E80000}, /* 5 */
93 {0x00000025, 0x07F00000}, /* 6 */
94 {0x00000025, 0x07F80000}, /* 7 */
95 {0x00000025, 0x00000000}, /* 8 */
96 {0x00000025, 0x00080000}, /* 9 */
97 {0x00000025, 0x00100000}, /* 10 */
98 {0x00000025, 0x00180000}, /* 11 */
99 {0x00000025, 0x00200000}, /* 12 */
100 {0x00000025, 0x00280000}, /* 13 */
101 {0x00000025, 0x00300000}, /* 14 */
102 {0x00000025, 0x00380000}, /* 15 */
103 {0x00000025, 0x00400000}, /* 16 */
104 {0x00000025, 0x00480000}, /* 17 */
105 {0x00000025, 0x00500000}, /* 18 */
106 {0x00000025, 0x00580000}, /* 19 */
107 {0x00000025, 0x00600000}, /* 20 */
108 {0x00000025, 0x00680000}, /* 21 */
109 {0x00000025, 0x00700000}, /* 22 */
110 {0x00000025, 0x00780000}, /* 23 */
111 {0x00000025, 0x00800000}, /* 24 */
112 {0x00000025, 0x00880000}, /* 25 */
113 {0x00000025, 0x00900000}, /* 26 */
114 {0x00000025, 0x00980000}, /* 27 */
115 {0x00000025, 0x00A00000}, /* 28 */
116 {0x00000025, 0x00A80000}, /* 29 */
117 {0x00000025, 0x00B00000}, /* 30 */
118 {0x00000025, 0x00B80000}, /* 31 */
119 {0x00000025, 0x00C00000}, /* 32 */
120 {0x00000025, 0x00C80000}, /* 33 */
121 {0x00000025, 0x00D00000}, /* 34 */
122 {0x00000025, 0x00D80000}, /* 35 */
123 {0x00000025, 0x00E00000}, /* 36 */
124 {0x00000025, 0x00E80000}, /* 37 */
125 {0x00000025, 0x00F00000}, /* 38 */
126 {0x00000025, 0x00F80000}, /* 39 */
127 {0x00000025, 0x01000000}, /* 40 */
128 {0x00000026, 0x07080000}, /* 41 */
129 {0x00000026, 0x07100000}, /* 42 */
130 {0x00000026, 0x07180000}, /* 43 */
131 {0x00000026, 0x07200000}, /* 44 */
132 {0x00000026, 0x07280000}, /* 45 */
133 {0x00000026, 0x07300000}, /* 46 */
134 {0x00000026, 0x07380000}, /* 47 */
135 {0x00000026, 0x07400000}, /* 48 */
136 {0x00000026, 0x07480000}, /* 49 */
137 {0x00000026, 0x07500000}, /* 50 */
138 {0x00000026, 0x07580000}, /* 51 */
139 {0x00000026, 0x07600000}, /* 52 */
140 {0x00000026, 0x07680000}, /* 53 */
141 {0x00000026, 0x07700000}, /* 54 */
142 {0x00000026, 0x07780000}, /* 55 */
143 {0x00000026, 0x07800000}, /* 56 */
144 {0x00000026, 0x07880000}, /* 57 */
145 {0x00000026, 0x07900000}, /* 58 */
146 {0x00000026, 0x07980000}, /* 59 */
147 {0x00000026, 0x07A00000}, /* 60 */
148 {0x00000026, 0x07A80000}, /* 61 */
149 {0x00000026, 0x07B00000}, /* 62 */
150 {0x00000026, 0x07B80000}, /* 63 */
151 {0x00000026, 0x07C00000}, /* 64 */
152 {0x00000026, 0x07C80000}, /* 65 */
153 {0x00000026, 0x07D00000}, /* 66 */
154 {0x00000026, 0x07D80000}, /* 67 */
155 {0x00000026, 0x07E00000}, /* 68 */
156 {0x00000026, 0x07E80000}, /* 69 */
157 {0x00000026, 0x07F00000}, /* 70 */
158 {0x00000026, 0x07F80000}, /* 71 */
159 {0x00000026, 0x00000000}, /* 72 */
160 {0x00000026, 0x00080000}, /* 73 */
161 {0x00000026, 0x00100000}, /* 74 */
162 {0x00000026, 0x00180000}, /* 75 */
163 {0x00000026, 0x00200000}, /* 76 */
164 {0x00000026, 0x00280000}, /* 77 */
165 {0x00000026, 0x00300000}, /* 78 */
166 {0x00000026, 0x00380000}, /* 79 */
167 {0x00000026, 0x00400000}, /* 80 */
168 {0x00000026, 0x00480000}, /* 81 */
169 {0x00000026, 0x00500000}, /* 82 */
170 {0x00000026, 0x00580000}, /* 83 */
171 {0x00000026, 0x00600000}, /* 84 */
172 {0x00000026, 0x00680000}, /* 85 */
173 {0x00000026, 0x00700000}, /* 86 */
174 {0x00000026, 0x00780000}, /* 87 */
175 {0x00000026, 0x00800000}, /* 88 */
176 {0x00000026, 0x00880000}, /* 89 */
177 {0x00000026, 0x00900000}, /* 90 */
178 {0x00000026, 0x00980000}, /* 91 */
179 {0x00000026, 0x00A00000}, /* 92 */
180 {0x00000026, 0x00A80000}, /* 93 */
181 {0x00000026, 0x00B00000}, /* 94 */
182 {0x00000026, 0x00B80000}, /* 95 */
183 {0x00000026, 0x00C00000}, /* 96 */
184 {0x00000026, 0x00C80000}, /* 97 */
185 {0x00000026, 0x00D00000}, /* 98 */
186 {0x00000026, 0x00D80000}, /* 99 */
187 {0x00000026, 0x00E00000}, /* 100 */
188 {0x00000026, 0x00E80000}, /* 101 */
189 {0x00000026, 0x00F00000}, /* 102 */
190 {0x00000026, 0x00F80000}, /* 103 */
191 {0x00000026, 0x01000000}, /* 104 */
192 {0x00000027, 0x07080000}, /* 105 */
193 {0x00000027, 0x07100000}, /* 106 */
194 {0x00000027, 0x07180000}, /* 107 */
195 {0x00000027, 0x07200000}, /* 108 */
196 {0x00000027, 0x07280000}, /* 109 */
197 {0x00000027, 0x07300000}, /* 110 */
198 {0x00000027, 0x07380000}, /* 111 */
199 {0x00000027, 0x07400000}, /* 112 */
200 {0x00000027, 0x07480000}, /* 113 */
201 {0x00000027, 0x07500000}, /* 114 */
202 {0x00000027, 0x07580000}, /* 115 */
203 {0x00000027, 0x07600000}, /* 116 */
204 {0x00000027, 0x07680000}, /* 117 */
205 {0x00000027, 0x07700000}, /* 118 */
206 {0x00000027, 0x07780000}, /* 119 */
207 {0x00000027, 0x07800000}, /* 120 */
208 {0x00000027, 0x07880000}, /* 121 */
209 {0x00000027, 0x07900000}, /* 122 */
210 {0x00000027, 0x07980000}, /* 123 */
211 {0x00000027, 0x07A00000}, /* 124 */
212 {0x00000027, 0x07A80000}, /* 125 */
213 {0x00000027, 0x07B00000}, /* 126 */
214 {0x00000027, 0x07B80000} /* 127 */
215 };
216
217 /* Registers for timing of TX & RX */
218 #if RADIO_IS_GEN_3P0
219 uint16_t tx_rx_on_delay = TX_RX_ON_DELinit;
220 uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init;
221 #else
222 #if RF_OSC_26MHZ == 1
223 uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ;
224 #else
225 uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL;
226 #endif /* RF_OSC_26MHZ == 1 */
227 uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL;
228 #endif /* RADIO_IS_GEN_3P0 */
229
230 /* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */
231 #if RADIO_IS_GEN_3P0
232 const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] =
233 {
234 (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
235 (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
236 (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
237 &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config,
238 &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config,
239 (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
240 (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
241 &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config,
242 &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config,
243 &xcvr_MSK_2mbps_config,
244 };
245 #endif /* RADIO_IS_GEN_3P0 */
246
247 const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] =
248 {
249 &xcvr_BLE_1mbps_config,
250 #if RADIO_IS_GEN_2P1
251 NULL,
252 NULL,
253 #else
254 &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */
255 &xcvr_ANT_1mbps_config,
256 #endif /* RADIO_IS_GEN_2P1 */
257 &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config,
258 &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config,
259 &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config,
260 &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config,
261 &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config,
262 &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config,
263 &xcvr_MSK_1mbps_config,
264 };
265
266 const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] =
267 {
268 &xcvr_BLE_1mbps_config, /* Invalid option */
269 #if RADIO_IS_GEN_2P1
270 NULL,
271 NULL,
272 #else
273 &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */
274 &xcvr_ANT_1mbps_config, /* Invalid option */
275 #endif /* RADIO_IS_GEN_2P1 */
276 &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config,
277 &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config,
278 &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config,
279 &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config,
280 &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config,
281 &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config,
282 &xcvr_MSK_500kbps_config,
283 };
284 const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] =
285 {
286 &xcvr_BLE_1mbps_config, /* Invalid option */
287 #if RADIO_IS_GEN_2P1
288 NULL,
289 NULL,
290 #else
291 &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */
292 &xcvr_ANT_1mbps_config, /* Invalid option */
293 #endif /* RADIO_IS_GEN_2P1 */
294 &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config,
295 &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config,
296 &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config,
297 &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config,
298 &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config,
299 &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config,
300 &xcvr_MSK_250kbps_config,
301 };
302
303 static xcvr_currConfig_t current_xcvr_config;
304
rf_osc_startup(void)305 void rf_osc_startup(void)
306 {
307 if (!RF_OSCILLATOR_READY)
308 {
309 RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK;
310 }
311 while (!RF_OSCILLATOR_READY)
312 {
313 /* Wait for RF_OSC_READY to be asserted before continuing */
314 }
315 }
316
rf_osc_shutdown(void)317 void rf_osc_shutdown(void)
318 {
319 if (!RF_OSCILLATOR_STAYS_ON)
320 {
321 RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK;
322 }
323 }
324
325 /*******************************************************************************
326 * Code
327 ******************************************************************************/
XCVR_Init(radio_mode_t radio_mode,data_rate_t data_rate)328 xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate)
329 {
330 const xcvr_mode_datarate_config_t * mode_datarate_config;
331 const xcvr_datarate_config_t * datarate_config ;
332 const xcvr_mode_config_t * radio_mode_cfg;
333 const xcvr_common_config_t * radio_common_config;
334
335 xcvrStatus_t status;
336
337 IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] =
338 {
339 {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/
340 {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/
341 };
342 const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T);
343
344 #ifndef SIMULATION
345
346 #if (EXTERNAL_CLOCK_GEN)
347 RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */
348 #endif /* EXTERNAL_CLOCK_GEN */
349
350 #if RADIO_IS_GEN_2P0
351 RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */
352 RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */
353 #endif /* RADIO_IS_GEN_2P0 */
354
355 /* Check that this is the proper radio version */
356 {
357 uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT);
358
359 if (
360 #if RADIO_IS_GEN_3P0
361 (radio_id != 0x5) /* KW3 Gen3 */
362 #elif RADIO_IS_GEN_2P1
363 (radio_id != 0x5) /* KW35 Gen2.1 */
364 #else
365 (radio_id != 0x3) && /* KW41/31/21 v1 */
366 (radio_id != 0xB) /* KW41/31/21 v1.1 */
367 #endif /* RADIO_IS_GEN_3P0 */
368 )
369 {
370 XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init);
371 }
372 }
373
374 #if RADIO_IS_GEN_3P0
375 /* Assert Radio Run Request and wait for ack from SPM. */
376 RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK;
377 while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0)
378 {
379 }
380 RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK;
381 rf_osc_startup(); /* Start RF_OSC to allow radio registers access */
382 #else
383 SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK;
384
385 /* Load IFR trim values */
386 handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES);
387 #endif /* RADIO_IS_GEN_3P0 */
388
389 #endif /* ifndef SIMULATION */
390
391 /* Perform the desired XCVR initialization and configuration */
392 status = XCVR_GetDefaultConfig(radio_mode, data_rate,
393 (const xcvr_common_config_t **)&radio_common_config,
394 (const xcvr_mode_config_t **)&radio_mode_cfg,
395 (const xcvr_mode_datarate_config_t **)&mode_datarate_config,
396 (const xcvr_datarate_config_t **)&datarate_config);
397
398 if (status == gXcvrSuccess_c)
399 {
400 status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config,
401 (const xcvr_mode_config_t *)radio_mode_cfg,
402 (const xcvr_mode_datarate_config_t *)mode_datarate_config,
403 (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT);
404 current_xcvr_config.radio_mode = radio_mode;
405 current_xcvr_config.data_rate = data_rate;
406 }
407
408 return status;
409 }
410
XCVR_Deinit(void)411 void XCVR_Deinit(void)
412 {
413 #if RADIO_IS_GEN_3P0
414 rf_osc_shutdown();
415 RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */
416 RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */
417 #else
418
419 #endif /* RADIO_IS_GEN_3P0 */
420 }
421
XCVR_GetDefaultConfig(radio_mode_t radio_mode,data_rate_t data_rate,const xcvr_common_config_t ** com_config,const xcvr_mode_config_t ** mode_config,const xcvr_mode_datarate_config_t ** mode_datarate_config,const xcvr_datarate_config_t ** datarate_config)422 xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode,
423 data_rate_t data_rate,
424 const xcvr_common_config_t ** com_config,
425 const xcvr_mode_config_t ** mode_config,
426 const xcvr_mode_datarate_config_t ** mode_datarate_config,
427 const xcvr_datarate_config_t ** datarate_config)
428 {
429 xcvrStatus_t status = gXcvrSuccess_c;
430 /* Common configuration pointer */
431 *com_config = (const xcvr_common_config_t *)&xcvr_common_config;
432
433 /* Mode dependent configuration pointer */
434 switch (radio_mode)
435 {
436 #if !RADIO_IS_GEN_2P1
437 case ZIGBEE_MODE:
438 *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */
439 break;
440 case ANT_MODE:
441 *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */
442 break;
443 #endif /* !RADIO_IS_GEN_2P1 */
444 case BLE_MODE:
445 *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */
446 break;
447 case GFSK_BT_0p5_h_0p5:
448 *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */
449 break;
450 case GFSK_BT_0p5_h_0p32:
451 *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */
452 break;
453 case GFSK_BT_0p5_h_0p7:
454 *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */
455 break;
456 case GFSK_BT_0p5_h_1p0:
457 *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */
458 break;
459 case GFSK_BT_0p3_h_0p5:
460 *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */
461 break;
462 case GFSK_BT_0p7_h_0p5:
463 *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */
464 break;
465 case MSK:
466 *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */
467 break;
468 default:
469 status = gXcvrInvalidParameters_c;
470 break;
471 }
472
473 /* Data rate dependent and modeXdatarate dependent configuration pointers */
474 if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */
475 {
476 switch (data_rate)
477 {
478 #if RADIO_IS_GEN_3P0
479 case DR_2MBPS:
480 if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE))
481 {
482 status = gXcvrInvalidParameters_c;
483 }
484 else
485 {
486 *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */
487 *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode];
488 }
489 break;
490 #endif /* RADIO_IS_GEN_3P0 */
491 case DR_1MBPS:
492 *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */
493 *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode];
494 break;
495 case DR_500KBPS:
496 if (radio_mode == ZIGBEE_MODE)
497 {
498 /* See fsl_xcvr_zgbe_config.c for settings */
499 #if !RADIO_IS_GEN_2P1
500 *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */
501 #endif /* !RADIO_IS_GEN_2P1 */
502 }
503 else
504 {
505 *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */
506 }
507 *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode];
508 break;
509 case DR_250KBPS:
510 *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */
511 *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode];
512 break;
513 default:
514 status = gXcvrInvalidParameters_c;
515 break;
516 }
517 }
518
519 return status;
520 }
521
XCVR_Configure(const xcvr_common_config_t * com_config,const xcvr_mode_config_t * mode_config,const xcvr_mode_datarate_config_t * mode_datarate_config,const xcvr_datarate_config_t * datarate_config,int16_t tempDegC,XCVR_INIT_MODE_CHG_T first_init)522 xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config,
523 const xcvr_mode_config_t *mode_config,
524 const xcvr_mode_datarate_config_t *mode_datarate_config,
525 const xcvr_datarate_config_t *datarate_config,
526 int16_t tempDegC,
527 XCVR_INIT_MODE_CHG_T first_init)
528 {
529 xcvrStatus_t config_status = gXcvrSuccess_c;
530 uint32_t temp;
531
532 /* Turn on the module clocks before doing anything */
533 #if RADIO_IS_GEN_3P0
534 RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */
535 #else
536 SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits;
537 #endif /* RADIO_IS_GEN_3P0 */
538
539 /*******************************************************************************/
540 /* XCVR_ANA configs */
541 /*******************************************************************************/
542
543 /* Configure PLL Loop Filter */
544 if (first_init)
545 {
546 XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask;
547 XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init;
548 }
549
550 /* Configure VCO KVM */
551 XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask;
552 XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init;
553
554 /* Configure analog filter bandwidth */
555 XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask;
556 XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init;
557 XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask;
558 XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init;
559
560 #if RADIO_IS_GEN_2P0
561 if (first_init)
562 {
563 temp = XCVR_ANA->TX_DAC_PA;
564 temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK;
565 temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4);
566 XCVR_ANA->TX_DAC_PA = temp;
567
568 temp = XCVR_ANA->BB_LDO_2;
569 temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK;
570 temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0);
571 XCVR_ANA->BB_LDO_2 = temp;
572
573 temp = XCVR_ANA->RX_LNA;
574 temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK;
575 temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1);
576 XCVR_ANA->RX_LNA = temp;
577
578 temp = XCVR_ANA->BB_LDO_1;
579 temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK;
580 temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1);
581 XCVR_ANA->BB_LDO_1 = temp;
582 }
583 #endif /* RADIO_IS_GEN_2P0 */
584
585 /*******************************************************************************/
586 /* XCVR_MISC configs */
587 /*******************************************************************************/
588 temp = XCVR_MISC->XCVR_CTRL;
589 temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK);
590 temp |= mode_config->xcvr_ctrl.init;
591
592 #if RF_OSC_26MHZ == 1
593 {
594 temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1);
595 }
596 #endif /* RF_OSC_26MHZ == 1 */
597
598 XCVR_MISC->XCVR_CTRL = temp;
599
600 #if RADIO_IS_GEN_2P1
601 XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK;
602 #endif /* RADIO_IS_GEN_2P1 */
603
604 /*******************************************************************************/
605 /* XCVR_PHY configs */
606 /*******************************************************************************/
607 #if RADIO_IS_GEN_3P0
608 XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0;
609 XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1;
610 XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg;
611 XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate;
612 XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl;
613 #else
614 XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init;
615 XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init;
616 XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init;
617 XCVR_PHY->CFG1 = mode_config->phy_cfg1_init;
618 XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init;
619 XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */
620 #endif /* RADIO_IS_GEN_3P0 */
621
622 /*******************************************************************************/
623 /* XCVR_PLL_DIG configs */
624 /*******************************************************************************/
625 if (first_init)
626 {
627 XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump;
628 XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl;
629 XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map;
630 XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect;
631 XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl;
632 #if !RADIO_IS_GEN_2P1
633 XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl;
634 #endif /* !RADIO_IS_GEN_2P1 */
635 XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res;
636 XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl;
637 XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1;
638 XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match;
639 XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl;
640 }
641
642 /*******************************************************************************/
643 /* XCVR_RX_DIG configs */
644 /*******************************************************************************/
645
646 /* Configure RF Aux PLL for proper operation based on external clock frequency */
647 if (first_init)
648 {
649 temp = XCVR_ANA->RX_AUXPLL;
650 temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK;
651 #if RF_OSC_26MHZ == 1
652 {
653 temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4);
654 }
655 #else
656 {
657 temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7);
658 }
659 #endif /* RF_OSC_26MHZ == 1 */
660 XCVR_ANA->RX_AUXPLL = temp;
661 }
662
663 /* Configure RX_DIG_CTRL */
664 #if RF_OSC_26MHZ == 1
665 {
666 temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */
667 mode_config->rx_dig_ctrl_init_26mhz | /* Mode specific portion of RX_DIG_CTRL init */
668 datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */
669 XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */
670 }
671 #else
672 {
673 temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */
674 mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */
675 datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */
676 0; /* Always disable the sample rate converter for 32MHz */
677 }
678 #endif /* RF_OSC_26MHZ == 1 */
679
680 temp |= com_config->rx_dig_ctrl_init; /* Common portion of RX_DIG_CTRL init */
681 XCVR_RX_DIG->RX_DIG_CTRL = temp;
682
683 /* DCOC_CAL_IIR */
684 #if RF_OSC_26MHZ == 1
685 {
686 XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz;
687 }
688 #else
689 {
690 XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz;
691 }
692 #endif /* RF_OSC_26MHZ == 1 */
693
694 /* DC_RESID_CTRL */
695 #if RF_OSC_26MHZ == 1
696 {
697 XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz;
698 }
699 #else
700 {
701 XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz;
702 }
703 #endif /* RF_OSC_26MHZ == 1 */
704
705 /* DCOC_CTRL_0 & _1 */
706 #if RF_OSC_26MHZ == 1
707 {
708 XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */
709 XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */
710 #if RADIO_IS_GEN_3P0
711 XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz;
712 #endif /* RADIO_IS_GEN_3P0 */
713
714 }
715 #else
716 {
717 XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */
718 XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */
719 #if RADIO_IS_GEN_3P0
720 XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz;
721 #endif /* RADIO_IS_GEN_3P0 */
722 }
723 #endif /* RF_OSC_26MHZ == 1 */
724 if (first_init)
725 {
726 /* DCOC_CAL_GAIN */
727 XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init;
728
729 /* DCOC_CAL_RCP */
730 XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init;
731 XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0;
732 XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4;
733 XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8;
734 XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0;
735 XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8;
736
737 /* LNA_GAIN_LIN_VAL */
738 XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init;
739 XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init;
740 XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init;
741 XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init;
742
743 /* BBA_RES_TUNE_LIN_VAL */
744 XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init;
745 XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init;
746 XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init;
747
748 /* BBA_STEP */
749 XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init;
750
751 /* DCOC_TZA_STEP */
752 XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init;
753 XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init;
754 XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init;
755 XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init;
756 XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init;
757 XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init;
758 XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init;
759 XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init;
760 XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init;
761 XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init;
762 XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init;
763
764 #if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1)
765 /* DCOC_CAL_FAIL and DCOC_CAL_PASS */
766 XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init;
767 XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init;
768 #endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */
769 }
770
771 /* AGC_CTRL_0 .. _3 */
772 XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init;
773
774 #if RF_OSC_26MHZ == 1
775 {
776 XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */
777 XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz;
778 }
779 #else
780 {
781 XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */
782 XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz;
783 }
784 #endif /* RF_OSC_26MHZ == 1 */
785
786 if (first_init)
787 {
788 XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init;
789
790 /* AGC_GAIN_TBL_** */
791 XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init;
792 XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init;
793 XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init;
794 XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init;
795 XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init;
796 XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init;
797 XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init;
798
799 /* RSSI_CTRL_0 */
800 XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init;
801
802 #if RADIO_IS_GEN_3P0
803 XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init;
804 #endif /* RADIO_IS_GEN_3P0 */
805
806 /* CCA_ED_LQI_0 and _1 */
807 XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init;
808 XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init;
809 }
810
811 /* Channel filter coefficients */
812 #if RF_OSC_26MHZ == 1
813 {
814 XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0;
815 XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1;
816 XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2;
817 XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3;
818 XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4;
819 XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5;
820 XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6;
821 XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7;
822 XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8;
823 XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9;
824 XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10;
825 XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11;
826 }
827 #else
828 {
829 XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0;
830 XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1;
831 XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2;
832 XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3;
833 XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4;
834 XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5;
835 XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6;
836 XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7;
837 XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8;
838 XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9;
839 XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10;
840 XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11;
841 }
842 #endif /* RF_OSC_26MHZ == 1 */
843
844 XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0;
845 XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1;
846
847 /*******************************************************************************/
848 /* XCVR_TSM configs */
849 /*******************************************************************************/
850 XCVR_TSM->CTRL = com_config->tsm_ctrl;
851
852 #if RADIO_IS_GEN_2P0
853 if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE))
854 {
855 XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK;
856 }
857 #endif /* RADIO_IS_GEN_2P0 */
858
859 if (first_init)
860 {
861 #if !RADIO_IS_GEN_2P1
862 XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */
863 #endif /* !RADIO_IS_GEN_2P1 */
864
865 XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init;
866 /* TSM registers and timings - dependent upon clock frequency */
867 #if RF_OSC_26MHZ == 1
868 {
869 XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz;
870 XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz;
871 XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz;
872 XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz;
873 XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz;
874 XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz;
875 XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz;
876 XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz;
877 XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz;
878 XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz;
879 XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz;
880 XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz;
881 XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz;
882 XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz;
883 XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz;
884 XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz;
885 XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz;
886 XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz;
887 XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz;
888 XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz;
889 XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz;
890 XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz;
891 }
892 #else
893 {
894 XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz;
895 XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz;
896 XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz;
897 XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz;
898 XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz;
899 XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz;
900 XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz;
901 XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz;
902 XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz;
903 XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz;
904 XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz;
905 XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz;
906 XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz;
907 XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz;
908 XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz;
909 XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz;
910 XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz;
911 XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz;
912 XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz;
913 XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz;
914 XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz;
915 XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz;
916 }
917 #endif /* RF_OSC_26MHZ == 1 */
918
919 /* TSM timings independent of clock frequency */
920 XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init;
921 XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init;
922 XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init;
923 XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init;
924 XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init;
925 XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init;
926 XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init;
927 XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init;
928 XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init;
929 XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init;
930 XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init;
931 XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init;
932 XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init;
933 XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init;
934 XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init;
935 XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init;
936 XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init;
937 XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init;
938 XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init;
939 XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init;
940 XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init;
941 XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init;
942 XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init;
943 XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init;
944 XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init;
945 XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init;
946 XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init;
947 XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init;
948 XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init;
949 XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init;
950 XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init;
951
952 #if RF_OSC_26MHZ == 1
953 {
954 XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) |
955 XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) |
956 XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) |
957 XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ);
958 }
959 #else
960 {
961 XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) |
962 XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) |
963 XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) |
964 XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD);
965 }
966 #endif /* RF_OSC_26MHZ == 1 */
967
968 XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init;
969 XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init;
970
971 #if RADIO_IS_GEN_3P0
972 XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init;
973 XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init;
974
975 /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */
976 #if (PA_RAMP_TIME == 4)
977 XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */
978 XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */
979 XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */
980 XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */
981 XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */
982 XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */
983 XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */
984 XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */
985 XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */
986 XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */
987 XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */
988 XCVR_TSM->TIMING20 += B1(2); /* (sy_pd_en) */
989 XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */
990 XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */
991 XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */
992 XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */
993 XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */
994 XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */
995 XCVR_TSM->TIMING58 += B1(2) /* (tx_hpm_dac_en) */
996 temp = XCVR_TSM->TIMING14;
997 temp &= 0xFFFF0000;
998 temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */
999 XCVR_TSM->TIMING14 = temp;
1000 #endif /* (PA_RAMP_TIME == 4) */
1001 #endif /* RADIO_IS_GEN_3P0 */
1002 }
1003
1004 #if RADIO_IS_GEN_3P0
1005 if (mode_config->radio_mode == ZIGBEE_MODE)
1006 {
1007 temp = XCVR_TSM->TIMING35;
1008 temp &= ~(B0(0xFF));
1009 if (DATA_PADDING_EN == 1)
1010 {
1011 temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */
1012 }
1013 else
1014 {
1015 temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */
1016 }
1017 XCVR_TSM->TIMING35 = temp;
1018 }
1019 #else
1020
1021 if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS)))
1022 {
1023 /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */
1024 XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */
1025 }
1026 else
1027 {
1028 XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */
1029 }
1030 #endif /* RADIO_IS_GEN_3P0 */
1031
1032 /*******************************************************************************/
1033 /* XCVR_TX_DIG configs */
1034 /*******************************************************************************/
1035 #if RF_OSC_26MHZ == 1
1036 {
1037 XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */
1038 XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz;
1039 XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz;
1040 }
1041 #else
1042 {
1043 XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */
1044 XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz;
1045 XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz;
1046 }
1047 #endif /* RF_OSC_26MHZ == 1 */
1048
1049 if (first_init)
1050 {
1051 XCVR_TX_DIG->CTRL = com_config->tx_ctrl;
1052 XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding;
1053 XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern;
1054
1055 #if !RADIO_IS_GEN_2P1
1056 XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1;
1057 XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2;
1058 #endif /* !RADIO_IS_GEN_2P1 */
1059 }
1060
1061 XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl;
1062
1063 #ifndef SIMULATION
1064 #if (TRIM_BBA_DCOC_DAC_AT_INIT)
1065 if (first_init)
1066 {
1067 uint32_t end_of_rx_wu = 0;
1068 XCVR_ForceRxWu();
1069 /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */
1070 temp = XCVR_TSM->END_OF_SEQ;
1071 end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
1072 while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
1073
1074 // if (!rx_bba_dcoc_dac_trim_shortIQ())
1075 if (!rx_bba_dcoc_dac_trim_DCest())
1076 {
1077 config_status = gXcvrTrimFailure_c;
1078 }
1079
1080 XCVR_ForceRxWd();
1081 DCOC_DAC_INIT_Cal(1);
1082 }
1083 #endif /* TRIM_BBA_DCOC_DAC_AT_INIT */
1084 #endif /* ifndef SIMULATION */
1085 return config_status;
1086 }
1087
XCVR_Reset(void)1088 void XCVR_Reset(void)
1089 {
1090 #if RADIO_IS_GEN_3P0
1091 #else
1092 RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */
1093 RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */
1094 RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */
1095 #endif /* RADIO_IS_GEN_3P0 */
1096 }
1097
XCVR_ChangeMode(radio_mode_t new_radio_mode,data_rate_t new_data_rate)1098 xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */
1099 {
1100 xcvrStatus_t status;
1101 const xcvr_mode_datarate_config_t * mode_datarate_config;
1102 const xcvr_datarate_config_t * datarate_config ;
1103 const xcvr_mode_config_t * radio_mode_cfg;
1104 const xcvr_common_config_t * radio_common_config;
1105
1106 status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config );
1107
1108 if (status == gXcvrSuccess_c)
1109 {
1110 status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config,
1111 (const xcvr_mode_config_t *)radio_mode_cfg,
1112 (const xcvr_mode_datarate_config_t *)mode_datarate_config,
1113 (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE);
1114 current_xcvr_config.radio_mode = new_radio_mode;
1115 current_xcvr_config.data_rate = new_data_rate;
1116 }
1117
1118 return status;
1119 }
1120
XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable)1121 void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable )
1122 {
1123 if (IIRnbEnable)
1124 {
1125 XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK;
1126 }
1127 else
1128 {
1129 XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK;
1130 }
1131 }
1132
XCVR_OverrideFrequency(uint32_t freq,uint32_t refOsc)1133 xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc )
1134 {
1135 double integer_used_in_Hz,
1136 integer_used_in_LSB,
1137 numerator_fraction,
1138 numerator_in_Hz,
1139 numerator_in_LSB,
1140 numerator_unrounded,
1141 real_int_and_fraction,
1142 real_fraction,
1143 requested_freq_in_LSB,
1144 sdm_lsb;
1145 uint32_t temp;
1146 static uint32_t integer_truncated,
1147 integer_to_use;
1148 static int32_t numerator_rounded;
1149
1150 /* Configure for Coarse Tune */
1151 uint32_t coarse_tune_target = freq / 1000000;
1152
1153 temp = XCVR_PLL_DIG->CTUNE_CTRL;
1154 temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK;
1155 temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target);
1156 XCVR_PLL_DIG->CTUNE_CTRL = temp;
1157
1158 /* Calculate the Low Port values */
1159 sdm_lsb = refOsc / 131072.0;
1160
1161 real_int_and_fraction = freq / (refOsc * 2.0);
1162
1163 integer_truncated = (uint32_t) trunc(real_int_and_fraction);
1164
1165 real_fraction = real_int_and_fraction - integer_truncated;
1166
1167 if (real_fraction > 0.5)
1168 {
1169 integer_to_use = integer_truncated + 1;
1170 }
1171 else
1172 {
1173 integer_to_use = integer_truncated;
1174 }
1175
1176 numerator_fraction = real_int_and_fraction - integer_to_use;
1177
1178 integer_used_in_Hz = integer_to_use * refOsc * 2;
1179 integer_used_in_LSB = integer_used_in_Hz / sdm_lsb;
1180
1181 numerator_in_Hz = numerator_fraction * refOsc * 2;
1182 numerator_in_LSB = numerator_in_Hz / sdm_lsb;
1183
1184 requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB;
1185
1186 numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256;
1187
1188 numerator_rounded = (int32_t)round(numerator_unrounded);
1189
1190 /* Write the Low Port Integer and Numerator */
1191 temp = XCVR_PLL_DIG->LPM_SDM_CTRL1;
1192 temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK;
1193 temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) |
1194 XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK);
1195 XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp;
1196
1197 XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded;
1198
1199 return gXcvrSuccess_c;
1200 }
1201
XCVR_RegisterPanicCb(panic_fptr fptr)1202 void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */
1203 {
1204 s_PanicFunctionPtr = fptr;
1205 }
1206
XcvrPanic(XCVR_PANIC_ID_T panic_id,uint32_t panic_address)1207 void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address)
1208 {
1209 if ( s_PanicFunctionPtr != NULL)
1210 {
1211 s_PanicFunctionPtr(panic_id, panic_address, 0, 0);
1212 }
1213 else
1214 {
1215 uint8_t dummy;
1216
1217 while(1)
1218 {
1219 dummy = dummy;
1220 }
1221 }
1222 }
1223
XCVR_HealthCheck(void)1224 healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */
1225 {
1226 return (healthStatus_t)NO_ERRORS;
1227 }
1228
XCVR_FadLppsControl(FAD_LPPS_CTRL_T control)1229 void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control)
1230 {
1231
1232 }
1233
1234 /* Helper function to map radio mode to LL usage */
map_mode_to_ll(radio_mode_t mode)1235 link_layer_t map_mode_to_ll(radio_mode_t mode)
1236 {
1237 link_layer_t llret;
1238 switch (mode)
1239 {
1240 case BLE_MODE:
1241 llret = BLE_LL;
1242 break;
1243 case ZIGBEE_MODE:
1244 llret = ZIGBEE_LL;
1245 break;
1246 case ANT_MODE:
1247 llret = ANT_LL;
1248 break;
1249 case GFSK_BT_0p5_h_0p5:
1250 case GFSK_BT_0p5_h_0p32:
1251 case GFSK_BT_0p5_h_0p7:
1252 case GFSK_BT_0p5_h_1p0:
1253 case GFSK_BT_0p3_h_0p5:
1254 case GFSK_BT_0p7_h_0p5:
1255 case MSK:
1256 llret = GENFSK_LL;
1257 break;
1258 default:
1259 llret = UNASSIGNED_LL;
1260 break;
1261 }
1262 return llret;
1263 }
1264
1265 #if RADIO_IS_GEN_3P0
XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address)1266 void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address)
1267 {
1268 XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address;
1269 }
1270
XCVR_GetBSM_NTW_Address(void)1271 uint32_t XCVR_GetBSM_NTW_Address(void)
1272 {
1273 return XCVR_PHY->NTW_ADR_BSM;
1274 }
1275 #endif /* RADIO_IS_GEN_3P0 */
1276
1277 /* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */
XCVR_SetIRQMapping(radio_mode_t irq0_mapping,radio_mode_t irq1_mapping)1278 xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping)
1279 {
1280 link_layer_t int0 = map_mode_to_ll(irq0_mapping);
1281 link_layer_t int1 = map_mode_to_ll(irq1_mapping);
1282 xcvrStatus_t statusret;
1283 /* Make sure the two LL's requested aren't the same */
1284 if (int0 == int1)
1285 {
1286 statusret = gXcvrInvalidParameters_c;
1287 }
1288 else
1289 {
1290 uint32_t temp;
1291 temp = XCVR_MISC->XCVR_CTRL;
1292 temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK);
1293 temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1));
1294 XCVR_MISC->XCVR_CTRL = temp;
1295 statusret = gXcvrSuccess_c;
1296 }
1297 return statusret;
1298 }
1299
1300 /* Get current state of IRQ mapping for either radio INT0 or INT1 */
XCVR_GetIRQMapping(uint8_t int_num)1301 link_layer_t XCVR_GetIRQMapping(uint8_t int_num)
1302 {
1303 if (int_num == 0)
1304 {
1305 return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT);
1306 }
1307 else
1308 {
1309 return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT);
1310 }
1311 }
1312
1313 /* Get current state of radio mode and data rate */
XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config)1314 xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config)
1315 {
1316 xcvrStatus_t status = gXcvrInvalidParameters_c;
1317 if (curr_config != NULL)
1318 {
1319 curr_config->radio_mode = current_xcvr_config.radio_mode;
1320 curr_config->data_rate = current_xcvr_config.data_rate;
1321 status = gXcvrSuccess_c;
1322 }
1323 return status;
1324 }
1325
1326 /* Customer level trim functions */
XCVR_SetXtalTrim(uint8_t xtalTrim)1327 xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim)
1328 {
1329 xcvrStatus_t status = gXcvrInvalidParameters_c;
1330
1331 if ((xtalTrim & 0x80) == 0)
1332 {
1333 uint32_t temp;
1334 temp = RSIM->ANA_TRIM;
1335 temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK;
1336 RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim);
1337 status = gXcvrSuccess_c;
1338 }
1339 return status;
1340 }
1341
XCVR_GetXtalTrim(void)1342 uint8_t XCVR_GetXtalTrim(void)
1343 {
1344 uint8_t temp_xtal;
1345 temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT);
1346 return temp_xtal;
1347 }
1348
1349 /* RSSI adjustment */
XCVR_SetRssiAdjustment(int8_t adj)1350 xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj)
1351 {
1352 XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK;
1353 XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj);
1354 return gXcvrSuccess_c;
1355 }
1356
XCVR_GetRssiAdjustment(void)1357 int8_t XCVR_GetRssiAdjustment(void)
1358 {
1359 int8_t adj;
1360 adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT;
1361 return adj;
1362 }
1363
1364 /* Radio debug functions */
XCVR_OverrideChannel(uint8_t channel,uint8_t useMappedChannel)1365 xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel)
1366 {
1367 uint32_t temp;
1368
1369 if (channel == 0xFF)
1370 {
1371 /* Clear all of the overrides and restore to LL channel control */
1372 temp = XCVR_PLL_DIG->CHAN_MAP;
1373 temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
1374 #if !RADIO_IS_GEN_2P1
1375 | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
1376 #endif /* !RADIO_IS_GEN_2P1 */
1377 #if RADIO_IS_GEN_3P0
1378 | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK
1379 #endif /* RADIO_IS_GEN_3P0 */
1380 );
1381
1382 XCVR_PLL_DIG->CHAN_MAP = temp;
1383
1384 /* Stop using the manual frequency setting */
1385 XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK;
1386
1387 return gXcvrSuccess_c;
1388 }
1389
1390 if (channel >= 128)
1391 {
1392 return gXcvrInvalidParameters_c;
1393 }
1394
1395 if (useMappedChannel)
1396 {
1397 temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */
1398
1399 switch (temp)
1400 {
1401 #if !RADIO_IS_GEN_2P1
1402 case 0x3: /* ANT protocol */
1403 ANT->CHANNEL_NUM = channel;
1404 break;
1405 #endif /* !RADIO_IS_GEN_2P1 */
1406 case 0x8: /* GENFSK protocol */
1407 case 0x9: /* MSK protocol */
1408 GENFSK->CHANNEL_NUM = channel;
1409 break;
1410 default: /* All other protocols */
1411 temp = XCVR_PLL_DIG->CHAN_MAP;
1412 temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK
1413 #if RADIO_IS_GEN_3P0
1414 | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK
1415 #endif /* RADIO_IS_GEN_3P0 */
1416 );
1417 temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
1418 #if !RADIO_IS_GEN_2P1
1419 | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
1420 #endif /* !RADIO_IS_GEN_2P1 */
1421 );
1422 XCVR_PLL_DIG->CHAN_MAP = temp;
1423 break;
1424 }
1425 }
1426 else
1427 {
1428 XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
1429 #if !RADIO_IS_GEN_2P1
1430 | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
1431 #endif /* !RADIO_IS_GEN_2P1 */
1432 );
1433
1434 XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c);
1435 XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator);
1436
1437 temp = XCVR_PLL_DIG->LPM_SDM_CTRL1;
1438 temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK;
1439 temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer);
1440 XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp;
1441
1442 /* Stop using the LL channel map and use the manual frequency setting */
1443 XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK;
1444 }
1445
1446 return gXcvrSuccess_c;
1447 }
1448
XCVR_GetFreq(void)1449 uint32_t XCVR_GetFreq ( void )
1450 {
1451 uint32_t pll_int;
1452 uint32_t pll_num_unsigned;
1453 int32_t pll_num;
1454 uint32_t pll_denom;
1455 float freq_float;
1456
1457 if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */
1458 {
1459 pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >>
1460 XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT;
1461
1462 pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2;
1463 pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3;
1464 }
1465 else
1466 {
1467 /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */
1468 pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >>
1469 XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT;
1470
1471 pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1;
1472 pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2;
1473 }
1474
1475 uint32_t freq = 0;
1476
1477 #if RF_OSC_26MHZ == 1
1478 uint32_t ref_clk = 26U;
1479 #else
1480 uint32_t ref_clk = 32U;
1481 #endif /* RF_OSC_26MHZ == 1 */
1482
1483 /* Check if sign bit is asserted */
1484 if (pll_num_unsigned & 0x04000000U)
1485 {
1486 /* Sign extend the numerator */
1487 pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU;
1488
1489 /* Calculate the frequency in MHz */
1490 freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom)));
1491 }
1492 else
1493 {
1494 /* Calculate the frequency in MHz */
1495 pll_num = pll_num_unsigned;
1496 freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom)));
1497 }
1498
1499 freq = (uint32_t)freq_float;
1500
1501 return freq;
1502 }
1503
XCVR_ForceRxWu(void)1504 void XCVR_ForceRxWu(void)
1505 {
1506 XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK;
1507 }
1508
XCVR_ForceRxWd(void)1509 void XCVR_ForceRxWd(void)
1510 {
1511 XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK;
1512 }
1513
XCVR_ForceTxWu(void)1514 void XCVR_ForceTxWu(void)
1515 {
1516 XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
1517 }
1518
XCVR_ForceTxWd(void)1519 void XCVR_ForceTxWd(void)
1520 {
1521 XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
1522 }
1523
XCVR_DftTxCW(uint16_t rf_channel_freq,uint8_t protocol)1524 xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol)
1525 {
1526 uint32_t temp;
1527 if ((protocol != 6) && (protocol != 7))
1528 {
1529 return gXcvrInvalidParameters_c; /* Failure */
1530 }
1531
1532 if ((rf_channel_freq < 2360) || (rf_channel_freq >2487))
1533 {
1534 return gXcvrInvalidParameters_c; /* failure */
1535 }
1536
1537 /* Set the DFT Mode */
1538 temp = XCVR_TX_DIG->CTRL;
1539 temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK;
1540 temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1);
1541 XCVR_TX_DIG->CTRL = temp;
1542
1543 /* Choose Protocol 6 or 7 if using the Channel Number register */
1544 temp = XCVR_MISC->XCVR_CTRL;
1545 temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK;
1546 temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol);
1547 XCVR_MISC->XCVR_CTRL = temp;
1548
1549 /* Select the RF Channel, using the Channel Number register */
1550 XCVR_OverrideChannel(rf_channel_freq-2360,1);
1551
1552 /* Warm-up the Radio */
1553 XCVR_ForceTxWu();
1554
1555 return gXcvrSuccess_c; /* Success */
1556 }
1557
XCVR_DftTxPatternReg(uint16_t channel_num,radio_mode_t radio_mode,data_rate_t data_rate,uint32_t tx_pattern)1558 xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern)
1559 {
1560 uint32_t temp;
1561 uint8_t dft_mode = 0;
1562 uint8_t dft_clk_sel = 0;
1563 xcvrStatus_t status = gXcvrSuccess_c;
1564
1565 XCVR_ChangeMode(radio_mode, data_rate);
1566
1567 /* Select the RF Channel, using the Channel Number register */
1568 XCVR_OverrideChannel(channel_num, 1);
1569
1570 switch (radio_mode)
1571 {
1572 case ZIGBEE_MODE:
1573 dft_mode = 6; /* OQPSK configuration */
1574 break;
1575 case ANT_MODE:
1576 case BLE_MODE:
1577 case GFSK_BT_0p5_h_0p5:
1578 case GFSK_BT_0p5_h_0p32:
1579 case GFSK_BT_0p5_h_0p7:
1580 case GFSK_BT_0p5_h_1p0:
1581 case GFSK_BT_0p3_h_0p5:
1582 case GFSK_BT_0p7_h_0p5:
1583 dft_mode = 2; /* GFSK configuration */
1584 break;
1585 case MSK:
1586 dft_mode = 4; /* MSK configuration */
1587 break;
1588 default:
1589 status = gXcvrInvalidParameters_c;
1590 break;
1591 }
1592
1593 if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */
1594 {
1595 switch (data_rate)
1596 {
1597 case DR_1MBPS:
1598 dft_clk_sel = 4;
1599 break;
1600 case DR_500KBPS:
1601 dft_clk_sel = 3;
1602 break;
1603 case DR_250KBPS:
1604 dft_clk_sel = 2;
1605 break;
1606 default:
1607 status = gXcvrInvalidParameters_c;
1608 break;
1609 }
1610 }
1611
1612 temp = XCVR_TX_DIG->CTRL;
1613 temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK);
1614 temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) |
1615 XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
1616 XCVR_TX_DIG_CTRL_TX_DFT_EN(1) |
1617 XCVR_TX_DIG_CTRL_LFSR_EN(0);
1618 XCVR_TX_DIG->CTRL = temp;
1619
1620 XCVR_TX_DIG->DFT_PATTERN = tx_pattern;
1621
1622 if (status == gXcvrSuccess_c)
1623 {
1624 /* Warm-up the Radio */
1625 XCVR_ForceTxWu();
1626 }
1627
1628 return status;
1629 }
1630
XCVR_DftTxLfsrReg(uint16_t channel_num,radio_mode_t radio_mode,data_rate_t data_rate,uint8_t lfsr_length)1631 xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length)
1632 {
1633 uint32_t temp;
1634 uint8_t dft_mode = 0;
1635 uint8_t dft_clk_sel = 0;
1636 xcvrStatus_t status = gXcvrSuccess_c;
1637 uint8_t bitrate_setting = 0xFF;
1638
1639 if (lfsr_length > 5)
1640 {
1641 return gXcvrInvalidParameters_c;
1642 }
1643
1644 XCVR_ChangeMode(radio_mode, data_rate);
1645
1646 /* Select the RF Channel, using the Channel Number register */
1647 XCVR_OverrideChannel(channel_num, 1);
1648
1649 switch (radio_mode)
1650 {
1651 case ZIGBEE_MODE:
1652 dft_mode = 7; /* OQPSK configuration */
1653 break;
1654 case ANT_MODE:
1655 case BLE_MODE:
1656 case GFSK_BT_0p5_h_0p5:
1657 case GFSK_BT_0p5_h_0p32:
1658 case GFSK_BT_0p5_h_0p7:
1659 case GFSK_BT_0p5_h_1p0:
1660 case GFSK_BT_0p3_h_0p5:
1661 case GFSK_BT_0p7_h_0p5:
1662 dft_mode = 3; /* GFSK configuration */
1663 bitrate_setting = data_rate;
1664 break;
1665 case MSK:
1666 dft_mode = 5; /* MSK configuration */
1667 break;
1668
1669 default:
1670 status = gXcvrInvalidParameters_c;
1671 break;
1672 }
1673
1674 if (status == gXcvrSuccess_c)
1675 {
1676 switch (data_rate)
1677 {
1678 case DR_1MBPS:
1679 dft_clk_sel = 4;
1680 break;
1681 case DR_500KBPS:
1682 dft_clk_sel = 3;
1683 break;
1684 case DR_250KBPS:
1685 dft_clk_sel = 2;
1686 break;
1687 default:
1688 status = gXcvrInvalidParameters_c;
1689 break;
1690 }
1691 }
1692
1693 if (bitrate_setting < 4)
1694 {
1695 GENFSK->BITRATE = bitrate_setting;
1696 }
1697
1698 temp = XCVR_TX_DIG->CTRL;
1699 temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK |
1700 XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK |
1701 XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK |
1702 XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK |
1703 XCVR_TX_DIG_CTRL_LFSR_EN_MASK);
1704 temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) |
1705 XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) |
1706 XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
1707 XCVR_TX_DIG_CTRL_TX_DFT_EN(0) |
1708 XCVR_TX_DIG_CTRL_LFSR_EN(1);
1709 XCVR_TX_DIG->CTRL = temp;
1710
1711 if (status == gXcvrSuccess_c)
1712 {
1713 /* Warm-up the Radio */
1714 XCVR_ForceTxWu();
1715 }
1716
1717 return status;
1718 }
1719
XCVR_DftTxOff(void)1720 void XCVR_DftTxOff(void)
1721 {
1722 XCVR_ForceTxWd();
1723 XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */
1724 /* Clear the RF Channel over-ride */
1725 XCVR_OverrideChannel(0xFF,1);
1726 XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */
1727 XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */
1728 XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */
1729 XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */
1730 }
1731
XCVR_ForcePAPower(uint8_t pa_power)1732 xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power)
1733 {
1734 if (pa_power > 0x3F)
1735 {
1736 return gXcvrInvalidParameters_c; /* Failure */
1737 }
1738
1739 if (pa_power != 1)
1740 {
1741 pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */
1742 }
1743
1744 XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */
1745 XCVR_TSM->PA_POWER = pa_power;
1746
1747 return gXcvrSuccess_c; /* Success */
1748 }
1749
XCVR_CoexistenceInit(void)1750 xcvrStatus_t XCVR_CoexistenceInit(void)
1751 {
1752 #if gMWS_UseCoexistence_d
1753 uint32_t temp = 0x00U;
1754 uint32_t end_of_tx_wu = 0x00U;
1755 uint32_t end_of_rx_wu = 0x00U;
1756
1757 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
1758 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
1759 uint32_t tsm_timing47 = 0x00U;
1760 #else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */
1761 uint32_t tsm_timing48 = 0x00U;
1762 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
1763 uint32_t tsm_timing50 = 0x00U;
1764 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
1765
1766 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
1767 // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en)
1768 uint32_t tsm_timing48 = 0x00U;
1769 // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en)
1770 uint32_t tsm_timing47 = 0x00U;
1771 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
1772
1773 uint16_t tsm_timing43_rx = 0x00;
1774 uint16_t tsm_timing43_tx = 0x00;
1775
1776 /* Select GPIO mode for FAD pins */
1777 temp = XCVR_MISC->FAD_CTRL;
1778 temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK);
1779 XCVR_MISC->FAD_CTRL = temp;
1780
1781 /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */
1782 end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
1783 XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
1784 end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >>
1785 XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
1786
1787 /*****************
1788 * TX SEQUENCE *
1789 *****************/
1790
1791 if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d)
1792 {
1793 temp = end_of_tx_wu;
1794 }
1795 else
1796 {
1797 temp = gMWS_CoexRfActiveAssertTime_d;
1798 }
1799
1800 /* Save the TX RF_ACTIVE start time. */
1801 tsm_timing43_tx = end_of_tx_wu - temp;
1802
1803 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
1804 /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
1805 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
1806 tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
1807 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
1808 #else
1809 tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) &
1810 XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK);
1811 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
1812
1813 /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
1814 tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) &
1815 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
1816 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
1817
1818 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
1819 /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
1820 tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) &
1821 XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK);
1822
1823 /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
1824 tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
1825 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
1826 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
1827
1828 /*****************
1829 * RX SEQUENCE *
1830 *****************/
1831
1832 if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d)
1833 {
1834 temp = end_of_rx_wu;
1835 }
1836 else
1837 {
1838 temp = gMWS_CoexRfActiveAssertTime_d;
1839 }
1840
1841 /* Save the RX RF_ACTIVE start time. */
1842 tsm_timing43_rx = end_of_rx_wu - temp;
1843
1844 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
1845 /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */
1846 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
1847 tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
1848 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
1849 #else
1850 tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) &
1851 XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
1852 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
1853
1854 /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */
1855 tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) &
1856 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
1857 (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) &
1858 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
1859
1860 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
1861 temp = XCVR_TSM->TIMING47;
1862 temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
1863 temp |= tsm_timing47;
1864 XCVR_TSM->TIMING47 = temp;
1865 #else
1866 temp = XCVR_TSM->TIMING48;
1867 temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
1868 temp |= tsm_timing48;
1869 XCVR_TSM->TIMING48 = temp;
1870 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
1871
1872 temp = XCVR_TSM->TIMING50;
1873 temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK |
1874 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK |
1875 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK);
1876 temp |= tsm_timing50;
1877 XCVR_TSM->TIMING50 = temp;
1878
1879 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
1880 GPIOC->PDDR |= 0x18;
1881 PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
1882 PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
1883 #else
1884 GPIOC->PDDR |= 0x0A;
1885 PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
1886 PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
1887 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
1888 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
1889
1890 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
1891 /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */
1892 tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) &
1893 XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
1894
1895 /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */
1896 tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
1897 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
1898
1899 /* RF_ACTIVE */
1900 temp = XCVR_TSM->TIMING48;
1901 temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
1902 temp |= tsm_timing48;
1903 XCVR_TSM->TIMING48 = temp;
1904
1905 /* RF_PRIORITY */
1906 temp = XCVR_TSM->TIMING47;
1907 temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
1908 temp |= tsm_timing47;
1909 XCVR_TSM->TIMING47 = temp;
1910
1911 /* Overwrite pins settings */
1912 GPIOC->PDDR |= 0x12;
1913 PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
1914 PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
1915 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
1916
1917 tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d;
1918
1919 if (tsm_timing43_tx > end_of_tx_wu - 1)
1920 {
1921 tsm_timing43_tx = end_of_tx_wu - 1;
1922 }
1923
1924 tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d;
1925
1926 if (tsm_timing43_rx > end_of_rx_wu - 1)
1927 {
1928 tsm_timing43_rx = end_of_rx_wu - 1;
1929 }
1930
1931 XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) |
1932 (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) |
1933 (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) |
1934 (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK));
1935
1936 BTLE_RF->MISC_CTRL = 0x02;
1937
1938 XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK;
1939
1940 /* Save the updated registers values. */
1941 XCVR_CoexistenceSaveRestoreTimings(1);
1942 #endif /* gMWS_UseCoexistence_d */
1943
1944 return gXcvrSuccess_c;
1945 }
1946
XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority,XCVR_COEX_PRIORITY_T txPriority)1947 xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority)
1948 {
1949 #if gMWS_UseCoexistence_d
1950 uint32_t temp = 0x00U;
1951 uint32_t end_of_tx_wu = 0x00U;
1952 uint32_t end_of_rx_wu = 0x00U;
1953 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
1954 uint32_t tsm_timing50 = 0x00U;
1955 #endif
1956 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
1957 uint32_t tsm_timing47 = 0x00U;
1958 #endif
1959
1960 /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */
1961 end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
1962 XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
1963 end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >>
1964 XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
1965
1966 /*****************
1967 * RX *
1968 *****************/
1969
1970 if (XCVR_COEX_HIGH_PRIO == rxPriority)
1971 {
1972 if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d)
1973 {
1974 temp = end_of_rx_wu;
1975 }
1976 else
1977 {
1978 temp = gMWS_CoexRfActiveAssertTime_d;
1979 }
1980
1981 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
1982 /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */
1983 tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) &
1984 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
1985 (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) &
1986 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
1987 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
1988 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
1989 /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */
1990 tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
1991 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
1992 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
1993 }
1994 else
1995 {
1996 /* Low priority RX */
1997 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
1998 tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) &
1999 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
2000 ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) &
2001 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
2002 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
2003 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
2004 tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
2005 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) |
2006 ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) &
2007 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK));
2008 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
2009 }
2010
2011 /*****************
2012 * TX *
2013 *****************/
2014 if (XCVR_COEX_HIGH_PRIO == txPriority)
2015 {
2016 if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d)
2017 {
2018 temp = end_of_tx_wu;
2019 }
2020 else
2021 {
2022 temp = gMWS_CoexRfActiveAssertTime_d;
2023 }
2024
2025 /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */
2026 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
2027 tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) &
2028 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
2029 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
2030 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
2031 tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
2032 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
2033 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
2034 }
2035 else
2036 {
2037 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
2038 /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */
2039 tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) &
2040 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
2041 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
2042 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
2043 /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */
2044 tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
2045 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) |
2046 ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) &
2047 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK));
2048 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
2049 }
2050
2051 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
2052 temp = XCVR_TSM->TIMING50;
2053 temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK |
2054 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK |
2055 XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK);
2056 temp |= tsm_timing50;
2057 XCVR_TSM->TIMING50 = temp;
2058 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
2059 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
2060 temp = XCVR_TSM->TIMING47;
2061 temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK |
2062 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK |
2063 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK |
2064 XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK);
2065 temp |= tsm_timing47;
2066 XCVR_TSM->TIMING47 = temp;
2067 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
2068
2069 /* Save the updated registers values. */
2070 XCVR_CoexistenceSaveRestoreTimings(1);
2071 #endif /* gMWS_UseCoexistence_d */
2072
2073 return gXcvrSuccess_c;
2074 }
2075
XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings)2076 xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings)
2077 {
2078 #if gMWS_UseCoexistence_d
2079 static uint32_t tsm_ovrd0_saved = 0x00;
2080 static uint32_t tsm_ovrd1_saved = 0x00;
2081 static uint32_t tsm_ovrd2_saved = 0x00;
2082 static uint32_t tsm_ovrd3_saved = 0x00;
2083 static uint32_t tsm_timing47_saved = 0x00;
2084 static uint32_t tsm_timing48_saved = 0x00;
2085 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
2086 static uint32_t tsm_timing49_saved = 0x00;
2087 static uint32_t tsm_timing50_saved = 0x00;
2088 #endif
2089
2090 if (saveTimings == 0)
2091 {
2092 /* Restore registers values. */
2093 XCVR_TSM->OVRD0 = tsm_ovrd0_saved;
2094 XCVR_TSM->OVRD1 = tsm_ovrd1_saved;
2095 XCVR_TSM->OVRD2 = tsm_ovrd2_saved;
2096 XCVR_TSM->OVRD3 = tsm_ovrd3_saved;
2097
2098 XCVR_TSM->TIMING47 = tsm_timing47_saved;
2099 XCVR_TSM->TIMING48 = tsm_timing48_saved;
2100 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
2101 XCVR_TSM->TIMING49 = tsm_timing49_saved;
2102 XCVR_TSM->TIMING50 = tsm_timing50_saved;
2103 #endif
2104 }
2105 else
2106 {
2107 /* Save registers values. */
2108 tsm_ovrd0_saved = XCVR_TSM->OVRD0;
2109 tsm_ovrd1_saved = XCVR_TSM->OVRD1;
2110 tsm_ovrd2_saved = XCVR_TSM->OVRD2;
2111 tsm_ovrd3_saved = XCVR_TSM->OVRD3;
2112 tsm_timing47_saved = XCVR_TSM->TIMING47;
2113 tsm_timing48_saved = XCVR_TSM->TIMING48;
2114 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
2115 tsm_timing49_saved = XCVR_TSM->TIMING49;
2116 tsm_timing50_saved = XCVR_TSM->TIMING50;
2117 #endif
2118 }
2119 #endif /* gMWS_UseCoexistence_d */
2120
2121 return gXcvrSuccess_c;
2122 }
2123
2124
