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Searched defs:XCHAL_TIMER2_INTERRUPT (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h327 #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h427 #define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h427 #define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h427 #define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h450 #define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h438 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h448 #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h438 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h526 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h464 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h528 #define XCHAL_TIMER2_INTERRUPT 18 /* CCOMPARE2 */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h573 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h587 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro