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Searched defs:XCHAL_TIMER0_INTERRUPT (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h325 #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h425 #define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h425 #define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h425 #define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h436 #define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h448 #define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h446 #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h436 #define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h524 #define XCHAL_TIMER0_INTERRUPT 3 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dcore-isa.h462 #define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h526 #define XCHAL_TIMER0_INTERRUPT 16 /* CCOMPARE0 */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h585 #define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */ macro