Home
last modified time | relevance | path

Searched defs:XCHAL_NUM_WRITEBUFFER_ENTRIES (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h114 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h192 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h192 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h192 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h192 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h185 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h165 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h165 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h227 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h220 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h225 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ macro