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Searched defs:XCHAL_MPU_ALIGN_REQ (Results 1 – 10 of 10) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h597 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h597 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h597 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h620 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h633 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h691 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h662 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h714 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h786 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h801 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ macro