1 /* 2 * xtensa/config/core.h -- HAL definitions dependent on CORE configuration 3 * 4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL. 5 * It pulls definitions tailored for a specific Xtensa processor configuration. 6 * 7 * Sources for binaries meant to be configuration-independent generally avoid 8 * including this file (they may use the configuration-specific HAL library). 9 * It is normal for the HAL library source itself to include this file. 10 */ 11 12 /* 13 * Copyright (c) 2005-2015 Cadence Design Systems, Inc. 14 * 15 * Permission is hereby granted, free of charge, to any person obtaining 16 * a copy of this software and associated documentation files (the 17 * "Software"), to deal in the Software without restriction, including 18 * without limitation the rights to use, copy, modify, merge, publish, 19 * distribute, sublicense, and/or sell copies of the Software, and to 20 * permit persons to whom the Software is furnished to do so, subject to 21 * the following conditions: 22 * 23 * The above copyright notice and this permission notice shall be included 24 * in all copies or substantial portions of the Software. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 29 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 30 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 31 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 32 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 33 */ 34 35 36 #ifndef XTENSA_CONFIG_CORE_H 37 #define XTENSA_CONFIG_CORE_H 38 39 /* CONFIGURATION INDEPENDENT DEFINITIONS: */ 40 #ifdef __XTENSA__ 41 #include <xtensa/hal.h> 42 #include <xtensa/xtensa-versions.h> 43 #else 44 #include "../hal.h" 45 #include "../xtensa-versions.h" 46 #endif 47 48 /* CONFIGURATION SPECIFIC DEFINITIONS: */ 49 #ifdef __XTENSA__ 50 #include <xtensa/config/core-isa.h> 51 #include <xtensa/config/core-matmap.h> 52 #include <xtensa/config/tie.h> 53 #else 54 #include "core-isa.h" 55 #include "core-matmap.h" 56 #include "tie.h" 57 #endif 58 59 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) 60 #ifdef __XTENSA__ 61 #include <xtensa/config/tie-asm.h> 62 #else 63 #include "tie-asm.h" 64 #endif 65 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ 66 67 68 /*---------------------------------------------------------------------- 69 GENERAL 70 ----------------------------------------------------------------------*/ 71 72 /* 73 * Separators for macros that expand into arrays. 74 * These can be predefined by files that #include this one, 75 * when different separators are required. 76 */ 77 /* Element separator for macros that expand into 1-dimensional arrays: */ 78 #ifndef XCHAL_SEP 79 #define XCHAL_SEP , 80 #endif 81 /* Array separator for macros that expand into 2-dimensional arrays: */ 82 #ifndef XCHAL_SEP2 83 #define XCHAL_SEP2 },{ 84 #endif 85 86 87 /*---------------------------------------------------------------------- 88 ERRATA 89 ----------------------------------------------------------------------*/ 90 91 /* 92 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; 93 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): 94 */ 95 #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ 96 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \ 97 || XCHAL_HW_RELEASE_AT(1050,0))) 98 /* 99 * Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1. 100 * Applies to specific set of configuration options. 101 * Part of the workaround is to add ISYNC at certain points in the code. 102 * The workaround gated by this macro can be disabled if not needed, e.g. if 103 * zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453. 104 */ 105 #if ( XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \ 106 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \ 107 XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \ 108 XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 && \ 109 XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) ) 110 #define XCHAL_ERRATUM_453 1 111 #else 112 #define XCHAL_ERRATUM_453 0 113 #endif 114 115 /* 116 * Erratum 497 present in RE-2012.2 up to RG/RF-2015.2 117 * Applies to specific set of configuration options. 118 * Workaround is to add MEMWs after at most 8 cache WB instructions 119 */ 120 #if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 && \ 121 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \ 122 (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 && \ 123 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2) \ 124 ) && \ 125 XCHAL_DCACHE_IS_WRITEBACK && \ 126 XCHAL_HAVE_AXI && \ 127 XCHAL_HAVE_PIF_WR_RESP && \ 128 XCHAL_HAVE_PIF_REQ_ATTR && !defined(_NO_ERRATUM_497) \ 129 ) 130 #define XCHAL_ERRATUM_497 1 131 #else 132 #define XCHAL_ERRATUM_497 0 133 #endif 134 135 136 /*---------------------------------------------------------------------- 137 ISA 138 ----------------------------------------------------------------------*/ 139 140 #if XCHAL_HAVE_BE 141 # define XCHAL_HAVE_LE 0 142 # define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN 143 #else 144 # define XCHAL_HAVE_LE 1 145 # define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN 146 #endif 147 148 149 150 /*---------------------------------------------------------------------- 151 INTERRUPTS 152 ----------------------------------------------------------------------*/ 153 154 /* Indexing macros: */ 155 #define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK 156 #define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ 157 #define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK 158 #define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ 159 #define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM 160 #define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ 161 #define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL 162 #define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ 163 #define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE 164 #define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ 165 #define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT 166 #define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ 167 168 169 #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS 170 #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */ 171 #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */ 172 /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ 173 174 /* These values are constant for existing Xtensa processor implementations: */ 175 #define XCHAL_INTLEVEL0_MASK 0x00000000 176 #define XCHAL_INTLEVEL8_MASK 0x00000000 177 #define XCHAL_INTLEVEL9_MASK 0x00000000 178 #define XCHAL_INTLEVEL10_MASK 0x00000000 179 #define XCHAL_INTLEVEL11_MASK 0x00000000 180 #define XCHAL_INTLEVEL12_MASK 0x00000000 181 #define XCHAL_INTLEVEL13_MASK 0x00000000 182 #define XCHAL_INTLEVEL14_MASK 0x00000000 183 #define XCHAL_INTLEVEL15_MASK 0x00000000 184 185 /* Array of masks of interrupts at each interrupt level: */ 186 #define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ 187 XCHAL_SEP XCHAL_INTLEVEL1_MASK \ 188 XCHAL_SEP XCHAL_INTLEVEL2_MASK \ 189 XCHAL_SEP XCHAL_INTLEVEL3_MASK \ 190 XCHAL_SEP XCHAL_INTLEVEL4_MASK \ 191 XCHAL_SEP XCHAL_INTLEVEL5_MASK \ 192 XCHAL_SEP XCHAL_INTLEVEL6_MASK \ 193 XCHAL_SEP XCHAL_INTLEVEL7_MASK \ 194 XCHAL_SEP XCHAL_INTLEVEL8_MASK \ 195 XCHAL_SEP XCHAL_INTLEVEL9_MASK \ 196 XCHAL_SEP XCHAL_INTLEVEL10_MASK \ 197 XCHAL_SEP XCHAL_INTLEVEL11_MASK \ 198 XCHAL_SEP XCHAL_INTLEVEL12_MASK \ 199 XCHAL_SEP XCHAL_INTLEVEL13_MASK \ 200 XCHAL_SEP XCHAL_INTLEVEL14_MASK \ 201 XCHAL_SEP XCHAL_INTLEVEL15_MASK 202 203 /* These values are constant for existing Xtensa processor implementations: */ 204 #define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 205 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 206 #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 207 #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 208 #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 209 #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 210 #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 211 #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 212 #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 213 214 /* Mask of all low-priority interrupts: */ 215 #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK 216 217 /* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ 218 #define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) 219 220 /* Array of masks of interrupts at each range 1..n of interrupt levels: */ 221 #define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ 222 XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ 223 XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ 224 XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ 225 XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ 226 XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ 227 XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ 228 XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ 229 XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ 230 XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ 231 XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ 232 XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ 233 XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ 234 XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ 235 XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ 236 XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK 237 238 #if 0 /*XCHAL_HAVE_NMI*/ 239 /* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ 240 # define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) 241 #endif 242 243 /* Array of levels of each possible interrupt: */ 244 #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ 245 XCHAL_SEP XCHAL_INT1_LEVEL \ 246 XCHAL_SEP XCHAL_INT2_LEVEL \ 247 XCHAL_SEP XCHAL_INT3_LEVEL \ 248 XCHAL_SEP XCHAL_INT4_LEVEL \ 249 XCHAL_SEP XCHAL_INT5_LEVEL \ 250 XCHAL_SEP XCHAL_INT6_LEVEL \ 251 XCHAL_SEP XCHAL_INT7_LEVEL \ 252 XCHAL_SEP XCHAL_INT8_LEVEL \ 253 XCHAL_SEP XCHAL_INT9_LEVEL \ 254 XCHAL_SEP XCHAL_INT10_LEVEL \ 255 XCHAL_SEP XCHAL_INT11_LEVEL \ 256 XCHAL_SEP XCHAL_INT12_LEVEL \ 257 XCHAL_SEP XCHAL_INT13_LEVEL \ 258 XCHAL_SEP XCHAL_INT14_LEVEL \ 259 XCHAL_SEP XCHAL_INT15_LEVEL \ 260 XCHAL_SEP XCHAL_INT16_LEVEL \ 261 XCHAL_SEP XCHAL_INT17_LEVEL \ 262 XCHAL_SEP XCHAL_INT18_LEVEL \ 263 XCHAL_SEP XCHAL_INT19_LEVEL \ 264 XCHAL_SEP XCHAL_INT20_LEVEL \ 265 XCHAL_SEP XCHAL_INT21_LEVEL \ 266 XCHAL_SEP XCHAL_INT22_LEVEL \ 267 XCHAL_SEP XCHAL_INT23_LEVEL \ 268 XCHAL_SEP XCHAL_INT24_LEVEL \ 269 XCHAL_SEP XCHAL_INT25_LEVEL \ 270 XCHAL_SEP XCHAL_INT26_LEVEL \ 271 XCHAL_SEP XCHAL_INT27_LEVEL \ 272 XCHAL_SEP XCHAL_INT28_LEVEL \ 273 XCHAL_SEP XCHAL_INT29_LEVEL \ 274 XCHAL_SEP XCHAL_INT30_LEVEL \ 275 XCHAL_SEP XCHAL_INT31_LEVEL 276 277 /* Array of types of each possible interrupt: */ 278 #define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ 279 XCHAL_SEP XCHAL_INT1_TYPE \ 280 XCHAL_SEP XCHAL_INT2_TYPE \ 281 XCHAL_SEP XCHAL_INT3_TYPE \ 282 XCHAL_SEP XCHAL_INT4_TYPE \ 283 XCHAL_SEP XCHAL_INT5_TYPE \ 284 XCHAL_SEP XCHAL_INT6_TYPE \ 285 XCHAL_SEP XCHAL_INT7_TYPE \ 286 XCHAL_SEP XCHAL_INT8_TYPE \ 287 XCHAL_SEP XCHAL_INT9_TYPE \ 288 XCHAL_SEP XCHAL_INT10_TYPE \ 289 XCHAL_SEP XCHAL_INT11_TYPE \ 290 XCHAL_SEP XCHAL_INT12_TYPE \ 291 XCHAL_SEP XCHAL_INT13_TYPE \ 292 XCHAL_SEP XCHAL_INT14_TYPE \ 293 XCHAL_SEP XCHAL_INT15_TYPE \ 294 XCHAL_SEP XCHAL_INT16_TYPE \ 295 XCHAL_SEP XCHAL_INT17_TYPE \ 296 XCHAL_SEP XCHAL_INT18_TYPE \ 297 XCHAL_SEP XCHAL_INT19_TYPE \ 298 XCHAL_SEP XCHAL_INT20_TYPE \ 299 XCHAL_SEP XCHAL_INT21_TYPE \ 300 XCHAL_SEP XCHAL_INT22_TYPE \ 301 XCHAL_SEP XCHAL_INT23_TYPE \ 302 XCHAL_SEP XCHAL_INT24_TYPE \ 303 XCHAL_SEP XCHAL_INT25_TYPE \ 304 XCHAL_SEP XCHAL_INT26_TYPE \ 305 XCHAL_SEP XCHAL_INT27_TYPE \ 306 XCHAL_SEP XCHAL_INT28_TYPE \ 307 XCHAL_SEP XCHAL_INT29_TYPE \ 308 XCHAL_SEP XCHAL_INT30_TYPE \ 309 XCHAL_SEP XCHAL_INT31_TYPE 310 311 /* Array of masks of interrupts for each type of interrupt: */ 312 #define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ 313 XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ 314 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ 315 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ 316 XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ 317 XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ 318 XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR \ 319 XCHAL_SEP XCHAL_INTTYPE_MASK_IDMA_DONE \ 320 XCHAL_SEP XCHAL_INTTYPE_MASK_IDMA_ERR \ 321 XCHAL_SEP XCHAL_INTTYPE_MASK_GS_ERR 322 323 /* Interrupts that can be cleared using the INTCLEAR special register: */ 324 #define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) 325 /* Interrupts that can be triggered using the INTSET special register: */ 326 #define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE 327 328 /* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ 329 #define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ 330 XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ 331 XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ 332 XCHAL_SEP XCHAL_TIMER3_INTERRUPT 333 334 335 336 /* For backward compatibility and for the array macros, define macros for 337 * each unconfigured interrupt number (unfortunately, the value of 338 * XTHAL_INTTYPE_UNCONFIGURED is not zero): */ 339 #if XCHAL_NUM_INTERRUPTS == 0 340 # define XCHAL_INT0_LEVEL 0 341 # define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED 342 #endif 343 #if XCHAL_NUM_INTERRUPTS <= 1 344 # define XCHAL_INT1_LEVEL 0 345 # define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED 346 #endif 347 #if XCHAL_NUM_INTERRUPTS <= 2 348 # define XCHAL_INT2_LEVEL 0 349 # define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED 350 #endif 351 #if XCHAL_NUM_INTERRUPTS <= 3 352 # define XCHAL_INT3_LEVEL 0 353 # define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED 354 #endif 355 #if XCHAL_NUM_INTERRUPTS <= 4 356 # define XCHAL_INT4_LEVEL 0 357 # define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED 358 #endif 359 #if XCHAL_NUM_INTERRUPTS <= 5 360 # define XCHAL_INT5_LEVEL 0 361 # define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED 362 #endif 363 #if XCHAL_NUM_INTERRUPTS <= 6 364 # define XCHAL_INT6_LEVEL 0 365 # define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED 366 #endif 367 #if XCHAL_NUM_INTERRUPTS <= 7 368 # define XCHAL_INT7_LEVEL 0 369 # define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED 370 #endif 371 #if XCHAL_NUM_INTERRUPTS <= 8 372 # define XCHAL_INT8_LEVEL 0 373 # define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED 374 #endif 375 #if XCHAL_NUM_INTERRUPTS <= 9 376 # define XCHAL_INT9_LEVEL 0 377 # define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED 378 #endif 379 #if XCHAL_NUM_INTERRUPTS <= 10 380 # define XCHAL_INT10_LEVEL 0 381 # define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED 382 #endif 383 #if XCHAL_NUM_INTERRUPTS <= 11 384 # define XCHAL_INT11_LEVEL 0 385 # define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED 386 #endif 387 #if XCHAL_NUM_INTERRUPTS <= 12 388 # define XCHAL_INT12_LEVEL 0 389 # define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED 390 #endif 391 #if XCHAL_NUM_INTERRUPTS <= 13 392 # define XCHAL_INT13_LEVEL 0 393 # define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED 394 #endif 395 #if XCHAL_NUM_INTERRUPTS <= 14 396 # define XCHAL_INT14_LEVEL 0 397 # define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED 398 #endif 399 #if XCHAL_NUM_INTERRUPTS <= 15 400 # define XCHAL_INT15_LEVEL 0 401 # define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED 402 #endif 403 #if XCHAL_NUM_INTERRUPTS <= 16 404 # define XCHAL_INT16_LEVEL 0 405 # define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED 406 #endif 407 #if XCHAL_NUM_INTERRUPTS <= 17 408 # define XCHAL_INT17_LEVEL 0 409 # define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED 410 #endif 411 #if XCHAL_NUM_INTERRUPTS <= 18 412 # define XCHAL_INT18_LEVEL 0 413 # define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED 414 #endif 415 #if XCHAL_NUM_INTERRUPTS <= 19 416 # define XCHAL_INT19_LEVEL 0 417 # define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED 418 #endif 419 #if XCHAL_NUM_INTERRUPTS <= 20 420 # define XCHAL_INT20_LEVEL 0 421 # define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED 422 #endif 423 #if XCHAL_NUM_INTERRUPTS <= 21 424 # define XCHAL_INT21_LEVEL 0 425 # define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED 426 #endif 427 #if XCHAL_NUM_INTERRUPTS <= 22 428 # define XCHAL_INT22_LEVEL 0 429 # define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED 430 #endif 431 #if XCHAL_NUM_INTERRUPTS <= 23 432 # define XCHAL_INT23_LEVEL 0 433 # define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED 434 #endif 435 #if XCHAL_NUM_INTERRUPTS <= 24 436 # define XCHAL_INT24_LEVEL 0 437 # define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED 438 #endif 439 #if XCHAL_NUM_INTERRUPTS <= 25 440 # define XCHAL_INT25_LEVEL 0 441 # define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED 442 #endif 443 #if XCHAL_NUM_INTERRUPTS <= 26 444 # define XCHAL_INT26_LEVEL 0 445 # define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED 446 #endif 447 #if XCHAL_NUM_INTERRUPTS <= 27 448 # define XCHAL_INT27_LEVEL 0 449 # define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED 450 #endif 451 #if XCHAL_NUM_INTERRUPTS <= 28 452 # define XCHAL_INT28_LEVEL 0 453 # define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED 454 #endif 455 #if XCHAL_NUM_INTERRUPTS <= 29 456 # define XCHAL_INT29_LEVEL 0 457 # define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED 458 #endif 459 #if XCHAL_NUM_INTERRUPTS <= 30 460 # define XCHAL_INT30_LEVEL 0 461 # define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED 462 #endif 463 #if XCHAL_NUM_INTERRUPTS <= 31 464 # define XCHAL_INT31_LEVEL 0 465 # define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED 466 #endif 467 468 469 /* 470 * Masks and levels corresponding to each *external* interrupt. 471 */ 472 473 #define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) 474 #define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) 475 #define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) 476 #define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) 477 #define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) 478 #define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) 479 #define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) 480 #define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) 481 #define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) 482 #define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) 483 #define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) 484 #define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) 485 #define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) 486 #define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) 487 #define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) 488 #define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) 489 #define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) 490 #define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) 491 #define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) 492 #define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) 493 #define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) 494 #define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) 495 #define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) 496 #define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) 497 #define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) 498 #define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) 499 #define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) 500 #define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) 501 #define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) 502 #define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) 503 #define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) 504 #define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) 505 #define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) 506 #define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) 507 #define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) 508 #define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) 509 #define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) 510 #define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) 511 #define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) 512 #define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) 513 #define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) 514 #define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) 515 #define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) 516 #define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) 517 #define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) 518 #define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) 519 #define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) 520 #define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) 521 #define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) 522 #define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) 523 #define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) 524 #define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) 525 #define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) 526 #define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) 527 #define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) 528 #define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) 529 #define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) 530 #define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) 531 #define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) 532 #define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) 533 #define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) 534 #define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) 535 #define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) 536 #define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) 537 538 539 /*---------------------------------------------------------------------- 540 EXCEPTIONS and VECTORS 541 ----------------------------------------------------------------------*/ 542 543 /* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ 544 #define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */ 545 #define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */ 546 #ifdef XCHAL_USER_VECTOR_VADDR 547 #define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR 548 #define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR 549 #endif 550 #ifdef XCHAL_USER_VECTOR_PADDR 551 # define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR 552 # define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR 553 #endif 554 #ifdef XCHAL_KERNEL_VECTOR_VADDR 555 # define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR 556 # define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR 557 #endif 558 #ifdef XCHAL_KERNEL_VECTOR_PADDR 559 # define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR 560 # define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR 561 #endif 562 563 #if 0 564 #if XCHAL_HAVE_DEBUG 565 # define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) 566 /* This one should only get defined if the corresponding intlevel paddr macro exists: */ 567 # define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) 568 #endif 569 #endif 570 571 /* Indexing macros: */ 572 #define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR 573 #define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ 574 575 /* 576 * General Exception Causes 577 * (values of EXCCAUSE special register set by general exceptions, 578 * which vector to the user, kernel, or double-exception vectors). 579 * 580 * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros 581 * defined in <xtensa/corebits.h>. (Note that these have slightly 582 * different names, they don't just have the XCHAL_ prefix removed.) 583 */ 584 #define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ 585 #define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ 586 #define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ 587 #define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ 588 #define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ 589 #define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ 590 #define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ 591 #define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ 592 #define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ 593 #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ 594 /*10..15 reserved*/ 595 #define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ 596 #define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ 597 #define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ 598 #define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ 599 #define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ 600 /*21..23 reserved*/ 601 #define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ 602 #define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ 603 #define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ 604 #define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ 605 #define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ 606 #define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ 607 /*30..31 reserved*/ 608 #define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ 609 #define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ 610 #define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ 611 #define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ 612 #define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ 613 #define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ 614 #define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ 615 #define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ 616 /*40..63 reserved*/ 617 618 619 /* 620 * Miscellaneous special register fields. 621 * 622 * For each special register, and each field within each register: 623 * XCHAL_<regname>_VALIDMASK is the set of bits defined in the register. 624 * XCHAL_<regname>_<field>_BITS is the number of bits in the field. 625 * XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values 626 * of the field. 627 * XCHAL_<regname>_<field>_SHIFT is the position of the field within 628 * the register, starting from the least significant bit. 629 * 630 * DEPRECATED. Please use the equivalent macros defined in 631 * <xtensa/corebits.h>. (Note that these have different names.) 632 */ 633 634 /* DBREAKC (special register number 160): */ 635 #define XCHAL_DBREAKC_VALIDMASK 0xC000003F 636 #define XCHAL_DBREAKC_MASK_BITS 6 637 #define XCHAL_DBREAKC_MASK_NUM 64 638 #define XCHAL_DBREAKC_MASK_SHIFT 0 639 #define XCHAL_DBREAKC_MASK_MASK 0x0000003F 640 #define XCHAL_DBREAKC_LOADBREAK_BITS 1 641 #define XCHAL_DBREAKC_LOADBREAK_NUM 2 642 #define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 643 #define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 644 #define XCHAL_DBREAKC_STOREBREAK_BITS 1 645 #define XCHAL_DBREAKC_STOREBREAK_NUM 2 646 #define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 647 #define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 648 /* PS (special register number 230): */ 649 #define XCHAL_PS_VALIDMASK 0x00070F3F 650 #define XCHAL_PS_INTLEVEL_BITS 4 651 #define XCHAL_PS_INTLEVEL_NUM 16 652 #define XCHAL_PS_INTLEVEL_SHIFT 0 653 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F 654 #define XCHAL_PS_EXCM_BITS 1 655 #define XCHAL_PS_EXCM_NUM 2 656 #define XCHAL_PS_EXCM_SHIFT 4 657 #define XCHAL_PS_EXCM_MASK 0x00000010 658 #define XCHAL_PS_UM_BITS 1 659 #define XCHAL_PS_UM_NUM 2 660 #define XCHAL_PS_UM_SHIFT 5 661 #define XCHAL_PS_UM_MASK 0x00000020 662 #define XCHAL_PS_RING_BITS 2 663 #define XCHAL_PS_RING_NUM 4 664 #define XCHAL_PS_RING_SHIFT 6 665 #define XCHAL_PS_RING_MASK 0x000000C0 666 #define XCHAL_PS_OWB_BITS 4 667 #define XCHAL_PS_OWB_NUM 16 668 #define XCHAL_PS_OWB_SHIFT 8 669 #define XCHAL_PS_OWB_MASK 0x00000F00 670 #define XCHAL_PS_CALLINC_BITS 2 671 #define XCHAL_PS_CALLINC_NUM 4 672 #define XCHAL_PS_CALLINC_SHIFT 16 673 #define XCHAL_PS_CALLINC_MASK 0x00030000 674 #define XCHAL_PS_WOE_BITS 1 675 #define XCHAL_PS_WOE_NUM 2 676 #define XCHAL_PS_WOE_SHIFT 18 677 #define XCHAL_PS_WOE_MASK 0x00040000 678 /* EXCCAUSE (special register number 232): */ 679 #define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F 680 #define XCHAL_EXCCAUSE_BITS 6 681 #define XCHAL_EXCCAUSE_NUM 64 682 #define XCHAL_EXCCAUSE_SHIFT 0 683 #define XCHAL_EXCCAUSE_MASK 0x0000003F 684 /* DEBUGCAUSE (special register number 233): */ 685 #define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F 686 #define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 687 #define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 688 #define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 689 #define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 690 #define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 691 #define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 692 #define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 693 #define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 694 #define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 695 #define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 696 #define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 697 #define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 698 #define XCHAL_DEBUGCAUSE_BREAK_BITS 1 699 #define XCHAL_DEBUGCAUSE_BREAK_NUM 2 700 #define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 701 #define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 702 #define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 703 #define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 704 #define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 705 #define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 706 #define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 707 #define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 708 #define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 709 #define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 710 711 712 713 714 /*---------------------------------------------------------------------- 715 TIMERS 716 ----------------------------------------------------------------------*/ 717 718 /*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/ 719 720 721 722 /*---------------------------------------------------------------------- 723 INTERNAL I/D RAM/ROMs and XLMI 724 ----------------------------------------------------------------------*/ 725 726 #define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ 727 #define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ 728 #define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ 729 #define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ 730 731 #define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ 732 #define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ 733 #define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ 734 #define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ 735 #define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ 736 #define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ 737 #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ 738 #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ 739 #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ 740 #define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ 741 #define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ 742 #define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ 743 #define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ 744 #define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ 745 #define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ 746 #define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ 747 #define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ 748 #define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ 749 #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ 750 #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ 751 #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ 752 #define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ 753 #define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ 754 #define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ 755 756 757 758 /*---------------------------------------------------------------------- 759 CACHE 760 ----------------------------------------------------------------------*/ 761 762 763 /* Default PREFCTL value to enable prefetch. */ 764 #if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0 765 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x00044 /* enabled, not aggressive */ 766 #elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0 767 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* + enable prefetch to L1 */ 768 #elif ((XCHAL_PREFETCH_ENTRIES >= 16) && XCHAL_HAVE_CACHE_BLOCKOPS) 769 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */ 770 #elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS) 771 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */ 772 #else 773 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */ 774 #endif 775 776 777 /* Max for both I-cache and D-cache (used for general alignment): */ 778 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE 779 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH 780 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE 781 #else 782 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH 783 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE 784 #endif 785 786 #define XCHAL_ICACHE_SETSIZE (1<<XCHAL_ICACHE_SETWIDTH) 787 #define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH) 788 /* Max for both I and D caches (used for cache-coherency page alignment): */ 789 #if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH 790 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH 791 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE 792 #else 793 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH 794 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE 795 #endif 796 797 /* Instruction cache tag bits: */ 798 #define XCHAL_ICACHE_TAG_V_SHIFT 0 799 #define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ 800 #if XCHAL_ICACHE_WAYS > 1 801 # define XCHAL_ICACHE_TAG_F_SHIFT 1 802 # define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ 803 #else 804 # define XCHAL_ICACHE_TAG_F_SHIFT 0 805 # define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ 806 #endif 807 #if XCHAL_ICACHE_LINE_LOCKABLE 808 # define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) 809 # define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */ 810 #else 811 # define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT 812 # define XCHAL_ICACHE_TAG_L 0 /* no lock bit */ 813 #endif 814 /* Data cache tag bits: */ 815 #define XCHAL_DCACHE_TAG_V_SHIFT 0 816 #define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */ 817 #if XCHAL_DCACHE_WAYS > 1 818 # define XCHAL_DCACHE_TAG_F_SHIFT 1 819 # define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ 820 #else 821 # define XCHAL_DCACHE_TAG_F_SHIFT 0 822 # define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ 823 #endif 824 #if XCHAL_DCACHE_IS_WRITEBACK 825 # define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) 826 # define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */ 827 #else 828 # define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT 829 # define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */ 830 #endif 831 #if XCHAL_DCACHE_LINE_LOCKABLE 832 # define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) 833 # define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_L_SHIFT) /* lock bit */ 834 #else 835 # define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT 836 # define XCHAL_DCACHE_TAG_L 0 /* no lock bit */ 837 #endif 838 839 /* Whether MEMCTL register has anything useful */ 840 #define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ 841 XCHAL_DCACHE_IS_COHERENT || \ 842 XCHAL_HAVE_ICACHE_DYN_WAYS || \ 843 XCHAL_HAVE_DCACHE_DYN_WAYS) && \ 844 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) 845 846 #if XCHAL_DCACHE_IS_COHERENT 847 #define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */ 848 #else 849 #define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */ 850 #endif 851 852 #if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453 853 #define _MEMCTL_L0IBUF_EN 0x00 /* No loop buffer or don't enable */ 854 #else 855 #define _MEMCTL_L0IBUF_EN 0x01 /* Enable loop buffer */ 856 #endif 857 858 /* Default MEMCTL values: */ 859 #if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS 860 #define XCHAL_CACHE_MEMCTL_DEFAULT (0xFFFFFF00 | _MEMCTL_L0IBUF_EN) 861 #else 862 #define XCHAL_CACHE_MEMCTL_DEFAULT (0x00000000 | _MEMCTL_L0IBUF_EN) 863 #endif 864 865 #define XCHAL_SNOOP_LB_MEMCTL_DEFAULT (_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN) 866 867 868 /*---------------------------------------------------------------------- 869 MMU 870 ----------------------------------------------------------------------*/ 871 872 /* See <xtensa/config/core-matmap.h> for more details. */ 873 874 /* Has different semantic in open source headers (where it means HAVE_PTP_MMU), 875 so comment out starting with RB-2008.3 release; later, might get 876 get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: */ 877 /*#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*/ /* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */ 878 879 /* Indexing macros: */ 880 #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what 881 #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) 882 #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what 883 #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) 884 #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what 885 #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) 886 #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what 887 #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) 888 /* 889 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) 890 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set. 891 */ 892 893 /* Number of entries per autorefill way: */ 894 #define XCHAL_ITLB_ARF_ENTRIES (1<<XCHAL_ITLB_ARF_ENTRIES_LOG2) 895 #define XCHAL_DTLB_ARF_ENTRIES (1<<XCHAL_DTLB_ARF_ENTRIES_LOG2) 896 897 /* 898 * Determine whether we have a full MMU (with Page Table and Protection) 899 * usable for an MMU-based OS: 900 */ 901 #if 0 902 #if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 903 # define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */ 904 #else 905 # define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */ 906 #endif 907 #endif 908 909 /* 910 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings: 911 */ 912 #if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY 913 #define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */ 914 #define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */ 915 #define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */ 916 #define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */ 917 #define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */ 918 #define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */ 919 920 #define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */ 921 #define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */ 922 #define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */ 923 #define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */ 924 #define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */ 925 #define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */ 926 927 #define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */ 928 #define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ 929 /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ 930 #endif 931 932 933 /*---------------------------------------------------------------------- 934 MISC 935 ----------------------------------------------------------------------*/ 936 937 /* Data alignment required if used for instructions: */ 938 #if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH 939 # define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH 940 #else 941 # define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH 942 #endif 943 944 /* 945 * Names kept for backward compatibility. 946 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases 947 * under which they are released. In the T10##.# era there was no distinction.) 948 */ 949 #define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR 950 #define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR 951 #define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME 952 953 954 955 956 /*---------------------------------------------------------------------- 957 COPROCESSORS and EXTRA STATE 958 ----------------------------------------------------------------------*/ 959 960 #define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE 961 #define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN 962 #define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE 963 #define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN 964 965 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) 966 967 /* Invoked at start of save area load/store sequence macro to setup macro 968 * internal offsets. Not usually invoked directly. 969 * continue 0 for 1st sequence, 1 for subsequent consecutive ones. 970 * totofs offset from original ptr to next load/store location. 971 */ 972 .macro xchal_sa_start continue totofs 973 .ifeq \continue 974 .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */ 975 .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */ 976 .endif 977 .if \totofs + 1 /* if totofs specified (not -1) */ 978 .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */ 979 .endif 980 .endm 981 982 /* Align portion of save area and bring ptr in range if necessary. 983 * Used by save area load/store sequences. Not usually invoked directly. 984 * Allows combining multiple (sub-)sequences arbitrarily. 985 * ptr pointer to save area (may be off, see .Lxchal_pofs_) 986 * minofs,maxofs range of offset from cur ptr to next load/store loc; 987 * minofs <= 0 <= maxofs (0 must always be valid offset) 988 * range must be within +/- 30kB or so. 989 * ofsalign alignment granularity of minofs .. maxofs (pow of 2) 990 * (restriction on offset from ptr to next load/store loc) 991 * totalign align from orig ptr to next load/store loc (pow of 2) 992 */ 993 .macro xchal_sa_align ptr minofs maxofs ofsalign totalign 994 /* First align where we start accessing the next register 995 * per \totalign relative to original ptr (i.e. start of the save area): 996 */ 997 .set .Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_ 998 /* If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range: */ 999 .if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1)) 1000 .set .Ligmask, 0xFFFFFFFF /* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */ 1001 addi \ptr, \ptr, (.Lxchal_ofs_ & .Ligmask) 1002 .set .Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask) 1003 .set .Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask) 1004 .endif 1005 .endm 1006 /* 1007 * We could optimize for addi to expand to only addmi instead of 1008 * "addmi;addi", where possible. Here's a partial example how: 1009 * .set .Lmaxmask, -(\ofsalign) & -(\totalign) 1010 * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0) 1011 * .set .Ligmask, 0xFFFFFF00 1012 * .elif ... ditto for negative ofs range ... 1013 * .set .Ligmask, 0xFFFFFF00 1014 * .set ... adjust per offset ... 1015 * .else 1016 * .set .Ligmask, 0xFFFFFFFF 1017 * .endif 1018 */ 1019 1020 /* Invoke this after xchal_XXX_{load,store} macros to restore \ptr. */ 1021 .macro xchal_sa_ptr_restore ptr 1022 .if .Lxchal_pofs_ 1023 addi \ptr, \ptr, - .Lxchal_pofs_ 1024 .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ 1025 .set .Lxchal_pofs_, 0 1026 .endif 1027 .endm 1028 1029 /* 1030 * Use as eg: 1031 * xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 1032 * xchal_ncp_load a2, a0,a3,a4,a5 1033 * xchal_atmps_load a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 1034 * 1035 * Specify only the ARs you *haven't* saved/restored already, up to 4. 1036 * They *must* be the *last* ARs (in same order) specified to save area 1037 * load/store sequences. In the example above, a0 and a3 were already 1038 * saved/restored and unused (thus available) but a4 and a5 were not. 1039 */ 1040 #define xchal_atmps_store xchal_atmps_loadstore s32i, 1041 #define xchal_atmps_load xchal_atmps_loadstore l32i, 1042 .macro xchal_atmps_loadstore inst ptr offset nreq aa=0 ab=0 ac=0 ad=0 1043 .set .Lnsaved_, 0 1044 .irp reg,\aa,\ab,\ac,\ad 1045 .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif 1046 .endr 1047 .set .Laofs_, 0 1048 .irp reg,\aa,\ab,\ac,\ad 1049 .ifgt (\nreq)-.Lnsaved_ 1050 \inst \reg, \ptr, .Laofs_+\offset 1051 .set .Laofs_,.Laofs_+4 1052 .set .Lnsaved_,.Lnsaved_+1 1053 .endif 1054 .endr 1055 .endm 1056 1057 /*#define xchal_ncp_load_a2 xchal_ncp_load a2,a3,a4,a5,a6*/ 1058 /*#define xchal_ncp_store_a2 xchal_ncp_store a2,a3,a4,a5,a6*/ 1059 #define xchal_extratie_load xchal_ncptie_load 1060 #define xchal_extratie_store xchal_ncptie_store 1061 #define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6 1062 #define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6 1063 #define xchal_extra_load xchal_ncp_load 1064 #define xchal_extra_store xchal_ncp_store 1065 #define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 1066 #define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 1067 #define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6 1068 #define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6 1069 #define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6 1070 #define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6 1071 #define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6 1072 #define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6 1073 #define xchal_cp2_store_a2 xchal_cp2_store a2,a3,a4,a5,a6 1074 #define xchal_cp2_load_a2 xchal_cp2_load a2,a3,a4,a5,a6 1075 #define xchal_cp3_store_a2 xchal_cp3_store a2,a3,a4,a5,a6 1076 #define xchal_cp3_load_a2 xchal_cp3_load a2,a3,a4,a5,a6 1077 #define xchal_cp4_store_a2 xchal_cp4_store a2,a3,a4,a5,a6 1078 #define xchal_cp4_load_a2 xchal_cp4_load a2,a3,a4,a5,a6 1079 #define xchal_cp5_store_a2 xchal_cp5_store a2,a3,a4,a5,a6 1080 #define xchal_cp5_load_a2 xchal_cp5_load a2,a3,a4,a5,a6 1081 #define xchal_cp6_store_a2 xchal_cp6_store a2,a3,a4,a5,a6 1082 #define xchal_cp6_load_a2 xchal_cp6_load a2,a3,a4,a5,a6 1083 #define xchal_cp7_store_a2 xchal_cp7_store a2,a3,a4,a5,a6 1084 #define xchal_cp7_load_a2 xchal_cp7_load a2,a3,a4,a5,a6 1085 1086 /* Empty placeholder macros for undefined coprocessors: */ 1087 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0 1088 # if XCHAL_CP0_SA_SIZE == 0 1089 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1090 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1091 # endif 1092 # if XCHAL_CP1_SA_SIZE == 0 1093 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1094 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1095 # endif 1096 # if XCHAL_CP2_SA_SIZE == 0 1097 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1098 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1099 # endif 1100 # if XCHAL_CP3_SA_SIZE == 0 1101 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1102 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1103 # endif 1104 # if XCHAL_CP4_SA_SIZE == 0 1105 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1106 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1107 # endif 1108 # if XCHAL_CP5_SA_SIZE == 0 1109 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1110 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1111 # endif 1112 # if XCHAL_CP6_SA_SIZE == 0 1113 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1114 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1115 # endif 1116 # if XCHAL_CP7_SA_SIZE == 0 1117 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1118 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1119 # endif 1120 #endif 1121 1122 /******************** 1123 * Macros to create functions that save and restore the state of *any* TIE 1124 * coprocessor (by dynamic index). 1125 */ 1126 1127 /* 1128 * Macro that expands to the body of a function 1129 * that stores the selected coprocessor's state (registers etc). 1130 * Entry: a2 = ptr to save area in which to save cp state 1131 * a3 = coprocessor number 1132 * Exit: any register a2-a15 (?) may have been clobbered. 1133 */ 1134 .macro xchal_cpi_store_funcbody 1135 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) 1136 # if XCHAL_CP0_SA_SIZE 1137 bnez a3, 99f 1138 xchal_cp0_store_a2 1139 j 90f 1140 99: 1141 # endif 1142 # if XCHAL_CP1_SA_SIZE 1143 bnei a3, 1, 99f 1144 xchal_cp1_store_a2 1145 j 90f 1146 99: 1147 # endif 1148 # if XCHAL_CP2_SA_SIZE 1149 bnei a3, 2, 99f 1150 xchal_cp2_store_a2 1151 j 90f 1152 99: 1153 # endif 1154 # if XCHAL_CP3_SA_SIZE 1155 bnei a3, 3, 99f 1156 xchal_cp3_store_a2 1157 j 90f 1158 99: 1159 # endif 1160 # if XCHAL_CP4_SA_SIZE 1161 bnei a3, 4, 99f 1162 xchal_cp4_store_a2 1163 j 90f 1164 99: 1165 # endif 1166 # if XCHAL_CP5_SA_SIZE 1167 bnei a3, 5, 99f 1168 xchal_cp5_store_a2 1169 j 90f 1170 99: 1171 # endif 1172 # if XCHAL_CP6_SA_SIZE 1173 bnei a3, 6, 99f 1174 xchal_cp6_store_a2 1175 j 90f 1176 99: 1177 # endif 1178 # if XCHAL_CP7_SA_SIZE 1179 bnei a3, 7, 99f 1180 xchal_cp7_store_a2 1181 j 90f 1182 99: 1183 # endif 1184 90: 1185 #endif 1186 .endm 1187 1188 /* 1189 * Macro that expands to the body of a function 1190 * that loads the selected coprocessor's state (registers etc). 1191 * Entry: a2 = ptr to save area from which to restore cp state 1192 * a3 = coprocessor number 1193 * Exit: any register a2-a15 (?) may have been clobbered. 1194 */ 1195 .macro xchal_cpi_load_funcbody 1196 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) 1197 # if XCHAL_CP0_SA_SIZE 1198 bnez a3, 99f 1199 xchal_cp0_load_a2 1200 j 90f 1201 99: 1202 # endif 1203 # if XCHAL_CP1_SA_SIZE 1204 bnei a3, 1, 99f 1205 xchal_cp1_load_a2 1206 j 90f 1207 99: 1208 # endif 1209 # if XCHAL_CP2_SA_SIZE 1210 bnei a3, 2, 99f 1211 xchal_cp2_load_a2 1212 j 90f 1213 99: 1214 # endif 1215 # if XCHAL_CP3_SA_SIZE 1216 bnei a3, 3, 99f 1217 xchal_cp3_load_a2 1218 j 90f 1219 99: 1220 # endif 1221 # if XCHAL_CP4_SA_SIZE 1222 bnei a3, 4, 99f 1223 xchal_cp4_load_a2 1224 j 90f 1225 99: 1226 # endif 1227 # if XCHAL_CP5_SA_SIZE 1228 bnei a3, 5, 99f 1229 xchal_cp5_load_a2 1230 j 90f 1231 99: 1232 # endif 1233 # if XCHAL_CP6_SA_SIZE 1234 bnei a3, 6, 99f 1235 xchal_cp6_load_a2 1236 j 90f 1237 99: 1238 # endif 1239 # if XCHAL_CP7_SA_SIZE 1240 bnei a3, 7, 99f 1241 xchal_cp7_load_a2 1242 j 90f 1243 99: 1244 # endif 1245 90: 1246 #endif 1247 .endm 1248 1249 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ 1250 1251 1252 /* Other default macros for undefined coprocessors: */ 1253 #ifndef XCHAL_CP0_NAME 1254 # define XCHAL_CP0_NAME 0 1255 # define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 1256 # define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ 1257 #endif 1258 #ifndef XCHAL_CP1_NAME 1259 # define XCHAL_CP1_NAME 0 1260 # define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 1261 # define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ 1262 #endif 1263 #ifndef XCHAL_CP2_NAME 1264 # define XCHAL_CP2_NAME 0 1265 # define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 1266 # define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ 1267 #endif 1268 #ifndef XCHAL_CP3_NAME 1269 # define XCHAL_CP3_NAME 0 1270 # define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 1271 # define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ 1272 #endif 1273 #ifndef XCHAL_CP4_NAME 1274 # define XCHAL_CP4_NAME 0 1275 # define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 1276 # define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ 1277 #endif 1278 #ifndef XCHAL_CP5_NAME 1279 # define XCHAL_CP5_NAME 0 1280 # define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 1281 # define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ 1282 #endif 1283 #ifndef XCHAL_CP6_NAME 1284 # define XCHAL_CP6_NAME 0 1285 # define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 1286 # define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ 1287 #endif 1288 #ifndef XCHAL_CP7_NAME 1289 # define XCHAL_CP7_NAME 0 1290 # define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 1291 # define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ 1292 #endif 1293 1294 #if XCHAL_CP_MASK == 0 1295 /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 1296 #define XCHAL_CP0_SA_SIZE 0 1297 #define XCHAL_CP0_SA_ALIGN 1 1298 #define XCHAL_CP1_SA_SIZE 0 1299 #define XCHAL_CP1_SA_ALIGN 1 1300 #define XCHAL_CP2_SA_SIZE 0 1301 #define XCHAL_CP2_SA_ALIGN 1 1302 #define XCHAL_CP3_SA_SIZE 0 1303 #define XCHAL_CP3_SA_ALIGN 1 1304 #define XCHAL_CP4_SA_SIZE 0 1305 #define XCHAL_CP4_SA_ALIGN 1 1306 #define XCHAL_CP5_SA_SIZE 0 1307 #define XCHAL_CP5_SA_ALIGN 1 1308 #define XCHAL_CP6_SA_SIZE 0 1309 #define XCHAL_CP6_SA_ALIGN 1 1310 #define XCHAL_CP7_SA_SIZE 0 1311 #define XCHAL_CP7_SA_ALIGN 1 1312 #endif 1313 1314 1315 /* Indexing macros: */ 1316 #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE 1317 #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ 1318 #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN 1319 #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ 1320 1321 #define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ 1322 1323 /* Link-time HAL global variables that report coprocessor numbers by name 1324 (names are case-preserved from the original TIE): */ 1325 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 1326 # define _XCJOIN(a,b) a ## b 1327 # define XCJOIN(a,b) _XCJOIN(a,b) 1328 # ifdef XCHAL_CP0_NAME 1329 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT); 1330 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT); 1331 # endif 1332 # ifdef XCHAL_CP1_NAME 1333 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT); 1334 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT); 1335 # endif 1336 # ifdef XCHAL_CP2_NAME 1337 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT); 1338 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT); 1339 # endif 1340 # ifdef XCHAL_CP3_NAME 1341 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT); 1342 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT); 1343 # endif 1344 # ifdef XCHAL_CP4_NAME 1345 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT); 1346 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT); 1347 # endif 1348 # ifdef XCHAL_CP5_NAME 1349 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT); 1350 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT); 1351 # endif 1352 # ifdef XCHAL_CP6_NAME 1353 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT); 1354 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT); 1355 # endif 1356 # ifdef XCHAL_CP7_NAME 1357 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT); 1358 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT); 1359 # endif 1360 #endif 1361 1362 1363 1364 1365 /*---------------------------------------------------------------------- 1366 DERIVED 1367 ----------------------------------------------------------------------*/ 1368 1369 #if XCHAL_HAVE_BE 1370 #define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */ 1371 #define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */ 1372 #define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */ 1373 #else 1374 #define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */ 1375 #define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */ 1376 #define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */ 1377 #endif 1378 /* Belongs in xtensa/hal.h: */ 1379 #define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ 1380 1381 1382 /* 1383 * Because information as to exactly which hardware version is targeted 1384 * by a given software build is not always available, compile-time HAL 1385 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): 1386 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases 1387 * under which they are released. In the T10##.# era there was no distinction.) 1388 */ 1389 #if XCHAL_HW_CONFIGID_RELIABLE 1390 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1391 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1392 # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1393 # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) 1394 #else 1395 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ 1396 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ 1397 : XTHAL_MAYBE ) 1398 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ 1399 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ 1400 : XTHAL_MAYBE ) 1401 # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ 1402 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) 1403 # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) 1404 #endif 1405 1406 1407 #endif /*XTENSA_CONFIG_CORE_H*/ 1408 1409
