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Searched defs:XCHAL_ICACHE_LINESIZE (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h157 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h212 #define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h232 #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h212 #define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h291 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dcore-isa.h237 #define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h284 #define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h289 #define XCHAL_ICACHE_LINESIZE 8 /* I-cache line size in bytes */ macro