XCHAL_HAVE_XLT_CACHEATTR (definition) in projects: sof-2.7.6

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Searched defs:XCHAL_HAVE_XLT_CACHEATTR (Results 1 – 12 of 12) sorted by relevance

/sof-2.7.6/src/platform/baytrail/include/arch/xtensa/config/
D	core-isa.h	`478 #define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/amd/renoir/include/arch/xtensa/config/
D	core-isa.h	`520 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/suecreek/include/arch/xtensa/config/
D	core-isa.h	`580 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/cannonlake/include/arch/xtensa/config/
D	core-isa.h	`580 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/haswell/include/arch/xtensa/config/
D	core-isa-hsw.h	`588 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
D	core-isa-bdw.h	`588 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/icelake/include/arch/xtensa/config/
D	core-isa.h	`580 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/apollolake/include/arch/xtensa/config/
D	core-isa.h	`580 #define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/tigerlake/include/arch/xtensa/config/
D	core-isa.h	`603 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/imx8m/include/arch/xtensa/config/
D	core-isa.h	`612 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/imx8/include/arch/xtensa/config/
D	core-isa.h	`614 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`
/sof-2.7.6/src/platform/imx8ulp/include/arch/xtensa/config/
D	core-isa.h	`645 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
bsim-3.4.0
bsim-3.6.0-3.5.0
bsim-3.7.0
canopennode-2.7.6
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civetweb-2.7.6
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cmsis-3.7.0-3.6.0
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cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
edtt-2.7.6
edtt-3.6.0-3.5.0-3.4.0
edtt-3.7.0
fatfs-2.7.6
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hal_microchip-3.6.0-3.5.0-3.4.0
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hal_nordic-2.7.6
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hal_openisa-2.7.6
hal_openisa-3.5.0-3.4.0
hal_openisa-3.7.0-3.6.0
hal_quicklogic-3.6.0-3.5.0-3.4.0-2.7.6
hal_quicklogic-3.7.0
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hal_renesas-3.6.0
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hal_rpi_pico-3.4.0
hal_rpi_pico-3.7.0-3.6.0-3.5.0
hal_silabs-2.7.6
hal_silabs-3.4.0
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hal_silabs-3.7.0
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hal_st-3.6.0
hal_st-3.7.0
hal_stm32-2.7.6
hal_stm32-3.4.0
hal_stm32-3.5.0
hal_stm32-3.6.0
hal_stm32-3.7.0
hal_telink-2.7.6
hal_telink-3.6.0-3.5.0-3.4.0
hal_telink-3.7.0
hal_ti-2.7.6
hal_ti-3.4.0
hal_ti-3.7.0-3.6.0-3.5.0
hal_wurthelektronik-3.5.0-3.4.0
hal_wurthelektronik-3.7.0-3.6.0
hal_xtensa-2.7.6
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lvgl-2.7.6
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lvgl-3.6.0
lvgl-3.7.0
lz4-3.4.0-2.7.6
mbedtls-2.7.6
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segger-2.7.6
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segger-3.6.0-3.5.0
segger-3.7.0
sof-2.7.6
sof-3.4.0
tf-m-tests-3.4.0
tflite-micro-3.4.0-2.7.6
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tinycbor-2.7.6
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tinycrypt-3.7.0
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zscilib-3.4.0