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Searched defs:XCHAL_HAVE_PREFETCH (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h168 #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h250 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h250 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h250 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h250 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h223 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h243 #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h223 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h304 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h248 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h297 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h304 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h302 #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ macro