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Searched defs:XCHAL_HAVE_CP (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h88 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h95 #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h96 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h96 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro