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Searched defs:XCHAL_HAVE_CACHEATTR (Results 1 – 7 of 7) sorted by relevance

/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_18/xtensa/config/
Dcore-isa.h578 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_20/xtensa/config/
Dcore-isa.h578 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h578 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
/hal_xtensa-2.7.6/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h616 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
/hal_xtensa-2.7.6/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h614 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_25/xtensa/config/
Dcore-isa.h601 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h650 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro