1 /* 2 * Copyright 2022-2023 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_WM8962_H_ 9 #define _FSL_WM8962_H_ 10 11 #include "fsl_codec_i2c.h" 12 #include "fsl_common.h" 13 14 /*! 15 * @addtogroup wm8962 16 * @ingroup codec 17 * @{ 18 */ 19 20 /******************************************************************************* 21 * Definitions 22 ******************************************************************************/ 23 /*! @name Driver version */ 24 /*@{*/ 25 /*! @brief CLOCK driver version 2.1.3 */ 26 #define FSL_WM8962_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) 27 /*@}*/ 28 29 /*! @brief wm8962 handle size */ 30 #ifndef WM8962_I2C_HANDLER_SIZE 31 #define WM8962_I2C_HANDLER_SIZE CODEC_I2C_MASTER_HANDLER_SIZE 32 #endif 33 34 #define DEBUG_WM8962_REGISTER 0 35 #if DEBUG_WM8962_REGISTER 36 #include "fsl_debug_console.h" 37 #endif 38 39 #define DEBUG_WM8962_MODULE_NUM 11 40 41 /*! @brief Define the register address of WM8962. */ 42 #define WM8962_LINVOL 0x0U 43 #define WM8962_RINVOL 0x1U 44 #define WM8962_LOUT1 0x2U 45 #define WM8962_ROUT1 0x3U 46 #define WM8962_CLOCK1 0x4U 47 #define WM8962_DACCTL1 0x5U 48 #define WM8962_DACCTL2 0x6U 49 #define WM8962_IFACE0 0x7U 50 #define WM8962_IFACE1 0x9U 51 #define WM8962_CLOCK2 0x8U 52 #define WM8962_IFACE2 0xEU 53 #define WM8962_LDAC 0xaU 54 #define WM8962_RDAC 0xbU 55 56 #define WM8962_RESET 0xfU 57 #define WM8962_3D 0x10U 58 #define WM8962_ALC1 0x11U 59 #define WM8962_ALC2 0x12U 60 #define WM8962_ALC3 0x13U 61 #define WM8962_NOISEG 0x14U 62 #define WM8962_LADC 0x15U 63 #define WM8962_RADC 0x16U 64 #define WM8962_ADDCTL1 0x17U 65 #define WM8962_ADDCTL2 0x18U 66 #define WM8962_POWER1 0x19U 67 #define WM8962_POWER2 0x1aU 68 #define WM8962_ADDCTL3 0x1bU 69 #define WM8962_APOP1 0x1cU 70 #define WM8962_APOP2 0x1dU 71 #define WM8962_INPUT_MIXER_1 0x1FU 72 73 #define WM8962_LINPATH 0x20U 74 #define WM8962_RINPATH 0x21U 75 #define WM8962_INPUTMIX 0x22U 76 77 #define WM8962_LEFT_INPUT_PGA 0x25U 78 #define WM8962_RIGHT_INPUT_PGA 0x26U 79 #define WM8962_MONOMIX2 0x27U 80 #define WM8962_LOUT2 0x28U 81 #define WM8962_ROUT2 0x29U 82 #define WM8962_TEMP 0x2FU 83 #define WM8962_ADDCTL4 0x30U 84 #define WM8962_CLASSD1 0x31U 85 86 #define WM8962_CLASSD3 0x33U 87 #define WM8962_PLL1 0x34U 88 #define WM8962_PLL2 0x35U 89 #define WM8962_PLL3 0x36U 90 #define WM8962_PLL4 0x37U 91 #define WM8962_CLK4 0x38U 92 #define WM8962_DC_SERVO_0 0x3CU 93 #define WM8962_DC_SERVO_1 0x3DU 94 #define WM8962_ANALOG_HP_0 0x45U 95 #define WM8962_CHARGE_PUMP_1 0x48U 96 97 #define WM8962_LEFT_HEADPHONE_MIXER 0x64U 98 #define WM8962_RIGHT_HEADPHONE_MIXER 0x65U 99 #define WM8962_LEFT_HEADPHONE_MIXER_VOLUME 0x66U 100 #define WM8962_RIGHT_HEADPHONE_MIXER_VOLUME 0x67U 101 102 #define WM8962_LEFT_SPEAKER_MIXER 0x69U 103 #define WM8962_RIGHT_SPEAKER_MIXER 0x6AU 104 #define WM8962_LEFT_SPEAKER_MIXER_VOLUME 0x6BU 105 #define WM8962_RIGHT_SPEAKER_MIXER_VOLUME 0x6CU 106 107 #define WM8962_FLL_CTRL_1 0x9BU 108 #define WM8962_FLL_CTRL_2 0x9CU 109 #define WM8962_FLL_CTRL_3 0x9DU 110 #define WM8962_FLL_CTRL_6 0xA0U 111 #define WM8962_FLL_CTRL_7 0xA1U 112 #define WM8962_FLL_CTRL_8 0xA2U 113 #define WM8962_INT_STATUS_2 0x231U 114 /*! @brief Cache register number */ 115 #define WM8962_CACHEREGNUM 56U 116 117 /*! @brief WM8962 CLOCK2 bits */ 118 #define WM8962_CLOCK2_BCLK_DIV_MASK 0xFU 119 120 /*! @brief WM8962_IFACE0 FORMAT bits */ 121 #define WM8962_IFACE0_FORMAT_MASK 0x13U 122 #define WM8962_IFACE0_FORMAT_SHIFT 0x00U 123 #define WM8962_IFACE0_FORMAT_RJ 0x00U 124 #define WM8962_IFACE0_FORMAT_LJ 0x01U 125 #define WM8962_IFACE0_FORMAT_I2S 0x02U 126 #define WM8962_IFACE0_FORMAT_DSP 0x03U 127 #define WM8962_IFACE0_FORMAT(x) (((x) << WM8962_IFACE1_FORMAT_SHIFT) & WM8962_IFACE1_FORMAT_MASK) 128 129 /*! @brief WM8962_IFACE0 WL bits */ 130 #define WM8962_IFACE0_WL_MASK 0x0CU 131 #define WM8962_IFACE0_WL_SHIFT 0x02U 132 #define WM8962_IFACE0_WL_16BITS 0x00U 133 #define WM8962_IFACE0_WL_20BITS 0x01U 134 #define WM8962_IFACE0_WL_24BITS 0x02U 135 #define WM8962_IFACE0_WL_32BITS 0x03U 136 #define WM8962_IFACE0_WL(x) (((x) << WM8962_IFACE0_WL_SHIFT) & WM8962_IFACE0_WL_MASK) 137 138 /*! @brief WM8962_IFACE1 LRP bit */ 139 #define WM8962_IFACE1_LRP_MASK 0x10U 140 #define WM8962_IFACE1_LRP_SHIFT 0x04U 141 #define WM8962_IFACE1_LRCLK_NORMAL_POL 0x00U 142 #define WM8962_IFACE1_LRCLK_INVERT_POL 0x01U 143 #define WM8962_IFACE1_DSP_MODEA 0x00U 144 #define WM8962_IFACE1_DSP_MODEB 0x01U 145 #define WM8962_IFACE1_LRP(x) (((x) << WM8962_IFACE1_LRP_SHIFT) & WM8962_IFACE1_LRP_MASK) 146 147 /*! @brief WM8962_IFACE1 DLRSWAP bit */ 148 #define WM8962_IFACE1_DLRSWAP_MASK 0x20U 149 #define WM8962_IFACE1_DLRSWAP_SHIFT 0x05U 150 #define WM8962_IFACE1_DACCH_NORMAL 0x00U 151 #define WM8962_IFACE1_DACCH_SWAP 0x01U 152 #define WM8962_IFACE1_DLRSWAP(x) (((x) << WM8962_IFACE1_DLRSWAP_SHIFT) & WM8962_IFACE1_DLRSWAP_MASK) 153 154 /*! @brief WM8962_IFACE1 MS bit */ 155 #define WM8962_IFACE1_MS_MASK 0x40U 156 #define WM8962_IFACE1_MS_SHIFT 0x06U 157 #define WM8962_IFACE1_SLAVE 0x00U 158 #define WM8962_IFACE1_MASTER 0x01U 159 #define WM8962_IFACE1_MS(x) (((x) << WM8962_IFACE1_MS_SHIFT) & WM8962_IFACE1_MS_MASK) 160 161 /*! @brief WM8962_IFACE1 BCLKINV bit */ 162 #define WM8962_IFACE1_BCLKINV_MASK 0x80U 163 #define WM8962_IFACE1_BCLKINV_SHIFT 0x07U 164 #define WM8962_IFACE1_BCLK_NONINVERT 0x00U 165 #define WM8962_IFACE1_BCLK_INVERT 0x01U 166 #define WM8962_IFACE1_BCLKINV(x) (((x) << WM8962_IFACE1_BCLKINV_SHIFT) & WM8962_IFACE1_BCLKINV_MASK) 167 168 /*! @brief WM8962_IFACE1 ALRSWAP bit */ 169 #define WM8962_IFACE1_ALRSWAP_MASK 0x100U 170 #define WM8962_IFACE1_ALRSWAP_SHIFT 0x08U 171 #define WM8962_IFACE1_ADCCH_NORMAL 0x00U 172 #define WM8962_IFACE1_ADCCH_SWAP 0x01U 173 #define WM8962_IFACE1_ALRSWAP(x) (((x) << WM8962_IFACE1_ALRSWAP_SHIFT) & WM8962_IFACE1_ALRSWAP_MASK) 174 175 /*! @brief WM8962_POWER1 */ 176 #define WM8962_POWER1_VREF_MASK 0x40U 177 #define WM8962_POWER1_VREF_SHIFT 0x06U 178 179 #define WM8962_POWER1_AINL_MASK 0x20U 180 #define WM8962_POWER1_AINL_SHIFT 0x05U 181 182 #define WM8962_POWER1_AINR_MASK 0x10U 183 #define WM8962_POWER1_AINR_SHIFT 0x04U 184 185 #define WM8962_POWER1_ADCL_MASK 0x08U 186 #define WM8962_POWER1_ADCL_SHIFT 0x03U 187 188 #define WM8962_POWER1_ADCR_MASK 0x4U 189 #define WM8962_POWER1_ADCR_SHIFT 0x02U 190 191 #define WM8962_POWER1_MICB_MASK 0x02U 192 #define WM8962_POWER1_MICB_SHIFT 0x01U 193 194 #define WM8962_POWER1_DIGENB_MASK 0x01U 195 #define WM8962_POWER1_DIGENB_SHIFT 0x00U 196 197 /*! @brief WM8962_POWER2 */ 198 #define WM8962_POWER2_DACL_MASK 0x100U 199 #define WM8962_POWER2_DACL_SHIFT 0x08U 200 201 #define WM8962_POWER2_DACR_MASK 0x80U 202 #define WM8962_POWER2_DACR_SHIFT 0x07U 203 204 #define WM8962_POWER2_LOUT1_MASK 0x40U 205 #define WM8962_POWER2_LOUT1_SHIFT 0x06U 206 207 #define WM8962_POWER2_ROUT1_MASK 0x20U 208 #define WM8962_POWER2_ROUT1_SHIFT 0x05U 209 210 #define WM8962_POWER2_SPKL_MASK 0x10U 211 #define WM8962_POWER2_SPKL_SHIFT 0x04U 212 213 #define WM8962_POWER2_SPKR_MASK 0x08U 214 #define WM8962_POWER2_SPKR_SHIFT 0x03U 215 216 #define WM8962_POWER3_LMIC_MASK 0x20U 217 #define WM8962_POWER3_LMIC_SHIFT 0x05U 218 #define WM8962_POWER3_RMIC_MASK 0x10U 219 #define WM8962_POWER3_RMIC_SHIFT 0x04U 220 #define WM8962_POWER3_LOMIX_MASK 0x08U 221 #define WM8962_POWER3_LOMIX_SHIFT 0x03U 222 #define WM8962_POWER3_ROMIX_MASK 0x04U 223 #define WM8962_POWER3_ROMIX_SHIFT 0x02U 224 /*! @brief WM8962 I2C address. */ 225 #define WM8962_I2C_ADDR (0x34 >> 1U) 226 /*! @brief WM8962 I2C baudrate */ 227 #define WM8962_I2C_BAUDRATE (100000U) 228 /*! @brief WM8962 maximum volume value */ 229 #define WM8962_ADC_MAX_VOLUME_vALUE 0xFFU 230 #define WM8962_DAC_MAX_VOLUME_vALUE 0xFFU 231 #define WM8962_HEADPHONE_MAX_VOLUME_vALUE 0x7FU 232 #define WM8962_HEADPHONE_MIN_VOLUME_vALUE 0x2FU 233 #define WM8962_LINEIN_MAX_VOLUME_vALUE 0x3FU 234 #define WM8962_SPEAKER_MAX_VOLUME_vALUE 0x7FU 235 #define WM8962_SPEAKER_MIN_VOLUME_vALUE 0x2FU 236 237 /*! @brief wm8962 input mixer source. 238 * @anchor wm8962_input_mixer_source_t 239 */ 240 enum 241 { 242 kWM8962_InputMixerSourceInput2 = 4U, /*!< input mixer source input 2 */ 243 kWM8962_InputMixerSourceInput3 = 2U, /*!< input mixer source input 3 */ 244 kWM8962_InputMixerSourceInputPGA = 1U, /*!< input mixer source input PGA */ 245 }; 246 247 /*! @brief wm8962 output mixer source. 248 * @anchor wm8962_output_mixer_source_t 249 */ 250 enum 251 { 252 kWM8962_OutputMixerDisabled = 0U, /*!< output mixer disabled */ 253 kWM8962_OutputMixerSourceInput4Right = 1U, /*!< output mixer source input 4 left */ 254 kWM8962_OutputMixerSourceInput4Left = 2U, /*!< output mixer source input 4 right */ 255 kWM8962_OutputMixerSourceRightInputMixer = 4U, /*!< output mixer source left input mixer */ 256 kWM8962_OutputMixerSourceLeftInputMixer = 8U, /*!< output mixer source right input mixer*/ 257 kWM8962_OutputMixerSourceRightDAC = 0x10U, /*!< output mixer source left DAC */ 258 kWM8962_OutputMixerSourceLeftDAC = 0x20U, /*!< output mixer source Right DAC */ 259 }; 260 261 /*! @brief Modules in WM8962 board. */ 262 typedef enum _wm8962_module 263 { 264 kWM8962_ModuleADC = 0, /*!< ADC module in WM8962 */ 265 kWM8962_ModuleDAC = 1, /*!< DAC module in WM8962 */ 266 kWM8962_ModuleMICB = 4, /*!< Mic bias */ 267 kWM8962_ModuleMIC = 5, /*!< Input Mic */ 268 kWM8962_ModuleLineIn = 6, /*!< Analog in PGA */ 269 kWM8962_ModuleHeadphone = 7, /*!< Line out module */ 270 kWM8962_ModuleSpeaker = 8, /*!< Speaker module */ 271 kWM8962_ModuleHeaphoneMixer = 9, /*!< Output mixer */ 272 kWM8962_ModuleSpeakerMixer = 10, /*!< Output mixer */ 273 } wm8962_module_t; 274 275 /*! @brief wm8962 play channel 276 * @anchor _wm8962_play_channel 277 */ 278 enum 279 { 280 kWM8962_HeadphoneLeft = 1, /*!< wm8962 headphone left channel */ 281 kWM8962_HeadphoneRight = 2, /*!< wm8962 headphone right channel */ 282 kWM8962_SpeakerLeft = 4, /*!< wm8962 speaker left channel */ 283 kWM8962_SpeakerRight = 8, /*!< wm8962 speaker right channel */ 284 }; 285 286 /*! 287 * @brief The audio data transfer protocol choice. 288 * WM8962 only supports I2S format and PCM format. 289 */ 290 typedef enum _wm8962_protocol 291 { 292 kWM8962_BusPCMA = 4, /*!< PCMA mode */ 293 kWM8962_BusPCMB = 3, /*!< PCMB mode */ 294 kWM8962_BusI2S = 2, /*!< I2S type */ 295 kWM8962_BusLeftJustified = 1, /*!< Left justified mode */ 296 kWM8962_BusRightJustified = 0, /*!< Right justified mode */ 297 } wm8962_protocol_t; 298 299 /*! @brief wm8962 input source */ 300 typedef enum _wm8962_input_pga_source 301 { 302 kWM8962_InputPGASourceInput1 = 8, /*!< Input PGA source input1 */ 303 kWM8962_InputPGASourceInput2 = 4, /*!< Input PGA source input2 */ 304 kWM8962_InputPGASourceInput3 = 2, /*!< Input PGA source input3 */ 305 kWM8962_InputPGASourceInput4 = 1, /*!< Input PGA source input4 */ 306 } wm8962_input_pga_source_t; 307 308 /*! @brief wm8962 input source */ 309 typedef enum _wm8962_output_pga_source 310 { 311 kWM8962_OutputPGASourceMixer = 0, /*!< Output PGA source mixer */ 312 kWM8962_OutputPGASourceDAC = 1, /*!< Output PGA source DAC */ 313 } wm8962_output_pga_source_t; 314 315 /*! @brief audio sample rate definition 316 * @anchor _wm8962_sample_rate 317 */ 318 enum 319 { 320 kWM8962_AudioSampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ 321 kWM8962_AudioSampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ 322 kWM8962_AudioSampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ 323 kWM8962_AudioSampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ 324 kWM8962_AudioSampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ 325 kWM8962_AudioSampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ 326 kWM8962_AudioSampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ 327 kWM8962_AudioSampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ 328 kWM8962_AudioSampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ 329 kWM8962_AudioSampleRate88200Hz = 88200U, /*!< Sample rate 88200 Hz */ 330 kWM8962_AudioSampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ 331 }; 332 333 /*! @brief audio bit width 334 * @anchor _wm8962_audio_bit_width 335 */ 336 enum 337 { 338 kWM8962_AudioBitWidth16bit = 16U, /*!< audio bit width 16 */ 339 kWM8962_AudioBitWidth20bit = 20U, /*!< audio bit width 20 */ 340 kWM8962_AudioBitWidth24bit = 24U, /*!< audio bit width 24 */ 341 kWM8962_AudioBitWidth32bit = 32U, /*!< audio bit width 32 */ 342 }; 343 344 /*! @brief wm8962 fll clock source */ 345 typedef enum _wm8962_fllclk_source 346 { 347 kWM8962_FLLClkSourceMCLK = 0U, /*!< FLL clock source from MCLK */ 348 kWM8962_FLLClkSourceBCLK = 1U, /*!< FLL clock source from BCLK */ 349 } wm8962_fllclk_source_t; 350 351 /*! @brief wm8962 sysclk source */ 352 typedef enum _wm8962_sysclk_source 353 { 354 kWM8962_SysClkSourceMclk = 0U, /*!< sysclk source from external MCLK */ 355 kWM8962_SysClkSourceFLL = 1U, /*!< sysclk source from internal FLL */ 356 } wm8962_sysclk_source_t; 357 358 /*! @brief wm8962 audio format */ 359 typedef struct _wm8962_audio_format 360 { 361 uint32_t mclk_HZ; /*!< master clock frequency */ 362 uint32_t sampleRate; /*!< sample rate */ 363 uint32_t bitWidth; /*!< bit width */ 364 } wm8962_audio_format_t; 365 366 /*! @brief wm8962 master system clock configuration */ 367 typedef struct _wm8962_fll_clk_config 368 { 369 wm8962_fllclk_source_t fllClockSource; /*!< fll clock source */ 370 uint32_t fllReferenceClockFreq; /*!< external input frequency */ 371 uint32_t fllOutputFreq; /*!< FLL output frequency value */ 372 } wm8962_fll_clk_config_t; 373 374 /*! 375 * @brief WM8962 data route configurations 376 */ 377 typedef struct _wm8962_route_config 378 { 379 bool enableLoopBack; /*!< enable loopback: ADC->DAC directly*/ 380 381 /* adc input come from input mixer, input mixer source from: input PGA OR external input */ 382 wm8962_input_pga_source_t leftInputPGASource; /*!< Left input source for WM8962 */ 383 uint32_t leftInputMixerSource; /*!< left input MIXER source, combination value of wm8962_input_mixer_source_t */ 384 385 wm8962_input_pga_source_t rightInputPGASource; /*!< right input PGA source */ 386 uint32_t rightInputMixerSource; /*!< right input MIXER source, combination value of wm8962_input_mixer_source_t */ 387 388 /* headphone/speaker source from output PGA, output PGA source from mixer OR DAC */ 389 uint32_t 390 leftSpeakerMixerSource; /*!< speaker left MIXER source, combination value of wm8962_output_mixer_source_t */ 391 wm8962_output_pga_source_t leftSpeakerPGASource; /*!< speaker left PGA source */ 392 393 uint32_t 394 rightSpeakerMixerSource; /*!< speaker right MIXER source, combination value of wm8962_output_mixer_source_t */ 395 wm8962_output_pga_source_t rightSpeakerPGASource; /*!< speaker left PGA source */ 396 397 uint32_t 398 leftHeadphoneMixerSource; /*!< headphone left MIXER source, combination value of wm8962_output_mixer_source_t */ 399 wm8962_output_pga_source_t leftHeadphonePGASource; /*!< speaker left PGA source */ 400 401 uint32_t rightHeadphoneMixerSource; /*!< headphone left MIXER source, combination value of 402 wm8962_output_mixer_source_t */ 403 wm8962_output_pga_source_t rightHeadphonePGASource; /*!< speaker left PGA source */ 404 } wm8962_route_config_t; 405 406 /*! @brief Initialize structure of WM8962 */ 407 typedef struct wm8962_config 408 { 409 wm8962_route_config_t route; /*!< Audio data route.*/ 410 411 wm8962_protocol_t bus; /*!< Audio transfer protocol */ 412 wm8962_audio_format_t format; /*!< Audio format */ 413 414 bool masterSlave; /*!< Master or slave. true: master mode, false: slave mode */ 415 wm8962_sysclk_source_t sysclkSource; /*!< sysclk source */ 416 wm8962_fll_clk_config_t fllClock; /*!< FLL clock configurations, shall be configured when masterSlave is true */ 417 418 uint8_t slaveAddress; /*!< wm8962 device address */ 419 codec_i2c_config_t i2cConfig; /*!< i2c configuration */ 420 } wm8962_config_t; 421 422 /*! @brief wm8962 codec handler 423 */ 424 typedef struct _wm8962_handle 425 { 426 const wm8962_config_t *config; /*!< wm8904 config pointer */ 427 uint16_t volume[DEBUG_WM8962_MODULE_NUM]; /*!< Audio volume value */ 428 uint8_t i2cHandle[WM8962_I2C_HANDLER_SIZE]; /*!< i2c handle */ 429 } wm8962_handle_t; 430 /******************************************************************************* 431 * API 432 ******************************************************************************/ 433 #if defined(__cplusplus) 434 extern "C" { 435 #endif 436 437 /*! 438 * @brief WM8962 initialize function. 439 * 440 * The second parameter is NULL to WM8962 in this version. If users want 441 * to change the settings, they have to use wm8962_write_reg() or wm8962_modify_reg() 442 * to set the register value of WM8962. 443 * Note: If the codec_config is NULL, it would initialize WM8962 using default settings. 444 * The default setting: 445 * codec_config->route = kWM8962_RoutePlaybackandRecord 446 * codec_config->bus = kWM8962_BusI2S 447 * codec_config->master = slave 448 * 449 * @param handle WM8962 handle structure. 450 * @param config WM8962 configuration structure. 451 */ 452 status_t WM8962_Init(wm8962_handle_t *handle, const wm8962_config_t *config); 453 454 /*! 455 * @brief Deinit the WM8962 codec. 456 * 457 * This function close all modules in WM8962 to save power. 458 * 459 * @param handle WM8962 handle structure pointer. 460 */ 461 status_t WM8962_Deinit(wm8962_handle_t *handle); 462 463 /*! 464 * @brief Set audio data route in WM8962. 465 * 466 * This function would set the data route according to route. The route cannot be combined, 467 * as all route would enable different modules. 468 * Note: If a new route is set, the previous route would not work. 469 * 470 * @param handle WM8962 handle structure. 471 * @param route Audio data route in WM8962. 472 */ 473 status_t WM8962_SetDataRoute(wm8962_handle_t *handle, const wm8962_route_config_t *route); 474 475 /*! 476 * @brief Set the audio transfer protocol. 477 * 478 * WM8960 only supports I2S, left justified, right justified, PCM A, PCM B format. 479 * 480 * @param handle WM8960 handle structure. 481 * @param protocol Audio data transfer protocol. 482 */ 483 status_t WM8962_SetProtocol(wm8962_handle_t *handle, wm8962_protocol_t protocol); 484 485 /*! 486 * @brief Set the volume of different modules in WM8962. 487 * 488 * This function would set the volume of WM8962 modules. Uses need to appoint the module. 489 * The function assume that left channel and right channel has the same volume. 490 * 491 * Module:kWM8962_ModuleADC, volume range value: 0 is mute, 1-255 is -97db to 30db 492 * Module:kWM8962_ModuleDAC, volume range value: 0 is mute, 1-255 is -127db to 0db 493 * Module:kWM8962_ModuleHP, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db 494 * Module:kWM8962_ModuleLineIn, volume range value: 0 - 0x3F is -17.25db to 30db 495 * Module:kWM8962_ModuleSpeaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db 496 * 497 * 498 * @param handle WM8962 handle structure. 499 * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. 500 * @param volume Volume value need to be set. 501 */ 502 status_t WM8962_SetModuleVolume(wm8962_handle_t *handle, wm8962_module_t module, uint32_t volume); 503 504 /*! 505 * @brief Get the volume of different modules in WM8962. 506 * 507 * This function gets the volume of WM8962 modules. Uses need to appoint the module. 508 * The function assume that left channel and right channel has the same volume. 509 * 510 * @param handle WM8962 handle structure. 511 * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. 512 * @return Volume value of the module. 513 */ 514 uint32_t WM8962_GetModuleVolume(wm8962_handle_t *handle, wm8962_module_t module); 515 516 /*! 517 * @brief Mute modules in WM8962. 518 * 519 * @param handle WM8962 handle structure. 520 * @param module Modules need to be mute. 521 * @param isEnabled Mute or unmute, 1 represent mute. 522 */ 523 status_t WM8962_SetModuleMute(wm8962_handle_t *handle, wm8962_module_t module, bool isEnabled); 524 525 /*! 526 * @brief Enable/disable expected devices. 527 * 528 * @param handle WM8962 handle structure. 529 * @param module Module expected to enable. 530 * @param isEnabled Enable or disable moudles. 531 */ 532 status_t WM8962_SetModulePower(wm8962_handle_t *handle, wm8962_module_t module, bool isEnabled); 533 534 /*! 535 * @brief Configure the data format of audio data. 536 * 537 * This function would configure the registers about the sample rate, bit depths. 538 * 539 * @param handle WM8962 handle structure pointer. 540 * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. 541 * @param sample_rate Sample rate of audio file running in WM8962. WM8962 now 542 * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. 543 * @param bits Bit depth of audio file (WM8962 only supports 16bit, 20bit, 24bit 544 * and 32 bit in HW). 545 */ 546 status_t WM8962_ConfigDataFormat(wm8962_handle_t *handle, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); 547 548 /*! 549 * @brief Write register to WM8962 using I2C. 550 * 551 * @param handle WM8962 handle structure. 552 * @param reg The register address in WM8962. 553 * @param val Value needs to write into the register. 554 */ 555 status_t WM8962_WriteReg(wm8962_handle_t *handle, uint16_t reg, uint16_t val); 556 557 /*! 558 * @brief Read register from WM8962 using I2C. 559 * 560 * @param handle WM8962 handle structure. 561 * @param reg The register address in WM8962. 562 * @param val Value written to. 563 */ 564 status_t WM8962_ReadReg(wm8962_handle_t *handle, uint16_t reg, uint16_t *val); 565 566 /*! 567 * @brief Modify some bits in the register using I2C. 568 * @param handle WM8962 handle structure. 569 * @param reg The register address in WM8962. 570 * @param mask The mask code for the bits want to write. The bit you want to write should be 0. 571 * @param val Value needs to write into the register. 572 */ 573 status_t WM8962_ModifyReg(wm8962_handle_t *handle, uint16_t reg, uint16_t mask, uint16_t val); 574 575 #if DEBUG_WM8962_REGISTER 576 /*! 577 * @brief Dump all the wm8962 register. 578 579 * @param handle WM8962 handle structure. 580 * @param endAddress The end register address in WM8962. 581 */ 582 void WM8962_ReadAllReg(wm8962_handle_t *handle, uint32_t endAddress); 583 #endif 584 #if defined(__cplusplus) 585 } 586 #endif 587 588 /*! @} */ 589 590 #endif /* _FSL_WM8962_H_ */ 591 592 /******************************************************************************* 593 * API 594 ******************************************************************************/ 595
