1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_WKPU.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_WKPU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_WKPU_H_) /* Check if memory map has not been already included */ 58 #define S32K344_WKPU_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- WKPU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup WKPU_Peripheral_Access_Layer WKPU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** WKPU - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t NSR; /**< NMI Status Flag Register, offset: 0x0 */ 74 uint8_t RESERVED_0[4]; 75 __IO uint32_t NCR; /**< NMI Configuration Register, offset: 0x8 */ 76 uint8_t RESERVED_1[8]; 77 __IO uint32_t WISR; /**< Wakeup/Interrupt Status Flag Register, offset: 0x14 */ 78 __IO uint32_t IRER; /**< Interrupt Request Enable Register, offset: 0x18 */ 79 __IO uint32_t WRER; /**< Wakeup Request Enable Register, offset: 0x1C */ 80 uint8_t RESERVED_2[8]; 81 __IO uint32_t WIREER; /**< Wakeup/Interrupt Rising-Edge Event Enable Register, offset: 0x28 */ 82 __IO uint32_t WIFEER; /**< Wakeup/Interrupt Falling-Edge Event Enable Register, offset: 0x2C */ 83 __IO uint32_t WIFER; /**< Wakeup/Interrupt Filter Enable Register, offset: 0x30 */ 84 uint8_t RESERVED_3[32]; 85 __IO uint32_t WISR_64; /**< Wakeup/Interrupt Status Flag Register, offset: 0x54 */ 86 __IO uint32_t IRER_64; /**< Interrupt Request Enable Register, offset: 0x58 */ 87 __IO uint32_t WRER_64; /**< Wakeup Request Enable Register, offset: 0x5C */ 88 uint8_t RESERVED_4[8]; 89 __IO uint32_t WIREER_64; /**< Wakeup/Interrupt Rising-Edge Event Enable Register, offset: 0x68 */ 90 __IO uint32_t WIFEER_64; /**< Wakeup/Interrupt Falling-Edge Event Enable Register, offset: 0x6C */ 91 __IO uint32_t WIFER_64; /**< Wakeup/Interrupt Filter Enable Register, offset: 0x70 */ 92 } WKPU_Type, *WKPU_MemMapPtr; 93 94 /** Number of instances of the WKPU module. */ 95 #define WKPU_INSTANCE_COUNT (1) 96 97 /* WKPU - Peripheral instance base addresses */ 98 /** Peripheral WKPU base address */ 99 #define IP_WKPU_BASE (0x402B4000u) 100 /** Peripheral WKPU base pointer */ 101 #define IP_WKPU ((WKPU_Type *)IP_WKPU_BASE) 102 /** Array initializer of WKPU peripheral base addresses */ 103 #define IP_WKPU_BASE_ADDRS { IP_WKPU_BASE } 104 /** Array initializer of WKPU peripheral base pointers */ 105 #define IP_WKPU_BASE_PTRS { IP_WKPU } 106 107 /* ---------------------------------------------------------------------------- 108 -- WKPU Register Masks 109 ---------------------------------------------------------------------------- */ 110 111 /*! 112 * @addtogroup WKPU_Register_Masks WKPU Register Masks 113 * @{ 114 */ 115 116 /*! @name NSR - NMI Status Flag Register */ 117 /*! @{ */ 118 119 #define WKPU_NSR_NOVF1_MASK (0x400000U) 120 #define WKPU_NSR_NOVF1_SHIFT (22U) 121 #define WKPU_NSR_NOVF1_WIDTH (1U) 122 #define WKPU_NSR_NOVF1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NSR_NOVF1_SHIFT)) & WKPU_NSR_NOVF1_MASK) 123 124 #define WKPU_NSR_NIF1_MASK (0x800000U) 125 #define WKPU_NSR_NIF1_SHIFT (23U) 126 #define WKPU_NSR_NIF1_WIDTH (1U) 127 #define WKPU_NSR_NIF1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NSR_NIF1_SHIFT)) & WKPU_NSR_NIF1_MASK) 128 129 #define WKPU_NSR_NOVF0_MASK (0x40000000U) 130 #define WKPU_NSR_NOVF0_SHIFT (30U) 131 #define WKPU_NSR_NOVF0_WIDTH (1U) 132 #define WKPU_NSR_NOVF0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NSR_NOVF0_SHIFT)) & WKPU_NSR_NOVF0_MASK) 133 134 #define WKPU_NSR_NIF0_MASK (0x80000000U) 135 #define WKPU_NSR_NIF0_SHIFT (31U) 136 #define WKPU_NSR_NIF0_WIDTH (1U) 137 #define WKPU_NSR_NIF0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NSR_NIF0_SHIFT)) & WKPU_NSR_NIF0_MASK) 138 /*! @} */ 139 140 /*! @name NCR - NMI Configuration Register */ 141 /*! @{ */ 142 143 #define WKPU_NCR_NFE1_MASK (0x10000U) 144 #define WKPU_NCR_NFE1_SHIFT (16U) 145 #define WKPU_NCR_NFE1_WIDTH (1U) 146 #define WKPU_NCR_NFE1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NFE1_SHIFT)) & WKPU_NCR_NFE1_MASK) 147 148 #define WKPU_NCR_NFEE1_MASK (0x20000U) 149 #define WKPU_NCR_NFEE1_SHIFT (17U) 150 #define WKPU_NCR_NFEE1_WIDTH (1U) 151 #define WKPU_NCR_NFEE1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NFEE1_SHIFT)) & WKPU_NCR_NFEE1_MASK) 152 153 #define WKPU_NCR_NREE1_MASK (0x40000U) 154 #define WKPU_NCR_NREE1_SHIFT (18U) 155 #define WKPU_NCR_NREE1_WIDTH (1U) 156 #define WKPU_NCR_NREE1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NREE1_SHIFT)) & WKPU_NCR_NREE1_MASK) 157 158 #define WKPU_NCR_NWRE1_MASK (0x100000U) 159 #define WKPU_NCR_NWRE1_SHIFT (20U) 160 #define WKPU_NCR_NWRE1_WIDTH (1U) 161 #define WKPU_NCR_NWRE1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NWRE1_SHIFT)) & WKPU_NCR_NWRE1_MASK) 162 163 #define WKPU_NCR_NDSS1_MASK (0x600000U) 164 #define WKPU_NCR_NDSS1_SHIFT (21U) 165 #define WKPU_NCR_NDSS1_WIDTH (2U) 166 #define WKPU_NCR_NDSS1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NDSS1_SHIFT)) & WKPU_NCR_NDSS1_MASK) 167 168 #define WKPU_NCR_NLOCK1_MASK (0x800000U) 169 #define WKPU_NCR_NLOCK1_SHIFT (23U) 170 #define WKPU_NCR_NLOCK1_WIDTH (1U) 171 #define WKPU_NCR_NLOCK1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NLOCK1_SHIFT)) & WKPU_NCR_NLOCK1_MASK) 172 173 #define WKPU_NCR_NFE0_MASK (0x1000000U) 174 #define WKPU_NCR_NFE0_SHIFT (24U) 175 #define WKPU_NCR_NFE0_WIDTH (1U) 176 #define WKPU_NCR_NFE0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NFE0_SHIFT)) & WKPU_NCR_NFE0_MASK) 177 178 #define WKPU_NCR_NFEE0_MASK (0x2000000U) 179 #define WKPU_NCR_NFEE0_SHIFT (25U) 180 #define WKPU_NCR_NFEE0_WIDTH (1U) 181 #define WKPU_NCR_NFEE0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NFEE0_SHIFT)) & WKPU_NCR_NFEE0_MASK) 182 183 #define WKPU_NCR_NREE0_MASK (0x4000000U) 184 #define WKPU_NCR_NREE0_SHIFT (26U) 185 #define WKPU_NCR_NREE0_WIDTH (1U) 186 #define WKPU_NCR_NREE0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NREE0_SHIFT)) & WKPU_NCR_NREE0_MASK) 187 188 #define WKPU_NCR_NWRE0_MASK (0x10000000U) 189 #define WKPU_NCR_NWRE0_SHIFT (28U) 190 #define WKPU_NCR_NWRE0_WIDTH (1U) 191 #define WKPU_NCR_NWRE0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NWRE0_SHIFT)) & WKPU_NCR_NWRE0_MASK) 192 193 #define WKPU_NCR_NDSS0_MASK (0x60000000U) 194 #define WKPU_NCR_NDSS0_SHIFT (29U) 195 #define WKPU_NCR_NDSS0_WIDTH (2U) 196 #define WKPU_NCR_NDSS0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NDSS0_SHIFT)) & WKPU_NCR_NDSS0_MASK) 197 198 #define WKPU_NCR_NLOCK0_MASK (0x80000000U) 199 #define WKPU_NCR_NLOCK0_SHIFT (31U) 200 #define WKPU_NCR_NLOCK0_WIDTH (1U) 201 #define WKPU_NCR_NLOCK0(x) (((uint32_t)(((uint32_t)(x)) << WKPU_NCR_NLOCK0_SHIFT)) & WKPU_NCR_NLOCK0_MASK) 202 /*! @} */ 203 204 /*! @name WISR - Wakeup/Interrupt Status Flag Register */ 205 /*! @{ */ 206 207 #define WKPU_WISR_EIF_MASK (0xFFFFFFFFU) 208 #define WKPU_WISR_EIF_SHIFT (0U) 209 #define WKPU_WISR_EIF_WIDTH (32U) 210 #define WKPU_WISR_EIF(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WISR_EIF_SHIFT)) & WKPU_WISR_EIF_MASK) 211 /*! @} */ 212 213 /*! @name IRER - Interrupt Request Enable Register */ 214 /*! @{ */ 215 216 #define WKPU_IRER_EIRE_MASK (0xFFFFFFFFU) 217 #define WKPU_IRER_EIRE_SHIFT (0U) 218 #define WKPU_IRER_EIRE_WIDTH (32U) 219 #define WKPU_IRER_EIRE(x) (((uint32_t)(((uint32_t)(x)) << WKPU_IRER_EIRE_SHIFT)) & WKPU_IRER_EIRE_MASK) 220 /*! @} */ 221 222 /*! @name WRER - Wakeup Request Enable Register */ 223 /*! @{ */ 224 225 #define WKPU_WRER_WRE_MASK (0xFFFFFFFFU) 226 #define WKPU_WRER_WRE_SHIFT (0U) 227 #define WKPU_WRER_WRE_WIDTH (32U) 228 #define WKPU_WRER_WRE(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WRER_WRE_SHIFT)) & WKPU_WRER_WRE_MASK) 229 /*! @} */ 230 231 /*! @name WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ 232 /*! @{ */ 233 234 #define WKPU_WIREER_IREE_MASK (0xFFFFFFFFU) 235 #define WKPU_WIREER_IREE_SHIFT (0U) 236 #define WKPU_WIREER_IREE_WIDTH (32U) 237 #define WKPU_WIREER_IREE(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WIREER_IREE_SHIFT)) & WKPU_WIREER_IREE_MASK) 238 /*! @} */ 239 240 /*! @name WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ 241 /*! @{ */ 242 243 #define WKPU_WIFEER_IFEEx_MASK (0xFFFFFFFFU) 244 #define WKPU_WIFEER_IFEEx_SHIFT (0U) 245 #define WKPU_WIFEER_IFEEx_WIDTH (32U) 246 #define WKPU_WIFEER_IFEEx(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WIFEER_IFEEx_SHIFT)) & WKPU_WIFEER_IFEEx_MASK) 247 /*! @} */ 248 249 /*! @name WIFER - Wakeup/Interrupt Filter Enable Register */ 250 /*! @{ */ 251 252 #define WKPU_WIFER_IFE_MASK (0xFFFFFFFFU) 253 #define WKPU_WIFER_IFE_SHIFT (0U) 254 #define WKPU_WIFER_IFE_WIDTH (32U) 255 #define WKPU_WIFER_IFE(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WIFER_IFE_SHIFT)) & WKPU_WIFER_IFE_MASK) 256 /*! @} */ 257 258 /*! @name WISR_64 - Wakeup/Interrupt Status Flag Register */ 259 /*! @{ */ 260 261 #define WKPU_WISR_64_EIF_1_MASK (0xFFFFFFFFU) 262 #define WKPU_WISR_64_EIF_1_SHIFT (0U) 263 #define WKPU_WISR_64_EIF_1_WIDTH (32U) 264 #define WKPU_WISR_64_EIF_1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WISR_64_EIF_1_SHIFT)) & WKPU_WISR_64_EIF_1_MASK) 265 /*! @} */ 266 267 /*! @name IRER_64 - Interrupt Request Enable Register */ 268 /*! @{ */ 269 270 #define WKPU_IRER_64_EIRE_1_MASK (0xFFFFFFFFU) 271 #define WKPU_IRER_64_EIRE_1_SHIFT (0U) 272 #define WKPU_IRER_64_EIRE_1_WIDTH (32U) 273 #define WKPU_IRER_64_EIRE_1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_IRER_64_EIRE_1_SHIFT)) & WKPU_IRER_64_EIRE_1_MASK) 274 /*! @} */ 275 276 /*! @name WRER_64 - Wakeup Request Enable Register */ 277 /*! @{ */ 278 279 #define WKPU_WRER_64_WRE_1_MASK (0xFFFFFFFFU) 280 #define WKPU_WRER_64_WRE_1_SHIFT (0U) 281 #define WKPU_WRER_64_WRE_1_WIDTH (32U) 282 #define WKPU_WRER_64_WRE_1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WRER_64_WRE_1_SHIFT)) & WKPU_WRER_64_WRE_1_MASK) 283 /*! @} */ 284 285 /*! @name WIREER_64 - Wakeup/Interrupt Rising-Edge Event Enable Register */ 286 /*! @{ */ 287 288 #define WKPU_WIREER_64_IREE_1_MASK (0xFFFFFFFFU) 289 #define WKPU_WIREER_64_IREE_1_SHIFT (0U) 290 #define WKPU_WIREER_64_IREE_1_WIDTH (32U) 291 #define WKPU_WIREER_64_IREE_1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WIREER_64_IREE_1_SHIFT)) & WKPU_WIREER_64_IREE_1_MASK) 292 /*! @} */ 293 294 /*! @name WIFEER_64 - Wakeup/Interrupt Falling-Edge Event Enable Register */ 295 /*! @{ */ 296 297 #define WKPU_WIFEER_64_IFEEx_1_MASK (0xFFFFFFFFU) 298 #define WKPU_WIFEER_64_IFEEx_1_SHIFT (0U) 299 #define WKPU_WIFEER_64_IFEEx_1_WIDTH (32U) 300 #define WKPU_WIFEER_64_IFEEx_1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WIFEER_64_IFEEx_1_SHIFT)) & WKPU_WIFEER_64_IFEEx_1_MASK) 301 /*! @} */ 302 303 /*! @name WIFER_64 - Wakeup/Interrupt Filter Enable Register */ 304 /*! @{ */ 305 306 #define WKPU_WIFER_64_IFE_1_MASK (0xFFFFFFFFU) 307 #define WKPU_WIFER_64_IFE_1_SHIFT (0U) 308 #define WKPU_WIFER_64_IFE_1_WIDTH (32U) 309 #define WKPU_WIFER_64_IFE_1(x) (((uint32_t)(((uint32_t)(x)) << WKPU_WIFER_64_IFE_1_SHIFT)) & WKPU_WIFER_64_IFE_1_MASK) 310 /*! @} */ 311 312 /*! 313 * @} 314 */ /* end of group WKPU_Register_Masks */ 315 316 /*! 317 * @} 318 */ /* end of group WKPU_Peripheral_Access_Layer */ 319 320 #endif /* #if !defined(S32K344_WKPU_H_) */ 321
