1 /***************************************************************************/ /**
2 * @file rsi_ct.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 // Include Files
31
32 #include "rsi_ccp_common.h"
33 #include "base_types.h"
34 #include "rsi_error.h"
35
36 #ifndef RSI_CT_H
37 #define RSI_CT_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #define RSI_CT_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1
44 #define RSI_CT_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1
45
46 #define CLK_ENABLE_SET_3_REG (*((uint32_t volatile *)(0x46000000 + 0x10)))
47 #define M4SS_CT_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x10)))
48
49 #define ENABLE 1
50 #define DISABLE 0
51
52 #define LOW 0
53 #define HIGH 1
54
55 #define INPUT_CNT 4
56 #define OUTPUT_CNT 8
57 #define COUNTERS_CNT 2
58 #define EVENT_CNT 38
59 #define DMA_MODE 1
60
61 //CT Interrupt Flags
62 #define RSI_CT_EVENT_INTR_0_l (1UL << 0) // Counter 0 Interrupt event interrupt flag
63 #define RSI_CT_EVENT_FIFO_0_FULL_l (1UL << 1) // FIFO full signal of Counter 0 interrupt flag
64 #define RSI_CT_EVENT_COUNTER_0_IS_ZERO_l (1UL << 2) // Counter 0 hit zero in active mode interrupt flag
65 #define RSI_CT_EVENT_COUNTER_0_IS_PEAK_l (1UL << 3) // Counter 0 hit peak (MATCH) in active mode interrupt flag
66 #define RSI_CT_EVENT_INTR_1_l (1UL << 16) // Counter 1 Interrupt event interrupt flag
67 #define RSI_CT_EVENT_FIFO_1_FULL_l (1UL << 17) // FIFO full signal of Counter 1 interrupt flag
68 #define RSI_CT_EVENT_COUNTER_1_IS_ZERO_l (1UL << 18) // Counter 1 hit zero in active mode interrupt flag
69 #define RSI_CT_EVENT_COUNTER_1_IS_PEAK_l (1UL << 19) // Counter 1 hit peak (MATCH) in active mode interrupt flag
70
71 #define COUNTER_0 0
72 #define COUNTER_1 1
73 #define COUNTER_0_1 2
74
75 // CT Control Set Register Bits
76 #define COUNTER0_UP (0x1 << 4)
77 #define COUNTER0_DOWN (0x2 << 4)
78 #define COUNTER0_UP_DOWN (0x3 << 4)
79
80 #define COUNTER1_UP (0x1 << 20)
81 #define COUNTER1_DOWN (0x2 << 20)
82 #define COUNTER1_UP_DOWN (0x3 << 20)
83
84 #define COUNTER32_BITMODE (1UL << 0) // 32 bit Counter mode
85 #define SOFTRESET_COUNTER_0 (1UL << 1) // soft reset counter 0
86 #define PERIODIC_ENCOUNTER_0 (1UL << 2) // Periodic/One shot counter 0
87 #define COUNTER0_TRIG (1UL << 3) // trigger Counter 0
88 #define COUNTER0_SYNC_TRIG (1UL << 6) // Sync trigger for counter 0
89 #define BUF_REG0EN (1UL << 7) // Buffer enable for counter 0
90 #define SOFTRESET_COUNTER_1 (1UL << 17) // soft reset counter 1
91 #define PERIODIC_ENCOUNTER_1 (1UL << 18) // Periodic/One shot counter 1
92 #define COUNTER1_TRIG (1UL << 19) // trigger Counter 1
93 #define COUNTER1_SYNC_TRIG (1UL << 22) // Sync trigger for counter 1
94 #define BUF_REG1EN (1UL << 23) // Buffer enable for counter 1
95
96 #define RISE_EDGE_MASK0 (1UL << 0)
97 #define RISE_EDGE_MASK1 (1UL << 1)
98 #define RISE_EDGE_MASK2 (1UL << 2)
99 #define RISE_EDGE_MASK3 (1UL << 3)
100
101 #define FALL_EDGE_MASK0 (1UL << 4)
102 #define FALL_EDGE_MASK1 (1UL << 5)
103 #define FALL_EDGE_MASK2 (1UL << 6)
104 #define FALL_EDGE_MASK3 (1UL << 7)
105
106 #define RFE_EDGE_MASK0 (1UL << 8)
107 #define RFE_EDGE_MASK1 (1UL << 9)
108 #define RFE_EDGE_MASK2 (1UL << 10)
109 #define RFE_EDGE_MASK3 (1UL << 11)
110
111 #define LEVEL_LOW_MASK0 (1UL << 12)
112 #define LEVEL_LOW_MASK1 (1UL << 13)
113 #define LEVEL_LOW_MASK2 (1UL << 14)
114 #define LEVEL_LOW_MASK3 (1UL << 15)
115
116 #define LEVEL_HIGH_MASK0 (1UL << 16)
117 #define LEVEL_HIGH_MASK1 (1UL << 17)
118 #define LEVEL_HIGH_MASK2 (1UL << 18)
119 #define LEVEL_HIGH_MASK3 (1UL << 19)
120
121 // CT example defines
122 #define OUTPUT_OCU_0 (1UL << 0) // Counter 0 output OCU
123 #define OCU_DMA_0 (1UL << 4) // Counter 0 OCU DMA enable
124 #define OCU_8_MODE_0 (1UL << 5) // OCU using 16 bit mode
125 #define OUTPUT_OCU_1 (1UL << 16) // Counter 1output OCU
126 #define OCU_DMA_1 (1UL << 20) // Counter 1 OCU DMA enable
127 #define OCU_8_MODE_1 (1UL << 21) // OCU using 16 bit mode
128 #define MAKE_OUTPUT_0_HIGH_SEL_0 (0x2 << 6)
129 #define MAKE_OUTPUT_0_LOW_SEL_0 (0x3 << 9)
130 #define MAKE_OUTPUT_1_HIGH_SEL_1 (0x3 << 22)
131 #define MAKE_OUTPUT_1_LOW_SEL_1 (0x2 << 25)
132 #define OCU_SYNC_WITH_0 (0x1 << 1)
133 #define OCU_SYNC_WITH_1 (0x1 << 17)
134
135 #define OUTPUT_0_TGL_0_MAX 7 // Counter 0 output OCU
136 #define OUTPUT_0_TGL_1_MAX 7 // Counter 0 OCU DMA enable
137 #define TGL_CNT_0_PEAK 0xFF // OCU using 16 bit mode
138 #define OUTPUT_1_TGL_0_MAX 7 // Counter 0 output OCU
139 #define OUTPUT_1_TGL_1_MAX 7 // Counter 0 OCU DMA enable
140 #define TGL_CNT_1_PEAK 0xFF
141
142 #define MAX_PEAK_VALUE_0 0x1000
143 #define MAX_PEAK_VLAUE_1 0x2000
144
145 #define UDMA_CHNL_0 0
146 #define UDMA_CHNL_1 1
147 #define UDMA_CHNL_2 2
148 #define UDMA_CHNL_3 3
149 #define UDMA_CHNL_4 4
150 #define UDMA_CHNL_5 5
151 #define UDMA_CHNL_6 6
152 #define UDMA_CHNL_7 7
153
154 #define UDMA_CONTROL_TABLE_BASE_CHNL0 0x00000000
155 #define UDMA_CONTROL_TABLE_BASE_CHNL1 0x00000010
156 #define WFG_ON_PERIOD 0xFF
157
158 #define USE_DMA 1
159 #define NO_DMA 0
160
161 #define PERIODIC_EN_COUNTER_0_FRM_REG (1UL << 2)
162 #define PERIODIC_EN_COUNTER_1_FRM_REG (1UL << 18)
163 #define COUNTER_0_TRIG (1UL << 3)
164 #define COUNTER_1_TRIG (1UL << 19)
165 #define COUNTER_0_UP (0x1 << 4)
166 #define COUNTER_1_UP (0x1 << 20)
167
168 #define MAKE_OUTPUT_0_TGL_SEL_1 1
169
170 #define AND_COUNTER0(valid, event) ((event << 0) | (valid << 8))
171 #define AND_COUNTER1(valid, event) ((event << 16) | (valid << 24))
172
173 #define OR_COUNTER0(valid, event) ((event << 0) | (valid << 8))
174 #define OR_COUNTER1(valid, event) ((event << 16) | (valid << 24))
175
176 typedef CT0_Type RSI_CT_T;
177 typedef CT_MUX_REG_Type RSI_CT_MUX_REG_T;
178
179 /**============================================================================
180 * @brief CT Driver Capabilities.
181 ============================================================================**/
182
183 typedef struct {
184 unsigned int NoOfInputs : 3; /*!< Number of Input signals */
185 unsigned int NoOfOutputs : 4; /*!< Number of Output signlas */
186 unsigned int NumOfCounters : 4; /*!< Number of Counters present in CT module */
187 unsigned int NoOfEvents : 6; /*!< Number of Events can be generated by input events */
188 unsigned int DMAIntf : 1; /*!< Supports DMA interface or not */
189 } RSI_CT_CAPABILITIES_T;
190 /****** CT Events ******/
191 #define CT_EVT_0 1
192 #define CT_EVT_1 2
193 #define CT_EVT_2 3
194 #define CT_EVT_3 4
195 #define CT_EVT_4 5
196 #define CT_EVT_5 6
197 #define CT_EVT_6 7
198 #define CT_EVT_7 8
199 #define CT_EVT_8 9
200 #define CT_EVT_9 10
201 #define CT_EVT_10 11
202 #define CT_EVT_11 12
203 #define CT_EVT_12 13
204 #define CT_EVT_13 14
205 #define CT_EVT_14 15
206 #define CT_EVT_15 16
207 #define CT_EVT_16 17
208 #define CT_EVT_17 18
209 #define CT_EVT_18 19
210 #define CT_EVT_19 20
211 #define CT_EVT_20 21
212 #define CT_EVT_21 22
213 #define CT_EVT_22 23
214 #define CT_EVT_23 24
215 #define CT_EVT_24 25
216 #define CT_EVT_25 26
217 #define CT_EVT_26 27
218 #define CT_EVT_27 28
219 #define CT_EVT_28 29
220 #define CT_EVT_29 30
221 #define CT_EVT_30 31
222 #define CT_EVT_31 32
223 #define CT_EVT_32 33
224 #define CT_EVT_33 34
225 #define CT_EVT_34 35
226 #define CT_EVT_35 36
227 #define CT_EVT_36 37
228 #define CT_EVT_37 38
229
230 // CT Callback Flags
231 #define CT_INTR_0_l_CB 0x01 // Callback ID for Counter 0 Interrupt event
232 #define CT_FIFO_0_FULL_l_CB 0x02 // Callback ID for FIFO full signal of Counter 0
233 #define CT_COUNTER_0_IS_ZERO_l_CB 0x03 // Callback ID for Counter 0 hit zero in active mode
234 #define CT_COUNTER_0_IS_PEAK_l_CB 0x04 // Callback ID for Counter 0 hit peak (MATCH) in active mode
235 #define CT_INTR_1_l_CB 0x05 // Callback ID for Counter 1 Interrupt event
236 #define CT_FIFO_1_FULL_l_CB 0x06 // Callback ID for FIFO full signal of Counter 1
237 #define CT_COUNTER_1_IS_ZERO_l_CB 0x07 // Callback ID for Counter 1 hit zero in active mode
238 #define CT_COUNTER_1_IS_PEAK_l_CB 0x08 // Callback ID for Counter 1 hit peak (MATCH) in active mode
239 #define CT_OCU_DMA_EN_COUNTER0 0x09 // OCU DMA call back
240 #define CT_OCU_DMA_EN_COUNTER1 0x0A
241
242 // OCU parameter structure
243 typedef struct OCU_PARAMS {
244 uint16_t CompareVal1_0; /*!< two thresholds for counter 0 */
245 uint16_t CompareVal2_0;
246 uint16_t CompareVal1_1;
247 uint16_t CompareVal2_1;
248 uint16_t CompareNextVal1_0; /*!< two next thresholds for counter 0 */
249 uint16_t CompareNextVal2_0;
250 uint16_t CompareNextVal1_1; // next threshold for counter 1
251 uint16_t CompareNextVal2_1; // next threshold for counter 1
252 uint16_t SyncWith0; // Sync Value
253 uint16_t SyncWith1;
254 } OCU_PARAMS_T;
255
256 // WFG control parameters structure
257 typedef struct WFG_PARAMS {
258 uint32_t output0_tgl0_sel;
259 uint32_t output0_tgl1_sel;
260 uint32_t tgl_cnt0_peak;
261 uint32_t output1_tgl0_sel;
262 uint32_t output1_tgl1_sel;
263 uint32_t tgl_cnt1_peak;
264 } WFG_PARAMS_T;
265
266 // brief MCPWM Callback structure
267 typedef struct {
268 void (*cbFunc)(uint8_t event, uint8_t counterNum); // Call back function pointer
269 } RSI_CT_CALLBACK_T;
270
271 // brief CT handle type
272 typedef void *RSI_CT_HANDLE_T;
273
274 /*===================================================*/
275 /**
276 * @fn void RSI_CT_Config(RSI_CT_T *pCT, boolean_t cfg)
277 * @brief This API is used to set the 32bit/ 16bit coutners
278 * @param[in] pCT : Pointer to the CT instance register area
279 * @param[in] cfg : if cfg = 0 32bit Counter, cfg = 1 16bit counter
280 * @return none
281 */
RSI_CT_Config(RSI_CT_T * pCT,boolean_t cfg)282 STATIC INLINE void RSI_CT_Config(RSI_CT_T *pCT, boolean_t cfg)
283 {
284 // 32bit/16bit Counters
285 if (cfg == 1) {
286 pCT->CT_GEN_CTRL_SET_REG = (1 << 0);
287 } else {
288 pCT->CT_GEN_CTRL_RESET_REG = (1 << 0);
289 }
290 }
291
292 /*===================================================*/
293 /**
294 * @fn void RSI_CT_SetControl(RSI_CT_T *pCT, uint32_t value)
295 * @brief Programs General control register bit fields
296 * @param[in] pCT : Pointer to the CT instance register area
297 * @param[in] value : This parameter can be the logical OR of the below parameters
298 - \ref COUNTER32_BITMODE : sets 32bit mode
299 - \ref SOFTRESET_COUNTER_0 : Resets coutner 0
300 - \ref PERIODIC_ENCOUNTER_0 : sets periodic mode
301 - \ref COUNTER0_TRIG : starts counter 0
302 - \ref COUNTER0_UP_DOWN : Counter 0 direction (0,1,2,3)
303 - \ref COUNTER0_SYNC_TRIG : This enables the counter 0 to run/active when sync is found.
304 - \ref BUF_REG0EN : Buffer will be enabled and in path for Counter 0
305 - \ref SOFTRESET_COUNTER_1 : Resets Counter 1
306 - \ref PERIODIC_ENCOUNTER_1 : sets periodic mode
307 - \ref COUNTER1_TRIG : starts counter 1
308 - \ref COUNTER1_UP_DOWN : Counter 1 direction (0,1,2,3)
309 - \ref COUNTER1_SYNC_TRIG : This enables the counter 1 to run/active when sync is found.
310 - \ref BUF_REG1EN : Buffer will be enabled and in path for counter 1.
311 * @return none
312 */
RSI_CT_SetControl(RSI_CT_T * pCT,uint32_t value)313 STATIC INLINE void RSI_CT_SetControl(RSI_CT_T *pCT, uint32_t value)
314 {
315 // Sets required control bits
316 pCT->CT_GEN_CTRL_SET_REG = value;
317 }
318
319 /*===================================================*/
320 /**
321 * @fn void RSI_CT_ClearControl(RSI_CT_T *pCT, uint32_t value)
322 * @brief This API is used to Reset the required control bits in general control set register
323 * @param[in] pCT : Pointer to the CT instance register area
324 * @param[in] value : This parameter can be the logical OR of the required bit ,fields in CT Reset Control register as below.
325 - \ref COUNTER32_BITMODE : Sets 16bit mode
326 - \ref PERIODIC_ENCOUNTER_0 : Sets Counter_0 will be in single count mode.
327 - \ref COUNTER0_UP_DOWN : counter 0 to run in up/down/up-down/down-up directions (0,1,2,3)
328 - \ref BUF_REG0EN : Buffer will be disabled and in path and in path for Counter 0
329 - \ref PERIODIC_ENCOUNTER_1 : sets Counter 1 will be in single count mode
330 - \ref COUNTER1_UP_DOWN : Counter 1 to run in up/down/up-down/down-up directions(0,1,2,3)
331 - \ref BUF_REG1EN : Buffer will be disabled and in path for counter 1.
332 * @return none
333 */
RSI_CT_ClearControl(RSI_CT_T * pCT,uint32_t value)334 STATIC INLINE void RSI_CT_ClearControl(RSI_CT_T *pCT, uint32_t value)
335 {
336 // Resets required control bits
337 pCT->CT_GEN_CTRL_RESET_REG = value;
338 }
339
340 /*===================================================*/
341 /**
342 * @fn void RSI_CT_StartEventSelect(RSI_CT_T *pCT,uint32_t value)
343 * @brief This API is used to select the input event to start any counter
344 * @param[in] pCT : Pointer to the CT instance register area
345 * @param[in] value : ORed value of Events for counter0 and counter1
346 \n This parameter can be the logical OR of the event number for counter 0 and counter 1
347 \n possible event numbers are 1 to 38 if 0 : No event is selected
348 * @return none
349 */
RSI_CT_StartEventSelect(RSI_CT_T * pCT,uint32_t value)350 STATIC INLINE void RSI_CT_StartEventSelect(RSI_CT_T *pCT, uint32_t value)
351 {
352 pCT->CT_START_COUNTER_EVENT_SEL |= value;
353 }
354
355 /*===================================================*/
356 /**
357 * @fn void RSI_CT_StartEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue)
358 * @brief This API is used to Configure AND/OR event for start counter operation
359 * @param[in] pCT : Pointer to the CT instance register area
360 * @param[in] andValue : This parameter can be the logical OR of the below parameters.
361 - START_COUNTER_0_AND_EVENT : AND expression for AND event in start Counter_0 event,
362 possible values are 0x0 to 0xF.
363 - START_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
364 possible values are 0x0 to 0xF.
365 - START_COUNTER_1_AND_EVENT : AND expression for AND event in start Counter_1 event,
366 possible values are 0x0 to 0xF.
367 - START_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
368 possible values are 0x0 to 0xF.
369 * @param[in] orValue : This parameter can be the logical OR of the below parameters
370 - START_COUNTER_0_OR_EVENT : OR expression for OR event in start Counter_0 event,
371 possible values are 0x0 to 0xF.
372 - START_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
373 possible values are 0x0 to 0xF.
374 - START_COUNTER_1_OR_EVENT : OR expression for OR event in start Counter_1 event,
375 possible values are 0x0 to 0xF.
376 - START_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
377 possible values are 0x0 to 0xF.
378 * @return none
379 */
RSI_CT_StartEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)380 STATIC INLINE void RSI_CT_StartEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
381 {
382 // AND Event configuration for counter start
383 pCT->CT_START_COUNTER_AND_EVENT |= andValue;
384 // OR Event configuration for counter start
385 pCT->CT_START_COUNTER_OR_EVENT |= orValue;
386 }
387
388 /*===================================================*/
389 /**
390 * @fn void RSI_CT_StopEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue)
391 * @brief This API is used to Configure AND/OR event for stop counter operation
392 * @param[in] pCT : Pointer to the CT instance register area
393 * @param[in] andValue : Stop Counter AND Event register value, this parameter can be the logical OR of the
394 - STOP_COUNTER_0_AND_EVENT : AND expression for AND event in stop Counter_0 event,
395 possible values are 0x0 to 0xF,
396 - STOP_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
397 possible values are 0x0 to 0xF
398 - STOP_COUNTER_1_AND_EVENT : AND expression for AND event in stop Counter_1 event,
399 possible values are 0x0 to 0xF,
400 - STOP_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
401 possible values are 0x0 to 0xF
402 * @param[in] orValue : Stop Counter OR Event register value,this parameter can be the logical OR of the
403 - STOP_COUNTER_0_OR_EVENT : OR expression for OR event in stop Counter_0 event,
404 possible values are 0x0 to 0xF,
405 - STOP_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
406 possible values are 0x0 to 0xF
407 - STOP_COUNTER_1_OR_EVENT : OR expression for OR event in stop Counter_1 event,
408 possible values are 0x0 to 0xF,
409 - STOP_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
410 possible values are 0x0 to 0xF
411 * @return none
412 */
RSI_CT_StopEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)413 STATIC INLINE void RSI_CT_StopEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
414 {
415 // AND Event configuration for counter stop
416 pCT->CT_STOP_COUNTER_AND_EVENT |= andValue;
417 // OR Event configuration for counter stop
418 pCT->CT_STOP_COUNTER_OR_EVENT |= orValue;
419 }
420
421 /*===================================================*/
422 /**
423 * @fn void RSI_CT_ContinueEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue)
424 * @brief This API is used to Configure AND/OR event for Continue operation
425 * @param[in] pCT : Pointer to the CT instance register area
426 * @param[in] andValue : Continue Counter AND Event register value,this parameter can be the logical OR of the
427 - CONTINUE_COUNTER_0_AND_EVENT : AND expression for AND event in continue Counter_0 event,
428 possible values are 0x0 to 0xF,
429 - CONTINUE_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
430 possible values are 0x0 to 0xF
431 - CONTINUE_COUNTER_1_AND_EVENT : AND expression for AND event in continue Counter_1 event,
432 possible values are 0x0 to 0xF,
433 - CONTINUE_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
434 possible values are 0x0 to 0xF
435 * @param[in] orValue : Continue Counter OR Event register value,this parameter can be the logical OR of the
436 - CONTINUE_COUNTER_0_OR_EVENT : OR expression for OR event in continue Counter_0 event,
437 possible values are 0x0 to 0xF,
438 - CONTINUE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
439 possible values are 0x0 to 0xF
440 - CONTINUE_COUNTER_1_OR_EVENT : OR expression for OR event in continue Counter_1 event,
441 possible values are 0x0 to 0xF,
442 - CONTINUE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
443 possible values are 0x0 to 0xF
444 * @return none
445 */
RSI_CT_ContinueEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)446 STATIC INLINE void RSI_CT_ContinueEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
447 {
448 // AND Event configuration for counter continue
449 pCT->CT_CONTINUE_COUNTER_AND_EVENT |= andValue;
450 // OR Event configuration for counter continue
451 pCT->CT_CONTINUE_COUNTER_OR_EVENT |= orValue;
452 }
453
454 /*===================================================*/
455 /**
456 * @fn void RSI_CT_HaltEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue)
457 * @brief This API is used to Configure AND/OR event for Halt operation
458 * @param[in] pCT : Pointer to the CT instance register area
459 * @param[in] andValue : Halt Counter AND Event register value,This parameter can be the logical OR of the
460 - HALT_COUNTER_0_AND_EVENT : AND expression for AND event in halt Counter_0 event,
461 possible values are 0x0 to 0xF,
462 - HALT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
463 possible values are 0x0 to 0xF
464 - HALT_COUNTER_1_AND_EVENT : AND expression for AND event in halt Counter_1 event,
465 possible values are 0x0 to 0xF,
466 - HALT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
467 possible values are 0x0 to 0xF
468 * @param[in] orValue : Halt Counter OR Event register value
469 \n This parameter can be the logical OR of the
470 - HALT_COUNTER_0_OR_EVENT : OR expression for OR event in halt Counter_0 event,
471 possible values are 0x0 to 0xF,
472 - HALT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
473 possible values are 0x0 to 0xF
474 - HALT_COUNTER_1_OR_EVENT : OR expression for OR event in halt Counter_1 event,
475 possible values are 0x0 to 0xF,
476 - HALT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
477 possible values are 0x0 to 0xF
478 * @return none
479 */
RSI_CT_HaltEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)480 STATIC INLINE void RSI_CT_HaltEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
481 {
482 // AND Event configuration for counter Halt
483 pCT->CT_HALT_COUNTER_AND_EVENT |= andValue;
484 // OR Event configuration for counter Halt
485 pCT->CT_HALT_COUNTER_OR_EVENT |= orValue;
486 }
487
488 /*===================================================*/
489 /**
490 * @fn void RSI_CT_IncrementEventConfig(RSI_CT_T *pCT,uint32_t andValue, uint32_t orValue)
491 * @brief This API is used to Configure AND/OR event for increment operation
492 * @param[in] pCT : Pointer to the CT instance register area
493 * @param[in] andValue : Increment Counter AND Event register value,this parameter can be the logical OR of the
494 - INCREMENT_COUNTER_0_AND_EVENT : AND expression for AND event in increment Counter_0 event,
495 possible values are 0x0 to 0xF,
496 - INCREMENT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
497 possible values are 0x0 to 0xF
498 - INCREMENT_COUNTER_1_AND_EVENT : AND expression for AND event in increment Counter_1 event,
499 possible values are 0x0 to 0xF,
500 - INCREMENT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
501 possible values are 0x0 to 0xF
502 * @param[in] orValue : Increment Counter OR Event register value,this parameter can be the logical OR of the
503 - INCREMENT_COUNTER_0_OR_EVENT : OR expression for OR event in increment Counter_0 event,
504 possible values are 0x0 to 0xF,
505 - INCREMENT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
506 possible values are 0x0 to 0xF
507 - INCREMENT_COUNTER_1_OR_EVENT : OR expression for OR event in increment Counter_1 event,
508 possible values are 0x0 to 0xF,
509 - INCREMENT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
510 possible values are 0x0 to 0xF,
511 * @return none
512 */
RSI_CT_IncrementEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)513 STATIC INLINE void RSI_CT_IncrementEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
514 {
515 // AND Event configuration for counter Increment
516 pCT->CT_INCREMENT_COUNTER_AND_EVENT |= andValue;
517 // OR Event configuration for counter Increment
518 pCT->CT_INCREMENT_COUNTER_OR_EVENT |= orValue;
519 }
520
521 /*===================================================*/
522 /**
523 * @fn void RSI_CT_CaptureEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue)
524 * @brief This API is used to Configure AND/OR event for capture operation
525 * @param[in] pCT : Pointer to the CT instance register area
526 * @param[in] andValue : Capture Counter AND Event register value,This parameter can be the logical OR of the
527 - CAPTURE_COUNTER_0_AND_EVENT : AND expression for AND event in capture Counter_0 event,
528 possible values are 0x0 to 0xF,
529 - CAPTURE_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
530 possible values are 0x0 to 0xF
531 - CAPTURE_COUNTER_1_AND_EVENT : AND expression for AND event in capture Counter_1 event,
532 possible values are 0x0 to 0xF,
533 - CAPTURE_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
534 possible values are 0x0 to 0xF
535 * @param[in] orValue : Capture Counter OR Event register value,This parameter can be the logical OR of the
536 - CAPTURE_COUNTER_0_OR_EVENT : OR expression for OR event in capture Counter_0 event,
537 possible values are 0x0 to 0xF,
538 - CAPTURE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
539 possible values are 0x0 to 0xF
540 - CAPTURE_COUNTER_1_OR_EVENT : OR expression for OR event in capture Counter_1 event,
541 possible values are 0x0 to 0xF,
542 - CAPTURE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
543 possible values are 0x0 to 0xF
544 * @return none
545 */
RSI_CT_CaptureEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)546 STATIC INLINE void RSI_CT_CaptureEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
547 {
548
549 // AND Event configuration for counter Capture
550 pCT->CT_CAPTURE_COUNTER_AND_EVENT |= andValue;
551 // OR Event configuration for counter Capture
552 pCT->CT_CAPTURE_COUNTER_OR_EVENT |= orValue;
553 }
554
555 /*===================================================*/
556 /**
557 * @fn void RSI_CT_InterruptEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue)
558 * @brief This API is used to Configure AND/OR event for interrupt operation.
559 * @param[in] pCT : Pointer to the CT instance register area
560 * @param[in] andValue : Interrupt Counter AND Event register value,this parameter can be the logical OR of the
561 - INTR_COUNTER_0_AND_EVENT : AND expression for AND event in interrupt Counter_0 event,
562 possible values are 0x0 to 0xF,
563 - INTR_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
564 possible values are 0x0 to 0xF
565 - INTR_COUNTER_1_AND_EVENT : AND expression for AND event in capture Counter_1 event,
566 possible values are 0x0 to 0xF,
567 - INTR_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
568 possible values are 0x0 to 0xF
569 * @param[in] orValue : Capture Counter OR Event register value,this parameter can be the logical OR of the
570 - CAPTURE_COUNTER_0_OR_EVENT : OR expression for OR event in interrupt Counter_0 event,
571 possible values are 0x0 to 0xF,
572 - CAPTURE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
573 possible values are 0x0 to 0xF
574 - CAPTURE_COUNTER_1_OR_EVENT : OR expression for OR event in interrupt Counter_1 event,
575 possible values are 0x0 to 0xF,
576 - CAPTURE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
577 possible values are 0x0 to 0xF
578 * @return none
579 */
RSI_CT_InterruptEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)580 STATIC INLINE void RSI_CT_InterruptEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
581 {
582 // AND Event configuration for counter Interrupt
583 pCT->CT_INTR_AND_EVENT |= andValue;
584 // OR Event configuration for counter Interrupt
585 pCT->CT_INTR_OR_EVENT_REG |= orValue;
586 }
587
588 /*===================================================*/
589 /**
590 * @fn void RSI_CT_OutputEventConfig( RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue)
591 * @brief This API is used to Configure AND/OR event for output operation.
592 * @param[in] pCT Pointer to the CT instance register area
593 * @param[in] andValue : Output Counter AND Event register value,this parameter can be the logical OR of the
594 - OUTPUT_COUNTER_0_AND_EVENT : AND expression for AND event in output Counter_0 event,
595 possible values are 0x0 to 0xF,
596 - OUTPUT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event,
597 possible values are 0x0 to 0xF
598 - OUTPUT_COUNTER_1_AND_EVENT : AND expression for AND event in output Counter_1 event,
599 possible values are 0x0 to 0xF,
600 - OUTPUT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event,
601 possible values are 0x0 to 0xF
602 * @param[in] orValue : Output Counter OR Event register value,this parameter can be the logical OR of the
603 - OUTPUT_COUNTER_0_OR_EVENT : OR expression for OR event in output Counter_0 event,
604 possible values are 0x0 to 0xF,
605 - OUTPUT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event,
606 possible values are 0x0 to 0xF
607 - OUTPUT_COUNTER_1_OR_EVENT : OR expression for OR event in output Counter_1 event,
608 possible values are 0x0 to 0xF,
609 - OUTPUT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event,
610 possible values are 0x0 to 0xF
611 * @return none
612 */
RSI_CT_OutputEventConfig(RSI_CT_T * pCT,uint32_t andValue,uint32_t orValue)613 STATIC INLINE void RSI_CT_OutputEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue)
614 {
615 // AND Event configuration for counter Output
616 pCT->CT_OUTPUT_AND_EVENT_REG |= andValue;
617 // OR Event configuration for counter Output
618 pCT->CT_OUTPUT_OR_EVENT |= orValue;
619 }
620 /*===================================================*/
621 /**
622 * @fn void RSI_CT_StopEventSelect(RSI_CT_T *pCT,uint32_t value)
623 * @brief This API is used to select the input event to stop counter
624 * @param[in] pCT : Pointer to the CT instance register area
625 * @param[in] value : Stop Event select register value,this parameter can be the logical OR of the
626 - STOP_EVENT_SEL_0 :event number for counter 0
627 - STOP_EVENT_SEL_1 :event number for counter 1
628 - possible event numbers are 1 to 38 if 0 : No event is selected
629 * @return none
630 */
RSI_CT_StopEventSelect(RSI_CT_T * pCT,uint32_t value)631 STATIC INLINE void RSI_CT_StopEventSelect(RSI_CT_T *pCT, uint32_t value)
632 {
633 // Event number to stop
634 pCT->CT_STOP_COUNTER_EVENT_SEL |= value;
635 }
636
637 /*===================================================*/
638 /**
639 * @fn void RSI_CT_ContinueEventSelect(RSI_CT_T *pCT,uint32_t value)
640 * @brief Configures event for Continue operation of Counter
641 * @param[in] pCT : Pointer to the CT instance register area
642 * @param[in] value : Continue Event select register value,this parameter can be the logical OR of the
643 - CONTINUE_EVENT_SEL_0 :event number for counter 0
644 - CONTINUE_EVENT_SEL_1 :event number for counter 1
645 - possible event numbers are 1 to 38 if 0 : No event is selected
646 * @return none
647 */
RSI_CT_ContinueEventSelect(RSI_CT_T * pCT,uint32_t value)648 STATIC INLINE void RSI_CT_ContinueEventSelect(RSI_CT_T *pCT, uint32_t value)
649 {
650 // Event number to continue
651 pCT->CT_CONTINUE_COUNTER_EVENT_SEL |= value;
652 }
653
654 /*===================================================*/
655 /**
656 * @fn void RSI_CT_HaltEventSelect(RSI_CT_T *pCT,uint32_t value)
657 * @brief Configures event for HALT operation of Counter
658 * @param[in] pCT : Pointer to the CT instance register area
659 * @param[in] value : Halt Event select register value,this parameter can be the logical OR of the
660 - HALT_EVENT_SEL_0 :event number for counter 0
661 - HALT_EVENT_SEL_1 :event number for counter 1
662 - possible event numbers are 1 to 38 if 0 : No event is selected
663 * @return none
664 */
RSI_CT_HaltEventSelect(RSI_CT_T * pCT,uint32_t value)665 STATIC INLINE void RSI_CT_HaltEventSelect(RSI_CT_T *pCT, uint32_t value)
666 {
667 // Event number to Halt
668 pCT->CT_HALT_COUNTER_EVENT_SEL |= value;
669 }
670
671 /*===================================================*/
672 /**
673 * @fn void RSI_CT_IncrementEventSelect(RSI_CT_T *pCT,uint32_t value)
674 * @brief Configures event for Increment operation of Counter
675 * @param[in] pCT : Pointer to the CT instance register area
676 * @param[in] value : Increment Event select register value,this parameter can be the logical OR of the
677 - INCREMENT_EVENT_SEL_0 :event number for counter 0
678 - INCREMENT_EVENT_SEL_1 :event number for counter 1
679 - possible event numbers are 1 to 38 if 0 : No event is selected
680 * @return none
681 */
RSI_CT_IncrementEventSelect(RSI_CT_T * pCT,uint32_t value)682 STATIC INLINE void RSI_CT_IncrementEventSelect(RSI_CT_T *pCT, uint32_t value)
683 {
684 // Event number to Increment
685 pCT->CT_INCREMENT_COUNTER_EVENT_SEL |= value;
686 }
687
688 /*===================================================*/
689 /**
690 * @fn void RSI_CT_CaptureEventSelect(RSI_CT_T *pCT,uint32_t value)
691 * @brief This API is used to select the input event to capture counter value
692 * @param[in] pCT : Pointer to the CT instance register area
693 * @param[in] value : Capture Event select register value,this parameter can be the logical OR of the
694 - CAPTURE_EVENT_SEL_0 :event number for counter 0
695 - CAPTURE_EVENT_SEL_1 :event number for counter 1
696 - possible event numbers are 1 to 38 if 0 : No event is selected
697 * @return none
698 */
RSI_CT_CaptureEventSelect(RSI_CT_T * pCT,uint32_t value)699 STATIC INLINE void RSI_CT_CaptureEventSelect(RSI_CT_T *pCT, uint32_t value)
700 {
701 // Event number to capture
702 pCT->CT_CAPTURE_COUNTER_EVENT_SEL |= value;
703 }
704
705 /*===================================================*/
706 /**
707 * @fn void RSI_CT_OutputEventSelect(RSI_CT_T *pCT,uint32_t value)
708 * @brief This API is used to select the input event to output counter value
709 * @param[in] pCT : Pointer to the CT instance register area
710 * @param[in] value : Output Event select register value,this parameter can be the logical OR of the
711 - OUTPUT_EVENT_SEL_0 :event number for counter 0
712 - OUTPUT_EVENT_SEL_1 :event number for counter 1
713 - possible event numbers are 1 to 38 if 0 : No event is selected
714 * @return none
715 */
RSI_CT_OutputEventSelect(RSI_CT_T * pCT,uint32_t value)716 STATIC INLINE void RSI_CT_OutputEventSelect(RSI_CT_T *pCT, uint32_t value)
717 {
718 // Event number to output event
719 pCT->CT_OUTPUT_EVENT_SEL |= value;
720 }
721
722 /*===================================================*/
723 /**
724 * @fn void RSI_CT_InterruptEventSelect(RSI_CT_T *pCT,uint32_t value)
725 * @brief This API is used to select the input event for interrupt
726 * @param[in] pCT : Pointer to the CT instance register area
727 * @param[in] value : Output Event select register value,this parameter can be the logical OR of the
728 - INTR_EVENT_SEL_0 :event number for counter 0
729 - INTR_EVENT_SEL_1 :event number for counter 1
730 - possible event numbers are 1 to 38 if 0 : No event is selected
731 * @return none
732 */
RSI_CT_InterruptEventSelect(RSI_CT_T * pCT,uint32_t value)733 STATIC INLINE void RSI_CT_InterruptEventSelect(RSI_CT_T *pCT, uint32_t value)
734 {
735 // Event number to interrupt
736 pCT->CT_INTR_EVENT_SEL |= value;
737 }
738
739 /*===================================================*/
740 /**
741 * @fn void RSI_CT_OutputEventADCTrigger(RSI_CT_MUX_REG_T *pCTmux,uint8_t output1,uint8_t output2)
742 * @brief This API is used to select one of the ADC trigger output
743 * @param[in] pCTmux : Pointer to the CT instance register area
744 * @param[in] output1 : output event for ADC trigger (0 to 31)
745 * @param[in] output2 : output event for ADC trigger (0 to 31)
746 * @return none
747 */
RSI_CT_OutputEventADCTrigger(RSI_CT_MUX_REG_T * pCTmux,uint8_t output1,uint8_t output2)748 STATIC INLINE void RSI_CT_OutputEventADCTrigger(RSI_CT_MUX_REG_T *pCTmux, uint8_t output1, uint8_t output2)
749 {
750 // Sets the output pin number for ADC
751 pCTmux->CT_OUTPUT_EVENT1_ADC_SEL_b.OUTPUT_EVENT_ADC_SEL = (unsigned int)(output1 & 0x0F);
752 // Sets the output pin number for ADC
753 pCTmux->CT_OUTPUT_EVENT2_ADC_SEL_b.OUTPUT_EVENT_ADC_SEL = (unsigned int)(output2 & 0x0F);
754 }
755
756 /*===================================================*/
757 /**
758 * @fn void RSI_CT_SetCount(RSI_CT_T *pCT, uint32_t count)
759 * @brief Sets the Counter Initial value.
760 * @param[in] pCT : Pointer to the CT instance register area
761 * @param[in] count : 32 bit Counter initial value,this parameter can be the logical OR of the
762 - \ref COUNTER_0 : Counter 0 load value ( 0x0 to 0xFFFF)
763 - \ref COUNTER_1 : Counter 1 load value ( 0x0 to 0xFFFF)
764 - possible values are 0x0 to 0xFFFFFFFF
765 * @return none
766 */
RSI_CT_SetCount(RSI_CT_T * pCT,uint32_t count)767 STATIC INLINE void RSI_CT_SetCount(RSI_CT_T *pCT, uint32_t count)
768 {
769 // Sets the Coutner start value
770 pCT->CT_COUNTER_REG = count;
771 }
772
773 /*===================================================*/
774 /**
775 * @fn void RSI_CT_OCUConfigSet(RSI_CT_T *pCT, uint32_t value)
776 * @brief This API is used to set OCU control parameters
777 * @param[in] pCT : Pointer to the CT instance register area
778 * @param[in] value : OCU control register value,this parameter can be the logical OR of the below parameters
779 - OUTPUT_IS_OCU_0 : sets Counter 0 output in OCU mode
780 - SYNC_WITH_0 : Indicates whether the other channel is in sync with this counter(0,1,2,3)
781 - OCU_DMA_MODE_0 : OCU DMA mode is active or not for counter-0
782 - OCU_8_16_MODE_0 : 16 bits or only 8-bits of the counter-0 are used in OCU mode
783 - OUTPUT_IS_OCU_1 : sets Counter 1 output in OCU mode
784 - SYNC_WITH_1 : Indicates whether the other channel is in sync with this counter(0,1,2,3)
785 - OCU_DMA_MODE_1 : OCU DMA mode is active or not for counter-1
786 - OCU_8_16_MODE_1 : 16 bits or only 8-bits of the counter-1 are used in OCU mode
787 * @return none
788 */
RSI_CT_OCUConfigSet(RSI_CT_T * pCT,uint32_t value)789 STATIC INLINE void RSI_CT_OCUConfigSet(RSI_CT_T *pCT, uint32_t value)
790 {
791 // OCU control parameters
792 pCT->CT_OCU_CTRL_REG |= value;
793 }
794
795 /*===================================================*/
796 /**
797 * @fn void RSI_CT_OCUConfigReset(RSI_CT_T *pCT, uint32_t value)
798 * @brief This API is used to set OCU control parameters
799 * @param[in] pCT : Pointer to the CT instance register area
800 * @param[in] value : OCU control register value,this parameter can be the logical OR required bit.
801 * @return none
802 */
RSI_CT_OCUConfigReset(RSI_CT_T * pCT,uint32_t value)803 STATIC INLINE void RSI_CT_OCUConfigReset(RSI_CT_T *pCT, uint32_t value)
804 {
805 // OCU control parameters
806 pCT->CT_OCU_CTRL_REG &= ~value;
807 }
808
809 /*===================================================*/
810 /**
811 * @fn void RSI_CT_InterruptEnable(RSI_CT_T *pCT, uint32_t unmaskFlags)
812 * @brief Enable the interrupts in State Configurable Timer.
813 * @param[in] pCT : Pointer to the CT instance register area
814 * @param[in] unmaskFlags : CT Interrupt unmask register value,this parameter can be the logical OR of the
815 - INTR_0_l : interrupt event flag for counter 0
816 - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0
817 - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0
818 - INTR_1_L : interrupt event flag for counter 1
819 - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1
820 - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1
821 * @return none
822 */
RSI_CT_InterruptEnable(RSI_CT_T * pCT,uint32_t unmaskFlags)823 STATIC INLINE void RSI_CT_InterruptEnable(RSI_CT_T *pCT, uint32_t unmaskFlags)
824 {
825 // multi channel VIC enable
826 M4SS_CT_INTR_SEL = 0xFFFFFFFF;
827
828 // unmasks required interrupt flags
829 pCT->CT_INTER_UNMASK = unmaskFlags;
830 }
831
832 /*===================================================*/
833 /**
834 * @fn void RSI_CT_InterruptDisable(RSI_CT_T *pCT, uint32_t maskFlags)
835 * @brief Disable the interrupts in State Configurable Timer
836 * @param[in] pCT : Pointer to the CT instance register area
837 * @param[in] maskFlags : CT Interrupt mask register value,this parameter can be the logical OR of the
838 - INTR_0_l : interrupt event flag for counter 0
839 - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0
840 - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0
841 - INTR_1_L : interrupt event flag for counter 1
842 - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1
843 - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1
844 * @return none
845 */
RSI_CT_InterruptDisable(RSI_CT_T * pCT,uint32_t maskFlags)846 STATIC INLINE void RSI_CT_InterruptDisable(RSI_CT_T *pCT, uint32_t maskFlags)
847 {
848 // unmasks required interrupt flags
849 pCT->CT_INTR_MASK = maskFlags;
850 }
851
852 /*===================================================*/
853 /**
854 * @fn void RSI_CT_InterruptClear(RSI_CT_T *pCT,uint32_t clr_flags)
855 * @brief Clear the specified interrupt flag in State Configurable Timer
856 * @param[in] pCT : Pointer to the CT instance register area
857 * @param[in] clr_flags : CT Interrupt Ack register value,this parameter can be the logical OR of the
858 - INTR_0_l : interrupt event flag for counter 0
859 - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0
860 - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0
861 - INTR_1_L : interrupt event flag for counter 1
862 - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1
863 - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1
864 * @return none
865 */
RSI_CT_InterruptClear(RSI_CT_T * pCT,uint32_t clrFlags)866 STATIC INLINE void RSI_CT_InterruptClear(RSI_CT_T *pCT, uint32_t clrFlags)
867 {
868 // Clears required interrupt flags
869 pCT->CT_INTR_ACK = clrFlags;
870 }
871
872 /*===================================================*/
873 /**
874 * @fn uint32_t RSI_CT_GetInterruptStatus(const RSI_CT_T *pCT)
875 * @brief Clear the specified interrupt flag in State Configurable Timer
876 * @param[in] pCT : Pointer to the CT instance register area
877 * @return CT Interrupt status value
878 */
RSI_CT_GetInterruptStatus(const RSI_CT_T * pCT)879 STATIC INLINE uint32_t RSI_CT_GetInterruptStatus(const RSI_CT_T *pCT)
880 {
881 return (pCT->CT_INTR_STS);
882 }
883
884 /*===================================================*/
885 /**
886 * @fn void RSI_CT_EdgeLevelEventControl(const RSI_CT_T *pCT,uint32_t value)
887 * @brief This API is used to control the input event generation to CT
888 * @param[in] pSCT : Pointer to the SCT instance register area
889 * @param[in] value : Mask value
890 * @return none
891 */
RSI_CT_EdgeLevelEventControl(const RSI_CT_T * pCT,uint32_t value)892 STATIC INLINE void RSI_CT_EdgeLevelEventControl(const RSI_CT_T *pCT, uint32_t value)
893 {
894 //pCT ->RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG = value;
895 (void)pCT;
896 (void)value;
897 }
898
899 /*===================================================*/
900 /**
901 * @fn void RSI_CT_SetTimerMuxSelect( RSI_CT_MUX_REG_T *pCTMux,uint8_t timerIns )
902 * @brief To Select Timer using mux.
903 * @param[in] pCTMux : Pointer to the CT Mux instance register area
904 * @param[in] timerIns : If 0 - Timer0 instance,if 1 - Timer1 instance
905 * @return none
906 */
RSI_CT_SetTimerMuxSelect(RSI_CT_MUX_REG_T * pCTMux,uint8_t timerIns)907 STATIC INLINE void RSI_CT_SetTimerMuxSelect(RSI_CT_MUX_REG_T *pCTMux, uint8_t timerIns)
908 {
909 pCTMux->CT_MUX_SEL_0_REG = timerIns;
910 pCTMux->CT_MUX_SEL_1_REG = timerIns;
911 }
912
913 /*===================================================*/
914 /**
915 * @fn void RSI_CT_ResumeHaltEvent(RSI_CT_T *pCT,boolean_t counterNum)
916 * @brief To Resume the HALT operation of counter with I/O events
917 * @param[in] pCT : Pointer to the CT instance register area
918 * @param[in] counterNum : Counter 0/1
919 * @return none
920 */
RSI_CT_ResumeHaltEvent(RSI_CT_T * pCT,boolean_t counterNum)921 STATIC INLINE void RSI_CT_ResumeHaltEvent(RSI_CT_T *pCT, boolean_t counterNum)
922 {
923 if (counterNum) {
924 pCT->CT_HALT_COUNTER_EVENT_SEL_b.RESUME_FROM_HALT_COUNTER_1 = 0x1;
925 } else {
926 pCT->CT_HALT_COUNTER_EVENT_SEL_b.RESUME_FROM_HALT_COUNTER_0 = 0x1;
927 }
928 }
929
930 /*===================================================*/
931 /**
932 * @fn rsi_error_t RSI_CT_PeripheralReset(RSI_CT_T *pCT,boolean_t counterNum)
933 * @brief This API is used to Reset any counter.
934 * @param[in] pCT : Pointer to the CT instance register area
935 * @param[in] counterNum : Counter 0/1
936 * @return none
937 */
RSI_CT_PeripheralReset(RSI_CT_T * pCT,boolean_t counterNum)938 STATIC INLINE void RSI_CT_PeripheralReset(RSI_CT_T *pCT, boolean_t counterNum)
939 {
940 if (counterNum) {
941 // Counter 1 reset
942 pCT->CT_GEN_CTRL_SET_REG = (1 << 17);
943 } else {
944 // Counter 0 reset
945 pCT->CT_GEN_CTRL_SET_REG = (1 << 1);
946 }
947 }
948
949 /*===================================================*/
950 /**
951 * @fn rsi_error_t RSI_CT_StartSoftwareTrig(RSI_CT_T *pCT,boolean_t counterNum)
952 * @brief Starts the Counter form software register
953 * @param[in] pCT : Pointer to the CT instance register area
954 * @param[in] counterNum : Coutner 0/1
955 * @return none
956 */
RSI_CT_StartSoftwareTrig(RSI_CT_T * pCT,boolean_t counterNum)957 STATIC INLINE void RSI_CT_StartSoftwareTrig(RSI_CT_T *pCT, boolean_t counterNum)
958 {
959 // starts the required counter */
960 if (counterNum) {
961 pCT->CT_GEN_CTRL_SET_REG = (1 << 19);
962 } else {
963 pCT->CT_GEN_CTRL_SET_REG = (1 << 3);
964 }
965 }
966
967 /*===================================================*/
968 /**
969 * @fn rsi_error_t RSI_CT_OCUModeSet(RSI_CT_T *pCT, boolean_t counterNum)
970 * @brief OCU mode configuration setting
971 * @param[in] pCT : Pointer to the CT instance register area
972 * @param[in] counterNum : Coutner 0/1
973 * @return none
974 */
RSI_CT_OCUModeSet(RSI_CT_T * pCT,boolean_t counterNum)975 STATIC INLINE void RSI_CT_OCUModeSet(RSI_CT_T *pCT, boolean_t counterNum)
976 {
977 if (counterNum) {
978 // set the output in OCU mode for counter 1
979 pCT->CT_OCU_CTRL_REG_b.OUTPUT_1_IS_OCU = 1;
980 } else {
981 // set the output in OCU mode for counter 0
982 pCT->CT_OCU_CTRL_REG_b.OUTPUT_IS_OCU_0 = 1;
983 }
984 }
985
986 /*===================================================*/
987 /**
988 * @fn void RSI_CT_SetMatchCount(RSI_CT_T *pCT, uint32_t value,boolean_t counterMode, boolean_t counterNum)
989 * @brief Sets the Match load value for counter 0 and counter 1
990 * @param[in] pCT : Pointer to the SCT instance register area
991 * @param[in] value : Match register or match buffer register value,this parameter
992 \n can be the logical OR of the
993 - COUNTER_0_MATCH : Counter 0 match value ( 0x0 to 0xFFFF)
994 - COUNTER_1_MATCH : Counter 1 match value ( 0x0 to 0xFFFF)
995 * @param[in] counterMode : counterMode 0/1
996 * @param[in] counterNum : Counter 0/1
997 * @return none
998 */
RSI_CT_SetMatchCount(RSI_CT_T * pCT,uint32_t value,boolean_t counterMode,boolean_t counterNum)999 STATIC INLINE void RSI_CT_SetMatchCount(RSI_CT_T *pCT, uint32_t value, boolean_t counterMode, boolean_t counterNum)
1000 {
1001 if (counterMode == 0) {
1002 if (counterNum) {
1003 pCT->CT_MATCH_REG_b.COUNTER_1_MATCH = (uint16_t)value;
1004 } else {
1005 pCT->CT_MATCH_REG_b.COUNTER_0_MATCH = (uint16_t)value;
1006 }
1007 } else {
1008 pCT->CT_MATCH_REG = (uint16_t)value;
1009 }
1010 }
1011
1012 /*===================================================*/
1013 /**
1014 * @fn uint16_t RSI_CT_CaptureRead(const RSI_CT_T *pCT, boolean_t counterNum)
1015 * @brief Gets the captured counter value
1016 * @param[in] pCT : Pointer to the CT instance register area
1017 * @param[in] counterNum : Counter 0/1
1018 * @return Return counter value at the time of capture event occurs
1019 */
RSI_CT_CaptureRead(const RSI_CT_T * pCT,boolean_t counterNum)1020 STATIC INLINE uint16_t RSI_CT_CaptureRead(const RSI_CT_T *pCT, boolean_t counterNum)
1021 {
1022 if (counterNum) {
1023 return (pCT->CT_CAPTURE_REG_b.COUNTER_1_CAPTURE);
1024 } else {
1025 return (pCT->CT_CAPTURE_REG_b.COUNTER_0_CAPTURE);
1026 }
1027 }
1028
1029 /*===================================================*/
1030 /**
1031 * @fn uint32_t RSI_CT_GetCounter(const RSI_CT_T *pCT,boolean_t counterNum,boolean_t mode )
1032 * @brief Gets the captured counter value
1033 * @param[in] pCT : Pointer to the CT instance register area
1034 * @param[in] counterNum : Counter 0/1
1035 * @param[in] mode : mode 0/1
1036 * @return Return the counter value
1037 */
RSI_CT_GetCounter(const RSI_CT_T * pCT,boolean_t counterNum,boolean_t mode)1038 STATIC INLINE uint32_t RSI_CT_GetCounter(const RSI_CT_T *pCT, boolean_t counterNum, boolean_t mode)
1039 {
1040 if (mode) {
1041 return (pCT->CT_COUNTER_REG);
1042 } else {
1043 if (counterNum) {
1044 return (pCT->CT_COUNTER_REG_b.COUNTER1);
1045 } else {
1046 return (pCT->CT_COUNTER_REG_b.COUNTER0);
1047 }
1048 }
1049 }
1050
1051 /*===================================================*/
1052 /**
1053 * @fn void RSI_CT_SetCounerSync( RSI_CT_T *pCT, uint8_t syncCounter,boolean_t counterNum)
1054 * @brief Sets the captured counter value.
1055 * @param[in] pCT : Pointer to the CT instance register area
1056 * @param[in] syncCounter : set the counter number to be in sync
1057 * @param[in] counterNum : Counter 0/1
1058 * @return none
1059 */
RSI_CT_SetCounerSync(RSI_CT_T * pCT,uint8_t syncCounter,boolean_t counterNum)1060 STATIC INLINE void RSI_CT_SetCounerSync(RSI_CT_T *pCT, uint8_t syncCounter, boolean_t counterNum)
1061 {
1062 if (counterNum) {
1063 pCT->CT_OCU_CTRL_REG_b.SYNC_WITH_1 = (unsigned int)(syncCounter & 0x07);
1064 } else {
1065 pCT->CT_OCU_CTRL_REG_b.SYNC_WITH_0 = (unsigned int)(syncCounter & 0x07);
1066 }
1067 }
1068
1069 // CT FUNCTION PROTOTYPES
1070 void RSI_CT_Init(void);
1071 void ct_ocu_high_Low_toggle_select(RSI_CT_T *pCT, boolean_t lowHigh, boolean_t counterNum, uint8_t outputSel);
1072
1073 rsi_error_t ct_ocu_control(RSI_CT_T *pCT,
1074 boolean_t counterNum,
1075 boolean_t dmaEn,
1076 OCU_PARAMS_T *pOCUparams,
1077 RSI_CT_CALLBACK_T *pCB);
1078
1079 rsi_error_t ct_wfg_control_config(RSI_CT_T *pCT, WFG_PARAMS_T ctrlReg);
1080
1081 rsi_error_t ct_wfg_comapre_value_set(RSI_CT_T *pCT, boolean_t counterNum, OCU_PARAMS_T *pOCUparams);
1082
1083 #ifdef __cplusplus
1084 }
1085 #endif
1086
1087 #endif // RSI_CT_H
1088
