1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include "soc/clk_tree_defs.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 typedef enum { 16 WDT_RWDT = 0, /*!< RTC Watchdog Timer (RWDT) */ 17 WDT_MWDT0, /*!< Main System Watchdog Timer (MWDT) of Timer Group 0 */ 18 WDT_MWDT1, /*!< Main System Watchdog Timer (MWDT) of Timer Group 1 */ 19 } wdt_inst_t; 20 21 /** 22 * @brief Stages of a Watchdog Timer. A WDT has 4 stages. 23 */ 24 typedef enum { 25 WDT_STAGE0 = 0, /*!< Stage 0 */ 26 WDT_STAGE1 = 1, /*!< Stage 1 */ 27 WDT_STAGE2 = 2, /*!< Stage 2 */ 28 WDT_STAGE3 = 3 /*!< Stage 3 */ 29 } wdt_stage_t; 30 31 /** 32 * @brief Behavior of the WDT stage if it times out 33 * 34 * @note These enum values should be compatible with the corresponding register 35 * field values. 36 */ 37 typedef enum { 38 WDT_STAGE_ACTION_OFF = 0, /*!< Disabled. This stage will have no effects on the system. */ 39 WDT_STAGE_ACTION_INT = 1, /*!< Trigger an interrupt when the stage expires. */ 40 WDT_STAGE_ACTION_RESET_CPU = 2, /*!< Reset a CPU core when the stage expires. */ 41 WDT_STAGE_ACTION_RESET_SYSTEM = 3, /*!< Reset the main system when the stage expires. This includes the CPU and all peripherals. The RTC is an exception and will not be reset. */ 42 WDT_STAGE_ACTION_RESET_RTC = 4, /*!< Reset the main system and the RTC when the stage expires. ONLY AVAILABLE FOR RWDT */ 43 } wdt_stage_action_t; 44 45 /** 46 * @brief Length of CPU or System Reset signals 47 * 48 * @note These enum values should be compatible with the corresponding register 49 * field values. 50 */ 51 typedef enum { 52 WDT_RESET_SIG_LENGTH_100ns = 0, /*!< 100 ns */ 53 WDT_RESET_SIG_LENGTH_200ns = 1, /*!< 200 ns */ 54 WDT_RESET_SIG_LENGTH_300ns = 2, /*!< 300 ns */ 55 WDT_RESET_SIG_LENGTH_400ns = 3, /*!< 400 ns */ 56 WDT_RESET_SIG_LENGTH_500ns = 4, /*!< 500 ns */ 57 WDT_RESET_SIG_LENGTH_800ns = 5, /*!< 800 ns */ 58 WDT_RESET_SIG_LENGTH_1_6us = 6, /*!< 1.6 us */ 59 WDT_RESET_SIG_LENGTH_3_2us = 7 /*!< 3.2 us */ 60 } wdt_reset_sig_length_t; 61 62 63 typedef soc_periph_mwdt_clk_src_t mwdt_clock_source_t; 64 65 #ifdef __cplusplus 66 } 67 #endif 68
