1 /* 2 * Copyright (c) 2020 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_ 7 #define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_ 8 9 #define VTD_INT_SHV BIT(3) 10 #define VTD_INT_FORMAT BIT(4) 11 12 /* We don't care about int_idx[15], since the size is fixed to 256, 13 * it's always 0 14 */ 15 #define VTD_MSI_MAP(int_idx, shv) \ 16 ((0x0FEE00000U) | (int_idx << 5) | shv | VTD_INT_FORMAT) 17 18 /* Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts */ 19 union vtd_irte { 20 struct irte_parts { 21 uint64_t low; 22 uint64_t high; 23 } parts; 24 25 struct irte_bits { 26 uint64_t present : 1; 27 uint64_t fpd : 1; 28 uint64_t dst_mode : 1; 29 uint64_t redirection_hint : 1; 30 uint64_t trigger_mode : 1; 31 uint64_t delivery_mode : 3; 32 uint64_t available : 4; 33 uint64_t _reserved_0 : 3; 34 uint64_t irte_mode : 1; 35 uint64_t vector : 8; 36 uint64_t _reserved_1 : 8; 37 uint64_t dst_id : 32; 38 uint64_t src_id : 16; 39 uint64_t src_id_qualifier : 2; 40 uint64_t src_validation_type : 2; 41 uint64_t _reserved : 44; 42 } bits __packed; 43 }; 44 45 /* The table must be 4KB aligned, which is exactly 256 entries. 46 * And since we allow only 256 entries as a maximum: let's align to it. 47 */ 48 #define IRTE_NUM 256 49 #define IRTA_SIZE 7 /* size = 2^(X+1) where IRTA_SIZE is X 2^8 = 256 */ 50 51 #define QI_NUM 256 /* Which is the minimal number we can set for the queue */ 52 #define QI_SIZE 0 /* size = 2^(X+8) where QI_SIZE is X: 2^8 = 256 */ 53 #define QI_WIDTH 128 54 55 struct qi_descriptor { 56 uint64_t low; 57 uint64_t high; 58 }; 59 60 #define QI_TYPE_ICC 0x1UL 61 62 union qi_icc_descriptor { 63 struct qi_descriptor desc; 64 65 struct icc_bits { 66 uint64_t type : 4; 67 uint64_t granularity : 2; 68 uint64_t _reserved_0 : 3; 69 uint64_t zero : 3; 70 uint64_t _reserved_1 : 4; 71 uint64_t domain_id : 16; 72 uint64_t source_id : 16; 73 uint64_t function_mask : 2; 74 uint64_t _reserved_2 : 14; 75 uint64_t reserved; 76 } icc __packed; 77 }; 78 79 #define QI_TYPE_IEC 0x4UL 80 81 union qi_iec_descriptor { 82 struct qi_descriptor desc; 83 84 struct iec_bits { 85 uint64_t type : 4; 86 uint64_t granularity : 1; 87 uint64_t _reserved_0 : 4; 88 uint64_t zero : 3; 89 uint64_t _reserved_1 : 15; 90 uint64_t index_mask : 5; 91 uint64_t interrupt_index: 16; 92 uint64_t _reserved_2 : 16; 93 uint64_t reserved; 94 } iec __packed; 95 }; 96 97 #define QI_TYPE_WAIT 0x5UL 98 99 union qi_wait_descriptor { 100 struct qi_descriptor desc; 101 102 struct wait_bits { 103 uint64_t type : 4; 104 uint64_t interrupt_flag : 1; 105 uint64_t status_write : 1; 106 uint64_t fence_flag : 1; 107 uint64_t page_req_drain : 1; 108 uint64_t _reserved_0 : 1; 109 uint64_t zero : 3; 110 uint64_t _reserved_1 : 20; 111 uint64_t status_data : 32; 112 uint64_t reserved : 2; 113 uint64_t address : 62; 114 } wait __packed; 115 }; 116 117 #define QI_WAIT_STATUS_INCOMPLETE 0x0UL 118 #define QI_WAIT_STATUS_COMPLETE 0x1UL 119 120 /* Arbitrary wait counter limit */ 121 #define QI_WAIT_COUNT_LIMIT 100 122 123 struct vtd_ictl_data { 124 DEVICE_MMIO_RAM; 125 union vtd_irte irte[IRTE_NUM] __aligned(0x1000); 126 struct qi_descriptor qi[QI_NUM] __aligned(0x1000); 127 int irqs[IRTE_NUM]; 128 int vectors[IRTE_NUM]; 129 bool msi[IRTE_NUM]; 130 int irte_num_used; 131 unsigned int fault_irq; 132 uintptr_t fault_record_reg; 133 uint16_t fault_record_num; 134 uint16_t qi_tail; 135 uint8_t fault_vector; 136 bool pwc; 137 }; 138 139 struct vtd_ictl_cfg { 140 DEVICE_MMIO_ROM; 141 }; 142 143 #endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_ */ 144