1 /* 2 * Copyright (c) 2017, STMicroelectronics - All Rights Reserved 3 * 4 * This file is part of VL53L1 Core and is dual licensed, 5 * either 'STMicroelectronics 6 * Proprietary license' 7 * or 'BSD 3-clause "New" or "Revised" License' , at your option. 8 * 9 ******************************************************************************** 10 * 11 * 'STMicroelectronics Proprietary license' 12 * 13 ******************************************************************************** 14 * 15 * License terms: STMicroelectronics Proprietary in accordance with licensing 16 * terms at www.st.com/sla0081 17 * 18 * STMicroelectronics confidential 19 * Reproduction and Communication of this document is strictly prohibited unless 20 * specifically authorized in writing by STMicroelectronics. 21 * 22 * 23 ******************************************************************************** 24 * 25 * Alternatively, VL53L1 Core may be distributed under the terms of 26 * 'BSD 3-clause "New" or "Revised" License', in which case the following 27 * provisions apply instead of the ones mentioned above : 28 * 29 ******************************************************************************** 30 * 31 * License terms: BSD 3-clause "New" or "Revised" License. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions are met: 35 * 36 * 1. Redistributions of source code must retain the above copyright notice, this 37 * list of conditions and the following disclaimer. 38 * 39 * 2. Redistributions in binary form must reproduce the above copyright notice, 40 * this list of conditions and the following disclaimer in the documentation 41 * and/or other materials provided with the distribution. 42 * 43 * 3. Neither the name of the copyright holder nor the names of its contributors 44 * may be used to endorse or promote products derived from this software 45 * without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 48 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 50 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 54 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 55 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 * 59 ******************************************************************************** 60 * 61 */ 62 63 /** 64 * @file vl53l1_register_structs.h 65 * @brief VL53L1 Register Structure definitions 66 */ 67 68 #ifndef _VL53L1_REGISTER_STRUCTS_H_ 69 #define _VL53L1_REGISTER_STRUCTS_H_ 70 71 #include "vl53l1_types.h" 72 #include "vl53l1_register_map.h" 73 74 #define VL53L1_STATIC_NVM_MANAGED_I2C_INDEX VL53L1_I2C_SLAVE__DEVICE_ADDRESS 75 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_INDEX VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 76 #define VL53L1_STATIC_CONFIG_I2C_INDEX VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 77 #define VL53L1_GENERAL_CONFIG_I2C_INDEX VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 78 #define VL53L1_TIMING_CONFIG_I2C_INDEX VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI 79 #define VL53L1_DYNAMIC_CONFIG_I2C_INDEX VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0 80 #define VL53L1_SYSTEM_CONTROL_I2C_INDEX VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE 81 #define VL53L1_SYSTEM_RESULTS_I2C_INDEX VL53L1_RESULT__INTERRUPT_STATUS 82 #define VL53L1_CORE_RESULTS_I2C_INDEX VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 83 #define VL53L1_DEBUG_RESULTS_I2C_INDEX VL53L1_PHASECAL_RESULT__REFERENCE_PHASE 84 #define VL53L1_NVM_COPY_DATA_I2C_INDEX VL53L1_IDENTIFICATION__MODEL_ID 85 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS 86 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_INDEX VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 87 #define VL53L1_PATCH_DEBUG_I2C_INDEX VL53L1_RESULT__DEBUG_STATUS 88 #define VL53L1_GPH_GENERAL_CONFIG_I2C_INDEX VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH 89 #define VL53L1_GPH_STATIC_CONFIG_I2C_INDEX VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL 90 #define VL53L1_GPH_TIMING_CONFIG_I2C_INDEX VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 91 #define VL53L1_FW_INTERNAL_I2C_INDEX VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 92 #define VL53L1_PATCH_RESULTS_I2C_INDEX VL53L1_DSS_CALC__ROI_CTRL 93 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_INDEX VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START 94 #define VL53L1_SHADOW_CORE_RESULTS_I2C_INDEX VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 95 96 #define VL53L1_STATIC_NVM_MANAGED_I2C_SIZE_BYTES 11 97 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES 23 98 #define VL53L1_STATIC_CONFIG_I2C_SIZE_BYTES 32 99 #define VL53L1_GENERAL_CONFIG_I2C_SIZE_BYTES 22 100 #define VL53L1_TIMING_CONFIG_I2C_SIZE_BYTES 23 101 #define VL53L1_DYNAMIC_CONFIG_I2C_SIZE_BYTES 18 102 #define VL53L1_SYSTEM_CONTROL_I2C_SIZE_BYTES 5 103 #define VL53L1_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 104 #define VL53L1_CORE_RESULTS_I2C_SIZE_BYTES 33 105 #define VL53L1_DEBUG_RESULTS_I2C_SIZE_BYTES 56 106 #define VL53L1_NVM_COPY_DATA_I2C_SIZE_BYTES 49 107 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 108 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 109 #define VL53L1_PATCH_DEBUG_I2C_SIZE_BYTES 2 110 #define VL53L1_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES 5 111 #define VL53L1_GPH_STATIC_CONFIG_I2C_SIZE_BYTES 6 112 #define VL53L1_GPH_TIMING_CONFIG_I2C_SIZE_BYTES 16 113 #define VL53L1_FW_INTERNAL_I2C_SIZE_BYTES 2 114 #define VL53L1_PATCH_RESULTS_I2C_SIZE_BYTES 90 115 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 82 116 #define VL53L1_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 117 118 119 /** 120 * @struct VL53L1_static_nvm_managed_t 121 * 122 * - registers = 10 123 * - first_index = 1 (0x0001) 124 * - last _index = 11 (0x000B) 125 * - i2c_size = 11 126 */ 127 128 typedef struct { 129 uint8_t i2c_slave__device_address; 130 /*!< 131 info: \n 132 - msb = 6 133 - lsb = 0 134 - i2c_size = 1 135 136 fields: \n 137 - [6:0] = i2c_slave_device_address 138 */ 139 uint8_t ana_config__vhv_ref_sel_vddpix; 140 /*!< 141 info: \n 142 - msb = 3 143 - lsb = 0 144 - i2c_size = 1 145 146 fields: \n 147 - [3:0] = ref_sel_vddpix 148 */ 149 uint8_t ana_config__vhv_ref_sel_vquench; 150 /*!< 151 info: \n 152 - msb = 6 153 - lsb = 3 154 - i2c_size = 1 155 156 fields: \n 157 - [6:3] = ref_sel_vquench 158 */ 159 uint8_t ana_config__reg_avdd1v2_sel; 160 /*!< 161 info: \n 162 - msb = 1 163 - lsb = 0 164 - i2c_size = 1 165 166 fields: \n 167 - [1:0] = reg_avdd1v2_sel 168 */ 169 uint8_t ana_config__fast_osc__trim; 170 /*!< 171 info: \n 172 - msb = 6 173 - lsb = 0 174 - i2c_size = 1 175 176 fields: \n 177 - [6:0] = fast_osc_trim 178 */ 179 uint16_t osc_measured__fast_osc__frequency; 180 /*!< 181 info: \n 182 - msb = 15 183 - lsb = 0 184 - i2c_size = 2 185 186 fields: \n 187 - [15:0] = osc_frequency (fixed point 4.12) 188 */ 189 uint8_t vhv_config__timeout_macrop_loop_bound; 190 /*!< 191 info: \n 192 - msb = 7 193 - lsb = 0 194 - i2c_size = 1 195 196 fields: \n 197 - [1:0] = vhv_timeout__macrop 198 - [7:2] = vhv_loop_bound 199 */ 200 uint8_t vhv_config__count_thresh; 201 /*!< 202 info: \n 203 - msb = 7 204 - lsb = 0 205 - i2c_size = 1 206 207 fields: \n 208 - [7:0] = vhv_count_thresh 209 */ 210 uint8_t vhv_config__offset; 211 /*!< 212 info: \n 213 - msb = 5 214 - lsb = 0 215 - i2c_size = 1 216 217 fields: \n 218 - [5:0] = vhv_step_val 219 */ 220 uint8_t vhv_config__init; 221 /*!< 222 info: \n 223 - msb = 7 224 - lsb = 0 225 - i2c_size = 1 226 227 fields: \n 228 - [7] = vhv0_init_enable 229 - [5:0] = vhv0_init_value 230 */ 231 } VL53L1_static_nvm_managed_t; 232 233 234 /** 235 * @struct VL53L1_customer_nvm_managed_t 236 * 237 * - registers = 16 238 * - first_index = 13 (0x000D) 239 * - last _index = 34 (0x0022) 240 * - i2c_size = 23 241 */ 242 243 typedef struct { 244 uint8_t global_config__spad_enables_ref_0; 245 /*!< 246 info: \n 247 - msb = 7 248 - lsb = 0 249 - i2c_size = 1 250 251 fields: \n 252 - [7:0] = spad_enables_ref_0 253 */ 254 uint8_t global_config__spad_enables_ref_1; 255 /*!< 256 info: \n 257 - msb = 7 258 - lsb = 0 259 - i2c_size = 1 260 261 fields: \n 262 - [7:0] = spad_enables_ref_1 263 */ 264 uint8_t global_config__spad_enables_ref_2; 265 /*!< 266 info: \n 267 - msb = 7 268 - lsb = 0 269 - i2c_size = 1 270 271 fields: \n 272 - [7:0] = spad_enables_ref_2 273 */ 274 uint8_t global_config__spad_enables_ref_3; 275 /*!< 276 info: \n 277 - msb = 7 278 - lsb = 0 279 - i2c_size = 1 280 281 fields: \n 282 - [7:0] = spad_enables_ref_3 283 */ 284 uint8_t global_config__spad_enables_ref_4; 285 /*!< 286 info: \n 287 - msb = 7 288 - lsb = 0 289 - i2c_size = 1 290 291 fields: \n 292 - [7:0] = spad_enables_ref_4 293 */ 294 uint8_t global_config__spad_enables_ref_5; 295 /*!< 296 info: \n 297 - msb = 3 298 - lsb = 0 299 - i2c_size = 1 300 301 fields: \n 302 - [3:0] = spad_enables_ref_5 303 */ 304 uint8_t global_config__ref_en_start_select; 305 /*!< 306 info: \n 307 - msb = 7 308 - lsb = 0 309 - i2c_size = 1 310 311 fields: \n 312 - [7:0] = ref_en_start_select 313 */ 314 uint8_t ref_spad_man__num_requested_ref_spads; 315 /*!< 316 info: \n 317 - msb = 5 318 - lsb = 0 319 - i2c_size = 1 320 321 fields: \n 322 - [5:0] = ref_spad_man__num_requested_ref_spad 323 */ 324 uint8_t ref_spad_man__ref_location; 325 /*!< 326 info: \n 327 - msb = 1 328 - lsb = 0 329 - i2c_size = 1 330 331 fields: \n 332 - [1:0] = ref_spad_man__ref_location 333 */ 334 uint16_t algo__crosstalk_compensation_plane_offset_kcps; 335 /*!< 336 info: \n 337 - msb = 15 338 - lsb = 0 339 - i2c_size = 2 340 341 fields: \n 342 - [15:0] = crosstalk_compensation_plane_offset_kcps (fixed point 7.9) 343 */ 344 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 345 /*!< 346 info: \n 347 - msb = 15 348 - lsb = 0 349 - i2c_size = 2 350 351 fields: \n 352 - [15:0] = crosstalk_compensation_x_plane_gradient_kcps (fixed point 5.11) 353 */ 354 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 355 /*!< 356 info: \n 357 - msb = 15 358 - lsb = 0 359 - i2c_size = 2 360 361 fields: \n 362 - [15:0] = crosstalk_compensation_y_plane_gradient_kcps (fixed point 5.11) 363 */ 364 uint16_t ref_spad_char__total_rate_target_mcps; 365 /*!< 366 info: \n 367 - msb = 15 368 - lsb = 0 369 - i2c_size = 2 370 371 fields: \n 372 - [15:0] = ref_spad_char__total_rate_target_mcps (fixed point 9.7) 373 */ 374 int16_t algo__part_to_part_range_offset_mm; 375 /*!< 376 info: \n 377 - msb = 12 378 - lsb = 0 379 - i2c_size = 2 380 381 fields: \n 382 - [12:0] = part_to_part_offset_mm (fixed point 11.2) 383 */ 384 int16_t mm_config__inner_offset_mm; 385 /*!< 386 info: \n 387 - msb = 15 388 - lsb = 0 389 - i2c_size = 2 390 391 fields: \n 392 - [15:0] = mm_config__inner_offset_mm 393 */ 394 int16_t mm_config__outer_offset_mm; 395 /*!< 396 info: \n 397 - msb = 15 398 - lsb = 0 399 - i2c_size = 2 400 401 fields: \n 402 - [15:0] = mm_config__outer_offset_mm 403 */ 404 } VL53L1_customer_nvm_managed_t; 405 406 407 /** 408 * @struct VL53L1_static_config_t 409 * 410 * - registers = 30 411 * - first_index = 36 (0x0024) 412 * - last _index = 67 (0x0043) 413 * - i2c_size = 32 414 */ 415 416 typedef struct { 417 uint16_t dss_config__target_total_rate_mcps; 418 /*!< 419 info: \n 420 - msb = 15 421 - lsb = 0 422 - i2c_size = 2 423 424 fields: \n 425 - [15:0] = dss_config__target_total_rate_mcps (fixed point 9.7) 426 */ 427 uint8_t debug__ctrl; 428 /*!< 429 info: \n 430 - msb = 0 431 - lsb = 0 432 - i2c_size = 1 433 434 fields: \n 435 - [0] = enable_result_logging 436 */ 437 uint8_t test_mode__ctrl; 438 /*!< 439 info: \n 440 - msb = 3 441 - lsb = 0 442 - i2c_size = 1 443 444 fields: \n 445 - [3:0] = test_mode__cmd 446 */ 447 uint8_t clk_gating__ctrl; 448 /*!< 449 info: \n 450 - msb = 3 451 - lsb = 0 452 - i2c_size = 1 453 454 fields: \n 455 - [0] = clk_gate_en__mcu_bank 456 - [1] = clk_gate_en__mcu_patch_ctrl 457 - [2] = clk_gate_en__mcu_timers 458 - [3] = clk_gate_en__mcu_mult_div 459 */ 460 uint8_t nvm_bist__ctrl; 461 /*!< 462 info: \n 463 - msb = 4 464 - lsb = 0 465 - i2c_size = 1 466 467 fields: \n 468 - [2:0] = nvm_bist__cmd 469 - [4] = nvm_bist__ctrl 470 */ 471 uint8_t nvm_bist__num_nvm_words; 472 /*!< 473 info: \n 474 - msb = 6 475 - lsb = 0 476 - i2c_size = 1 477 478 fields: \n 479 - [6:0] = nvm_bist__num_nvm_words 480 */ 481 uint8_t nvm_bist__start_address; 482 /*!< 483 info: \n 484 - msb = 6 485 - lsb = 0 486 - i2c_size = 1 487 488 fields: \n 489 - [6:0] = nvm_bist__start_address 490 */ 491 uint8_t host_if__status; 492 /*!< 493 info: \n 494 - msb = 0 495 - lsb = 0 496 - i2c_size = 1 497 498 fields: \n 499 - [0] = host_interface 500 */ 501 uint8_t pad_i2c_hv__config; 502 /*!< 503 info: \n 504 - msb = 7 505 - lsb = 0 506 - i2c_size = 1 507 508 fields: \n 509 - [0] = pad_scl_sda__vmodeint_hv 510 - [1] = i2c_pad__test_hv 511 - [2] = pad_scl__fpen_hv 512 - [4:3] = pad_scl__progdel_hv 513 - [5] = pad_sda__fpen_hv 514 - [7:6] = pad_sda__progdel_hv 515 */ 516 uint8_t pad_i2c_hv__extsup_config; 517 /*!< 518 info: \n 519 - msb = 0 520 - lsb = 0 521 - i2c_size = 1 522 523 fields: \n 524 - [0] = pad_scl_sda__extsup_hv 525 */ 526 uint8_t gpio_hv_pad__ctrl; 527 /*!< 528 info: \n 529 - msb = 1 530 - lsb = 0 531 - i2c_size = 1 532 533 fields: \n 534 - [0] = gpio__extsup_hv 535 - [1] = gpio__vmodeint_hv 536 */ 537 uint8_t gpio_hv_mux__ctrl; 538 /*!< 539 info: \n 540 - msb = 4 541 - lsb = 0 542 - i2c_size = 1 543 544 fields: \n 545 - [3:0] = gpio__mux_select_hv 546 - [4] = gpio__mux_active_high_hv 547 */ 548 uint8_t gpio__tio_hv_status; 549 /*!< 550 info: \n 551 - msb = 1 552 - lsb = 0 553 - i2c_size = 1 554 555 fields: \n 556 - [0] = gpio__tio_hv 557 - [1] = fresh_out_of_reset 558 */ 559 uint8_t gpio__fio_hv_status; 560 /*!< 561 info: \n 562 - msb = 1 563 - lsb = 1 564 - i2c_size = 1 565 566 fields: \n 567 - [1] = gpio__fio_hv 568 */ 569 uint8_t ana_config__spad_sel_pswidth; 570 /*!< 571 info: \n 572 - msb = 2 573 - lsb = 0 574 - i2c_size = 1 575 576 fields: \n 577 - [2:0] = spad_sel_pswidth 578 */ 579 uint8_t ana_config__vcsel_pulse_width_offset; 580 /*!< 581 info: \n 582 - msb = 4 583 - lsb = 0 584 - i2c_size = 1 585 586 fields: \n 587 - [4:0] = vcsel_pulse_width_offset (fixed point 1.4) 588 */ 589 uint8_t ana_config__fast_osc__config_ctrl; 590 /*!< 591 info: \n 592 - msb = 0 593 - lsb = 0 594 - i2c_size = 1 595 596 fields: \n 597 - [0] = osc_config__latch_bypass 598 */ 599 uint8_t sigma_estimator__effective_pulse_width_ns; 600 /*!< 601 info: \n 602 - msb = 7 603 - lsb = 0 604 - i2c_size = 1 605 606 fields: \n 607 - [7:0] = sigma_estimator__eff_pulse_width 608 */ 609 uint8_t sigma_estimator__effective_ambient_width_ns; 610 /*!< 611 info: \n 612 - msb = 7 613 - lsb = 0 614 - i2c_size = 1 615 616 fields: \n 617 - [7:0] = sigma_estimator__eff_ambient_width 618 */ 619 uint8_t sigma_estimator__sigma_ref_mm; 620 /*!< 621 info: \n 622 - msb = 7 623 - lsb = 0 624 - i2c_size = 1 625 626 fields: \n 627 - [7:0] = sigma_estimator__sigma_ref 628 */ 629 uint8_t algo__crosstalk_compensation_valid_height_mm; 630 /*!< 631 info: \n 632 - msb = 7 633 - lsb = 0 634 - i2c_size = 1 635 636 fields: \n 637 - [7:0] = crosstalk_compensation_valid_height_mm 638 */ 639 uint8_t spare_host_config__static_config_spare_0; 640 /*!< 641 info: \n 642 - msb = 7 643 - lsb = 0 644 - i2c_size = 1 645 646 fields: \n 647 - [7:0] = static_config_spare_0 648 */ 649 uint8_t spare_host_config__static_config_spare_1; 650 /*!< 651 info: \n 652 - msb = 7 653 - lsb = 0 654 - i2c_size = 1 655 656 fields: \n 657 - [7:0] = static_config_spare_1 658 */ 659 uint16_t algo__range_ignore_threshold_mcps; 660 /*!< 661 info: \n 662 - msb = 15 663 - lsb = 0 664 - i2c_size = 2 665 666 fields: \n 667 - [15:0] = range_ignore_thresh_mcps (fixed point 3.13) 668 */ 669 uint8_t algo__range_ignore_valid_height_mm; 670 /*!< 671 info: \n 672 - msb = 7 673 - lsb = 0 674 - i2c_size = 1 675 676 fields: \n 677 - [7:0] = range_ignore_height_mm 678 */ 679 uint8_t algo__range_min_clip; 680 /*!< 681 info: \n 682 - msb = 7 683 - lsb = 0 684 - i2c_size = 1 685 686 fields: \n 687 - [0] = algo__range_min_clip_enable 688 - [7:1] = algo__range_min_clip_value_mm 689 */ 690 uint8_t algo__consistency_check__tolerance; 691 /*!< 692 info: \n 693 - msb = 3 694 - lsb = 0 695 - i2c_size = 1 696 697 fields: \n 698 - [3:0] = consistency_check_tolerance (fixed point 1.3) 699 */ 700 uint8_t spare_host_config__static_config_spare_2; 701 /*!< 702 info: \n 703 - msb = 7 704 - lsb = 0 705 - i2c_size = 1 706 707 fields: \n 708 - [7:0] = static_config_spare_2 709 */ 710 uint8_t sd_config__reset_stages_msb; 711 /*!< 712 info: \n 713 - msb = 3 714 - lsb = 0 715 - i2c_size = 1 716 717 fields: \n 718 - [3:0] = loop_init__clear_stage 719 */ 720 uint8_t sd_config__reset_stages_lsb; 721 /*!< 722 info: \n 723 - msb = 7 724 - lsb = 0 725 - i2c_size = 1 726 727 fields: \n 728 - [7:4] = accum_reset__clear_stage 729 - [3:0] = count_reset__clear_stage 730 */ 731 } VL53L1_static_config_t; 732 733 734 /** 735 * @struct VL53L1_general_config_t 736 * 737 * - registers = 17 738 * - first_index = 68 (0x0044) 739 * - last _index = 89 (0x0059) 740 * - i2c_size = 22 741 */ 742 743 typedef struct { 744 uint8_t gph_config__stream_count_update_value; 745 /*!< 746 info: \n 747 - msb = 7 748 - lsb = 0 749 - i2c_size = 1 750 751 fields: \n 752 - [7:0] = stream_count_update_value 753 */ 754 uint8_t global_config__stream_divider; 755 /*!< 756 info: \n 757 - msb = 7 758 - lsb = 0 759 - i2c_size = 1 760 761 fields: \n 762 - [7:0] = stream_count_internal_div 763 */ 764 uint8_t system__interrupt_config_gpio; 765 /*!< 766 info: \n 767 - msb = 7 768 - lsb = 0 769 - i2c_size = 1 770 771 fields: \n 772 - [1:0] = int_mode_distance 773 - [3:2] = int_mode_rate 774 - [4] = int_spare 775 - [5] = int_new_measure_ready 776 - [6] = int_no_target_en 777 - [7] = int_combined_mode 778 */ 779 uint8_t cal_config__vcsel_start; 780 /*!< 781 info: \n 782 - msb = 6 783 - lsb = 0 784 - i2c_size = 1 785 786 fields: \n 787 - [6:0] = cal_config__vcsel_start 788 */ 789 uint16_t cal_config__repeat_rate; 790 /*!< 791 info: \n 792 - msb = 11 793 - lsb = 0 794 - i2c_size = 2 795 796 fields: \n 797 - [11:0] = cal_config__repeat_rate 798 */ 799 uint8_t global_config__vcsel_width; 800 /*!< 801 info: \n 802 - msb = 6 803 - lsb = 0 804 - i2c_size = 1 805 806 fields: \n 807 - [6:0] = global_config__vcsel_width 808 */ 809 uint8_t phasecal_config__timeout_macrop; 810 /*!< 811 info: \n 812 - msb = 7 813 - lsb = 0 814 - i2c_size = 1 815 816 fields: \n 817 - [7:0] = phasecal_config__timeout_macrop 818 */ 819 uint8_t phasecal_config__target; 820 /*!< 821 info: \n 822 - msb = 7 823 - lsb = 0 824 - i2c_size = 1 825 826 fields: \n 827 - [7:0] = algo_phasecal_lim 828 */ 829 uint8_t phasecal_config__override; 830 /*!< 831 info: \n 832 - msb = 0 833 - lsb = 0 834 - i2c_size = 1 835 836 fields: \n 837 - [0] = phasecal_config__override 838 */ 839 uint8_t dss_config__roi_mode_control; 840 /*!< 841 info: \n 842 - msb = 2 843 - lsb = 0 844 - i2c_size = 1 845 846 fields: \n 847 - [1:0] = dss_config__input_mode 848 - [2] = calculate_roi_enable 849 */ 850 uint16_t system__thresh_rate_high; 851 /*!< 852 info: \n 853 - msb = 15 854 - lsb = 0 855 - i2c_size = 2 856 857 fields: \n 858 - [15:0] = thresh_rate_high (fixed point 9.7) 859 */ 860 uint16_t system__thresh_rate_low; 861 /*!< 862 info: \n 863 - msb = 15 864 - lsb = 0 865 - i2c_size = 2 866 867 fields: \n 868 - [15:0] = thresh_rate_low (fixed point 9.7) 869 */ 870 uint16_t dss_config__manual_effective_spads_select; 871 /*!< 872 info: \n 873 - msb = 15 874 - lsb = 0 875 - i2c_size = 2 876 877 fields: \n 878 - [15:0] = dss_config__manual_effective_spads_select 879 */ 880 uint8_t dss_config__manual_block_select; 881 /*!< 882 info: \n 883 - msb = 7 884 - lsb = 0 885 - i2c_size = 1 886 887 fields: \n 888 - [7:0] = dss_config__manual_block_select 889 */ 890 uint8_t dss_config__aperture_attenuation; 891 /*!< 892 info: \n 893 - msb = 7 894 - lsb = 0 895 - i2c_size = 1 896 897 fields: \n 898 - [7:0] = dss_config__aperture_attenuation 899 */ 900 uint8_t dss_config__max_spads_limit; 901 /*!< 902 info: \n 903 - msb = 7 904 - lsb = 0 905 - i2c_size = 1 906 907 fields: \n 908 - [7:0] = dss_config__max_spads_limit 909 */ 910 uint8_t dss_config__min_spads_limit; 911 /*!< 912 info: \n 913 - msb = 7 914 - lsb = 0 915 - i2c_size = 1 916 917 fields: \n 918 - [7:0] = dss_config__min_spads_limit 919 */ 920 } VL53L1_general_config_t; 921 922 923 /** 924 * @struct VL53L1_timing_config_t 925 * 926 * - registers = 16 927 * - first_index = 90 (0x005A) 928 * - last _index = 112 (0x0070) 929 * - i2c_size = 23 930 */ 931 932 typedef struct { 933 uint8_t mm_config__timeout_macrop_a_hi; 934 /*!< 935 info: \n 936 - msb = 3 937 - lsb = 0 938 - i2c_size = 1 939 940 fields: \n 941 - [3:0] = mm_config__config_timeout_macrop_a_hi 942 */ 943 uint8_t mm_config__timeout_macrop_a_lo; 944 /*!< 945 info: \n 946 - msb = 7 947 - lsb = 0 948 - i2c_size = 1 949 950 fields: \n 951 - [7:0] = mm_config__config_timeout_macrop_a_lo 952 */ 953 uint8_t mm_config__timeout_macrop_b_hi; 954 /*!< 955 info: \n 956 - msb = 3 957 - lsb = 0 958 - i2c_size = 1 959 960 fields: \n 961 - [3:0] = mm_config__config_timeout_macrop_b_hi 962 */ 963 uint8_t mm_config__timeout_macrop_b_lo; 964 /*!< 965 info: \n 966 - msb = 7 967 - lsb = 0 968 - i2c_size = 1 969 970 fields: \n 971 - [7:0] = mm_config__config_timeout_macrop_b_lo 972 */ 973 uint8_t range_config__timeout_macrop_a_hi; 974 /*!< 975 info: \n 976 - msb = 3 977 - lsb = 0 978 - i2c_size = 1 979 980 fields: \n 981 - [3:0] = range_timeout_overall_periods_macrop_a_hi 982 */ 983 uint8_t range_config__timeout_macrop_a_lo; 984 /*!< 985 info: \n 986 - msb = 7 987 - lsb = 0 988 - i2c_size = 1 989 990 fields: \n 991 - [7:0] = range_timeout_overall_periods_macrop_a_lo 992 */ 993 uint8_t range_config__vcsel_period_a; 994 /*!< 995 info: \n 996 - msb = 5 997 - lsb = 0 998 - i2c_size = 1 999 1000 fields: \n 1001 - [5:0] = range_config__vcsel_period_a 1002 */ 1003 uint8_t range_config__timeout_macrop_b_hi; 1004 /*!< 1005 info: \n 1006 - msb = 3 1007 - lsb = 0 1008 - i2c_size = 1 1009 1010 fields: \n 1011 - [3:0] = range_timeout_overall_periods_macrop_b_hi 1012 */ 1013 uint8_t range_config__timeout_macrop_b_lo; 1014 /*!< 1015 info: \n 1016 - msb = 7 1017 - lsb = 0 1018 - i2c_size = 1 1019 1020 fields: \n 1021 - [7:0] = range_timeout_overall_periods_macrop_b_lo 1022 */ 1023 uint8_t range_config__vcsel_period_b; 1024 /*!< 1025 info: \n 1026 - msb = 5 1027 - lsb = 0 1028 - i2c_size = 1 1029 1030 fields: \n 1031 - [5:0] = range_config__vcsel_period_b 1032 */ 1033 uint16_t range_config__sigma_thresh; 1034 /*!< 1035 info: \n 1036 - msb = 15 1037 - lsb = 0 1038 - i2c_size = 2 1039 1040 fields: \n 1041 - [15:0] = range_config__sigma_thresh (fixed point 14.2) 1042 */ 1043 uint16_t range_config__min_count_rate_rtn_limit_mcps; 1044 /*!< 1045 info: \n 1046 - msb = 15 1047 - lsb = 0 1048 - i2c_size = 2 1049 1050 fields: \n 1051 - [15:0] = range_config__min_count_rate_rtn_limit_mcps (fixed point 9.7) 1052 */ 1053 uint8_t range_config__valid_phase_low; 1054 /*!< 1055 info: \n 1056 - msb = 7 1057 - lsb = 0 1058 - i2c_size = 1 1059 1060 fields: \n 1061 - [7:0] = range_config__valid_phase_low (fixed point 5.3) 1062 */ 1063 uint8_t range_config__valid_phase_high; 1064 /*!< 1065 info: \n 1066 - msb = 7 1067 - lsb = 0 1068 - i2c_size = 1 1069 1070 fields: \n 1071 - [7:0] = range_config__valid_phase_high (fixed point 5.3) 1072 */ 1073 uint32_t system__intermeasurement_period; 1074 /*!< 1075 info: \n 1076 - msb = 31 1077 - lsb = 0 1078 - i2c_size = 4 1079 1080 fields: \n 1081 - [31:0] = intermeasurement_period 1082 */ 1083 uint8_t system__fractional_enable; 1084 /*!< 1085 info: \n 1086 - msb = 0 1087 - lsb = 0 1088 - i2c_size = 1 1089 1090 fields: \n 1091 - [0] = range_fractional_enable 1092 */ 1093 } VL53L1_timing_config_t; 1094 1095 1096 /** 1097 * @struct VL53L1_dynamic_config_t 1098 * 1099 * - registers = 16 1100 * - first_index = 113 (0x0071) 1101 * - last _index = 130 (0x0082) 1102 * - i2c_size = 18 1103 */ 1104 1105 typedef struct { 1106 uint8_t system__grouped_parameter_hold_0; 1107 /*!< 1108 info: \n 1109 - msb = 1 1110 - lsb = 0 1111 - i2c_size = 1 1112 1113 fields: \n 1114 - [0] = grouped_parameter_hold 1115 - [1] = grouped_parameter_hold_id 1116 */ 1117 uint16_t system__thresh_high; 1118 /*!< 1119 info: \n 1120 - msb = 15 1121 - lsb = 0 1122 - i2c_size = 2 1123 1124 fields: \n 1125 - [15:0] = thresh_high 1126 */ 1127 uint16_t system__thresh_low; 1128 /*!< 1129 info: \n 1130 - msb = 15 1131 - lsb = 0 1132 - i2c_size = 2 1133 1134 fields: \n 1135 - [15:0] = thresh_low 1136 */ 1137 uint8_t system__enable_xtalk_per_quadrant; 1138 /*!< 1139 info: \n 1140 - msb = 0 1141 - lsb = 0 1142 - i2c_size = 1 1143 1144 fields: \n 1145 - [0] = system__enable_xtalk_per_quadrant 1146 */ 1147 uint8_t system__seed_config; 1148 /*!< 1149 info: \n 1150 - msb = 2 1151 - lsb = 0 1152 - i2c_size = 1 1153 1154 fields: \n 1155 - [1:0] = system__seed_config 1156 - [2] = system__fw_pause_ctrl 1157 */ 1158 uint8_t sd_config__woi_sd0; 1159 /*!< 1160 info: \n 1161 - msb = 7 1162 - lsb = 0 1163 - i2c_size = 1 1164 1165 fields: \n 1166 - [7:0] = sd_config__woi_sd0 1167 */ 1168 uint8_t sd_config__woi_sd1; 1169 /*!< 1170 info: \n 1171 - msb = 7 1172 - lsb = 0 1173 - i2c_size = 1 1174 1175 fields: \n 1176 - [7:0] = sd_config__woi_sd1 1177 */ 1178 uint8_t sd_config__initial_phase_sd0; 1179 /*!< 1180 info: \n 1181 - msb = 6 1182 - lsb = 0 1183 - i2c_size = 1 1184 1185 fields: \n 1186 - [6:0] = sd_config__initial_phase_sd0 1187 */ 1188 uint8_t sd_config__initial_phase_sd1; 1189 /*!< 1190 info: \n 1191 - msb = 6 1192 - lsb = 0 1193 - i2c_size = 1 1194 1195 fields: \n 1196 - [6:0] = sd_config__initial_phase_sd1 1197 */ 1198 uint8_t system__grouped_parameter_hold_1; 1199 /*!< 1200 info: \n 1201 - msb = 1 1202 - lsb = 0 1203 - i2c_size = 1 1204 1205 fields: \n 1206 - [0] = grouped_parameter_hold 1207 - [1] = grouped_parameter_hold_id 1208 */ 1209 uint8_t sd_config__first_order_select; 1210 /*!< 1211 info: \n 1212 - msb = 1 1213 - lsb = 0 1214 - i2c_size = 1 1215 1216 fields: \n 1217 - [0] = sd_config__first_order_select_rtn 1218 - [1] = sd_config__first_order_select_ref 1219 */ 1220 uint8_t sd_config__quantifier; 1221 /*!< 1222 info: \n 1223 - msb = 3 1224 - lsb = 0 1225 - i2c_size = 1 1226 1227 fields: \n 1228 - [3:0] = sd_config__quantifier 1229 */ 1230 uint8_t roi_config__user_roi_centre_spad; 1231 /*!< 1232 info: \n 1233 - msb = 7 1234 - lsb = 0 1235 - i2c_size = 1 1236 1237 fields: \n 1238 - [7:0] = user_roi_center_spad 1239 */ 1240 uint8_t roi_config__user_roi_requested_global_xy_size; 1241 /*!< 1242 info: \n 1243 - msb = 7 1244 - lsb = 0 1245 - i2c_size = 1 1246 1247 fields: \n 1248 - [7:0] = roi_config__user_roi_requested_global_xy_size 1249 */ 1250 uint8_t system__sequence_config; 1251 /*!< 1252 info: \n 1253 - msb = 7 1254 - lsb = 0 1255 - i2c_size = 1 1256 1257 fields: \n 1258 - [0] = sequence_vhv_en 1259 - [1] = sequence_phasecal_en 1260 - [2] = sequence_reference_phase_en 1261 - [3] = sequence_dss1_en 1262 - [4] = sequence_dss2_en 1263 - [5] = sequence_mm1_en 1264 - [6] = sequence_mm2_en 1265 - [7] = sequence_range_en 1266 */ 1267 uint8_t system__grouped_parameter_hold; 1268 /*!< 1269 info: \n 1270 - msb = 1 1271 - lsb = 0 1272 - i2c_size = 1 1273 1274 fields: \n 1275 - [0] = grouped_parameter_hold 1276 - [1] = grouped_parameter_hold_id 1277 */ 1278 } VL53L1_dynamic_config_t; 1279 1280 1281 /** 1282 * @struct VL53L1_system_control_t 1283 * 1284 * - registers = 5 1285 * - first_index = 131 (0x0083) 1286 * - last _index = 135 (0x0087) 1287 * - i2c_size = 5 1288 */ 1289 1290 typedef struct { 1291 uint8_t power_management__go1_power_force; 1292 /*!< 1293 info: \n 1294 - msb = 0 1295 - lsb = 0 1296 - i2c_size = 1 1297 1298 fields: \n 1299 - [0] = go1_dig_powerforce 1300 */ 1301 uint8_t system__stream_count_ctrl; 1302 /*!< 1303 info: \n 1304 - msb = 0 1305 - lsb = 0 1306 - i2c_size = 1 1307 1308 fields: \n 1309 - [0] = retain_stream_count 1310 */ 1311 uint8_t firmware__enable; 1312 /*!< 1313 info: \n 1314 - msb = 0 1315 - lsb = 0 1316 - i2c_size = 1 1317 1318 fields: \n 1319 - [0] = firmware_enable 1320 */ 1321 uint8_t system__interrupt_clear; 1322 /*!< 1323 info: \n 1324 - msb = 1 1325 - lsb = 0 1326 - i2c_size = 1 1327 1328 fields: \n 1329 - [0] = sys_interrupt_clear_range 1330 - [1] = sys_interrupt_clear_error 1331 */ 1332 uint8_t system__mode_start; 1333 /*!< 1334 info: \n 1335 - msb = 7 1336 - lsb = 0 1337 - i2c_size = 1 1338 1339 fields: \n 1340 - [1:0] = scheduler_mode 1341 - [3:2] = readout_mode 1342 - [4] = mode_range__single_shot 1343 - [5] = mode_range__back_to_back 1344 - [6] = mode_range__timed 1345 - [7] = mode_range__abort 1346 */ 1347 } VL53L1_system_control_t; 1348 1349 1350 /** 1351 * @struct VL53L1_system_results_t 1352 * 1353 * - registers = 25 1354 * - first_index = 136 (0x0088) 1355 * - last _index = 179 (0x00B3) 1356 * - i2c_size = 44 1357 */ 1358 1359 typedef struct { 1360 uint8_t result__interrupt_status; 1361 /*!< 1362 info: \n 1363 - msb = 5 1364 - lsb = 0 1365 - i2c_size = 1 1366 1367 fields: \n 1368 - [2:0] = int_status 1369 - [4:3] = int_error_status 1370 - [5] = gph_id_gpio_status 1371 */ 1372 uint8_t result__range_status; 1373 /*!< 1374 info: \n 1375 - msb = 7 1376 - lsb = 0 1377 - i2c_size = 1 1378 1379 fields: \n 1380 - [4:0] = range_status 1381 - [5] = max_threshold_hit 1382 - [6] = min_threshold_hit 1383 - [7] = gph_id_range_status 1384 */ 1385 uint8_t result__report_status; 1386 /*!< 1387 info: \n 1388 - msb = 3 1389 - lsb = 0 1390 - i2c_size = 1 1391 1392 fields: \n 1393 - [3:0] = report_status 1394 */ 1395 uint8_t result__stream_count; 1396 /*!< 1397 info: \n 1398 - msb = 7 1399 - lsb = 0 1400 - i2c_size = 1 1401 1402 fields: \n 1403 - [7:0] = result__stream_count 1404 */ 1405 uint16_t result__dss_actual_effective_spads_sd0; 1406 /*!< 1407 info: \n 1408 - msb = 15 1409 - lsb = 0 1410 - i2c_size = 2 1411 1412 fields: \n 1413 - [15:0] = result__dss_actual_effective_spads_sd0 (fixed point 8.8) 1414 */ 1415 uint16_t result__peak_signal_count_rate_mcps_sd0; 1416 /*!< 1417 info: \n 1418 - msb = 15 1419 - lsb = 0 1420 - i2c_size = 2 1421 1422 fields: \n 1423 - [15:0] = result__peak_signal_count_rate_mcps_sd0 (fixed point 9.7) 1424 */ 1425 uint16_t result__ambient_count_rate_mcps_sd0; 1426 /*!< 1427 info: \n 1428 - msb = 15 1429 - lsb = 0 1430 - i2c_size = 2 1431 1432 fields: \n 1433 - [15:0] = result__ambient_count_rate_mcps_sd0 (fixed point 9.7) 1434 */ 1435 uint16_t result__sigma_sd0; 1436 /*!< 1437 info: \n 1438 - msb = 15 1439 - lsb = 0 1440 - i2c_size = 2 1441 1442 fields: \n 1443 - [15:0] = result__sigma_sd0 (fixed point 14.2) 1444 */ 1445 uint16_t result__phase_sd0; 1446 /*!< 1447 info: \n 1448 - msb = 15 1449 - lsb = 0 1450 - i2c_size = 2 1451 1452 fields: \n 1453 - [15:0] = result__phase_sd0 (fixed point 5.11) 1454 */ 1455 uint16_t result__final_crosstalk_corrected_range_mm_sd0; 1456 /*!< 1457 info: \n 1458 - msb = 15 1459 - lsb = 0 1460 - i2c_size = 2 1461 1462 fields: \n 1463 - [15:0] = result__final_crosstalk_corrected_range_mm_sd0 1464 */ 1465 uint16_t result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 1466 /*!< 1467 info: \n 1468 - msb = 15 1469 - lsb = 0 1470 - i2c_size = 2 1471 1472 fields: \n 1473 - [15:0] = result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0 (fixed point 9.7) 1474 */ 1475 uint16_t result__mm_inner_actual_effective_spads_sd0; 1476 /*!< 1477 info: \n 1478 - msb = 15 1479 - lsb = 0 1480 - i2c_size = 2 1481 1482 fields: \n 1483 - [15:0] = result__mm_inner_actual_effective_spads_sd0 (fixed point 8.8) 1484 */ 1485 uint16_t result__mm_outer_actual_effective_spads_sd0; 1486 /*!< 1487 info: \n 1488 - msb = 15 1489 - lsb = 0 1490 - i2c_size = 2 1491 1492 fields: \n 1493 - [15:0] = result__mm_outer_actual_effective_spads_sd0 (fixed point 8.8) 1494 */ 1495 uint16_t result__avg_signal_count_rate_mcps_sd0; 1496 /*!< 1497 info: \n 1498 - msb = 15 1499 - lsb = 0 1500 - i2c_size = 2 1501 1502 fields: \n 1503 - [15:0] = result__avg_signal_count_rate_mcps_sd0 (fixed point 9.7) 1504 */ 1505 uint16_t result__dss_actual_effective_spads_sd1; 1506 /*!< 1507 info: \n 1508 - msb = 15 1509 - lsb = 0 1510 - i2c_size = 2 1511 1512 fields: \n 1513 - [15:0] = result__dss_actual_effective_spads_sd1 (fixed point 8.8) 1514 */ 1515 uint16_t result__peak_signal_count_rate_mcps_sd1; 1516 /*!< 1517 info: \n 1518 - msb = 15 1519 - lsb = 0 1520 - i2c_size = 2 1521 1522 fields: \n 1523 - [15:0] = result__peak_signal_count_rate_mcps_sd1 (fixed point 9.7) 1524 */ 1525 uint16_t result__ambient_count_rate_mcps_sd1; 1526 /*!< 1527 info: \n 1528 - msb = 15 1529 - lsb = 0 1530 - i2c_size = 2 1531 1532 fields: \n 1533 - [15:0] = result__ambient_count_rate_mcps_sd1 (fixed point 9.7) 1534 */ 1535 uint16_t result__sigma_sd1; 1536 /*!< 1537 info: \n 1538 - msb = 15 1539 - lsb = 0 1540 - i2c_size = 2 1541 1542 fields: \n 1543 - [15:0] = result__sigma_sd1 (fixed point 14.2) 1544 */ 1545 uint16_t result__phase_sd1; 1546 /*!< 1547 info: \n 1548 - msb = 15 1549 - lsb = 0 1550 - i2c_size = 2 1551 1552 fields: \n 1553 - [15:0] = result__phase_sd1 (fixed point 5.11) 1554 */ 1555 uint16_t result__final_crosstalk_corrected_range_mm_sd1; 1556 /*!< 1557 info: \n 1558 - msb = 15 1559 - lsb = 0 1560 - i2c_size = 2 1561 1562 fields: \n 1563 - [15:0] = result__final_crosstalk_corrected_range_mm_sd1 1564 */ 1565 uint16_t result__spare_0_sd1; 1566 /*!< 1567 info: \n 1568 - msb = 15 1569 - lsb = 0 1570 - i2c_size = 2 1571 1572 fields: \n 1573 - [15:0] = result__spare_0_sd1 1574 */ 1575 uint16_t result__spare_1_sd1; 1576 /*!< 1577 info: \n 1578 - msb = 15 1579 - lsb = 0 1580 - i2c_size = 2 1581 1582 fields: \n 1583 - [15:0] = result__spare_1_sd1 1584 */ 1585 uint16_t result__spare_2_sd1; 1586 /*!< 1587 info: \n 1588 - msb = 15 1589 - lsb = 0 1590 - i2c_size = 2 1591 1592 fields: \n 1593 - [15:0] = result__spare_2_sd1 1594 */ 1595 uint8_t result__spare_3_sd1; 1596 /*!< 1597 info: \n 1598 - msb = 7 1599 - lsb = 0 1600 - i2c_size = 1 1601 1602 fields: \n 1603 - [7:0] = result__spare_3_sd1 1604 */ 1605 uint8_t result__thresh_info; 1606 /*!< 1607 info: \n 1608 - msb = 7 1609 - lsb = 0 1610 - i2c_size = 1 1611 1612 fields: \n 1613 - [3:0] = result__distance_int_info 1614 - [7:4] = result__rate_int_info 1615 */ 1616 } VL53L1_system_results_t; 1617 1618 1619 /** 1620 * @struct VL53L1_core_results_t 1621 * 1622 * - registers = 9 1623 * - first_index = 180 (0x00B4) 1624 * - last _index = 212 (0x00D4) 1625 * - i2c_size = 33 1626 */ 1627 1628 typedef struct { 1629 uint32_t result_core__ambient_window_events_sd0; 1630 /*!< 1631 info: \n 1632 - msb = 31 1633 - lsb = 0 1634 - i2c_size = 4 1635 1636 fields: \n 1637 - [31:0] = result_core__ambient_window_events_sd0 1638 */ 1639 uint32_t result_core__ranging_total_events_sd0; 1640 /*!< 1641 info: \n 1642 - msb = 31 1643 - lsb = 0 1644 - i2c_size = 4 1645 1646 fields: \n 1647 - [31:0] = result_core__ranging_total_events_sd0 1648 */ 1649 int32_t result_core__signal_total_events_sd0; 1650 /*!< 1651 info: \n 1652 - msb = 31 1653 - lsb = 0 1654 - i2c_size = 4 1655 1656 fields: \n 1657 - [31:0] = result_core__signal_total_events_sd0 1658 */ 1659 uint32_t result_core__total_periods_elapsed_sd0; 1660 /*!< 1661 info: \n 1662 - msb = 31 1663 - lsb = 0 1664 - i2c_size = 4 1665 1666 fields: \n 1667 - [31:0] = result_core__total_periods_elapsed_sd0 1668 */ 1669 uint32_t result_core__ambient_window_events_sd1; 1670 /*!< 1671 info: \n 1672 - msb = 31 1673 - lsb = 0 1674 - i2c_size = 4 1675 1676 fields: \n 1677 - [31:0] = result_core__ambient_window_events_sd1 1678 */ 1679 uint32_t result_core__ranging_total_events_sd1; 1680 /*!< 1681 info: \n 1682 - msb = 31 1683 - lsb = 0 1684 - i2c_size = 4 1685 1686 fields: \n 1687 - [31:0] = result_core__ranging_total_events_sd1 1688 */ 1689 int32_t result_core__signal_total_events_sd1; 1690 /*!< 1691 info: \n 1692 - msb = 31 1693 - lsb = 0 1694 - i2c_size = 4 1695 1696 fields: \n 1697 - [31:0] = result_core__signal_total_events_sd1 1698 */ 1699 uint32_t result_core__total_periods_elapsed_sd1; 1700 /*!< 1701 info: \n 1702 - msb = 31 1703 - lsb = 0 1704 - i2c_size = 4 1705 1706 fields: \n 1707 - [31:0] = result_core__total_periods_elapsed_sd1 1708 */ 1709 uint8_t result_core__spare_0; 1710 /*!< 1711 info: \n 1712 - msb = 7 1713 - lsb = 0 1714 - i2c_size = 1 1715 1716 fields: \n 1717 - [7:0] = result_core__spare_0 1718 */ 1719 } VL53L1_core_results_t; 1720 1721 1722 /** 1723 * @struct VL53L1_debug_results_t 1724 * 1725 * - registers = 43 1726 * - first_index = 214 (0x00D6) 1727 * - last _index = 269 (0x010D) 1728 * - i2c_size = 56 1729 */ 1730 1731 typedef struct { 1732 uint16_t phasecal_result__reference_phase; 1733 /*!< 1734 info: \n 1735 - msb = 15 1736 - lsb = 0 1737 - i2c_size = 2 1738 1739 fields: \n 1740 - [15:0] = result_phasecal__reference_phase (fixed point 5.11) 1741 */ 1742 uint8_t phasecal_result__vcsel_start; 1743 /*!< 1744 info: \n 1745 - msb = 6 1746 - lsb = 0 1747 - i2c_size = 1 1748 1749 fields: \n 1750 - [6:0] = result_phasecal__vcsel_start 1751 */ 1752 uint8_t ref_spad_char_result__num_actual_ref_spads; 1753 /*!< 1754 info: \n 1755 - msb = 5 1756 - lsb = 0 1757 - i2c_size = 1 1758 1759 fields: \n 1760 - [5:0] = ref_spad_char_result__num_actual_ref_spads 1761 */ 1762 uint8_t ref_spad_char_result__ref_location; 1763 /*!< 1764 info: \n 1765 - msb = 1 1766 - lsb = 0 1767 - i2c_size = 1 1768 1769 fields: \n 1770 - [1:0] = ref_spad_char_result__ref_location 1771 */ 1772 uint8_t vhv_result__coldboot_status; 1773 /*!< 1774 info: \n 1775 - msb = 0 1776 - lsb = 0 1777 - i2c_size = 1 1778 1779 fields: \n 1780 - [0] = vhv_result__coldboot_status 1781 */ 1782 uint8_t vhv_result__search_result; 1783 /*!< 1784 info: \n 1785 - msb = 5 1786 - lsb = 0 1787 - i2c_size = 1 1788 1789 fields: \n 1790 - [5:0] = cp_sel_result 1791 */ 1792 uint8_t vhv_result__latest_setting; 1793 /*!< 1794 info: \n 1795 - msb = 5 1796 - lsb = 0 1797 - i2c_size = 1 1798 1799 fields: \n 1800 - [5:0] = cp_sel_latest_setting 1801 */ 1802 uint16_t result__osc_calibrate_val; 1803 /*!< 1804 info: \n 1805 - msb = 9 1806 - lsb = 0 1807 - i2c_size = 2 1808 1809 fields: \n 1810 - [9:0] = osc_calibrate_val 1811 */ 1812 uint8_t ana_config__powerdown_go1; 1813 /*!< 1814 info: \n 1815 - msb = 1 1816 - lsb = 0 1817 - i2c_size = 1 1818 1819 fields: \n 1820 - [0] = go2_ref_bg_disable_avdd 1821 - [1] = go2_regdvdd1v2_enable_avdd 1822 */ 1823 uint8_t ana_config__ref_bg_ctrl; 1824 /*!< 1825 info: \n 1826 - msb = 1 1827 - lsb = 0 1828 - i2c_size = 1 1829 1830 fields: \n 1831 - [0] = go2_ref_overdrvbg_avdd 1832 - [1] = go2_ref_forcebgison_avdd 1833 */ 1834 uint8_t ana_config__regdvdd1v2_ctrl; 1835 /*!< 1836 info: \n 1837 - msb = 3 1838 - lsb = 0 1839 - i2c_size = 1 1840 1841 fields: \n 1842 - [0] = go2_regdvdd1v2_sel_pulldown_avdd 1843 - [1] = go2_regdvdd1v2_sel_boost_avdd 1844 - [3:2] = go2_regdvdd1v2_selv_avdd 1845 */ 1846 uint8_t ana_config__osc_slow_ctrl; 1847 /*!< 1848 info: \n 1849 - msb = 2 1850 - lsb = 0 1851 - i2c_size = 1 1852 1853 fields: \n 1854 - [0] = osc_slow_en 1855 - [1] = osc_slow_op_en 1856 - [2] = osc_slow_freq_sel 1857 */ 1858 uint8_t test_mode__status; 1859 /*!< 1860 info: \n 1861 - msb = 0 1862 - lsb = 0 1863 - i2c_size = 1 1864 1865 fields: \n 1866 - [0] = test_mode_status 1867 */ 1868 uint8_t firmware__system_status; 1869 /*!< 1870 info: \n 1871 - msb = 1 1872 - lsb = 0 1873 - i2c_size = 1 1874 1875 fields: \n 1876 - [0] = firmware_bootup 1877 - [1] = firmware_first_range 1878 */ 1879 uint8_t firmware__mode_status; 1880 /*!< 1881 info: \n 1882 - msb = 7 1883 - lsb = 0 1884 - i2c_size = 1 1885 1886 fields: \n 1887 - [7:0] = firmware_mode_status 1888 */ 1889 uint8_t firmware__secondary_mode_status; 1890 /*!< 1891 info: \n 1892 - msb = 7 1893 - lsb = 0 1894 - i2c_size = 1 1895 1896 fields: \n 1897 - [7:0] = fw_secondary_mode_status 1898 */ 1899 uint16_t firmware__cal_repeat_rate_counter; 1900 /*!< 1901 info: \n 1902 - msb = 11 1903 - lsb = 0 1904 - i2c_size = 2 1905 1906 fields: \n 1907 - [11:0] = firmware_cal_repeat_rate 1908 */ 1909 uint16_t gph__system__thresh_high; 1910 /*!< 1911 info: \n 1912 - msb = 15 1913 - lsb = 0 1914 - i2c_size = 2 1915 1916 fields: \n 1917 - [15:0] = shadow_thresh_high 1918 */ 1919 uint16_t gph__system__thresh_low; 1920 /*!< 1921 info: \n 1922 - msb = 15 1923 - lsb = 0 1924 - i2c_size = 2 1925 1926 fields: \n 1927 - [15:0] = shadow_thresh_low 1928 */ 1929 uint8_t gph__system__enable_xtalk_per_quadrant; 1930 /*!< 1931 info: \n 1932 - msb = 0 1933 - lsb = 0 1934 - i2c_size = 1 1935 1936 fields: \n 1937 - [0] = shadow__enable_xtalk_per_quadrant 1938 */ 1939 uint8_t gph__spare_0; 1940 /*!< 1941 info: \n 1942 - msb = 2 1943 - lsb = 0 1944 - i2c_size = 1 1945 1946 fields: \n 1947 - [0] = fw_safe_to_disable 1948 - [1] = shadow__spare_0 1949 - [2] = shadow__spare_1 1950 */ 1951 uint8_t gph__sd_config__woi_sd0; 1952 /*!< 1953 info: \n 1954 - msb = 7 1955 - lsb = 0 1956 - i2c_size = 1 1957 1958 fields: \n 1959 - [7:0] = shadow_sd_config__woi_sd0 1960 */ 1961 uint8_t gph__sd_config__woi_sd1; 1962 /*!< 1963 info: \n 1964 - msb = 7 1965 - lsb = 0 1966 - i2c_size = 1 1967 1968 fields: \n 1969 - [7:0] = shadow_sd_config__woi_sd1 1970 */ 1971 uint8_t gph__sd_config__initial_phase_sd0; 1972 /*!< 1973 info: \n 1974 - msb = 6 1975 - lsb = 0 1976 - i2c_size = 1 1977 1978 fields: \n 1979 - [6:0] = shadow_sd_config__initial_phase_sd0 1980 */ 1981 uint8_t gph__sd_config__initial_phase_sd1; 1982 /*!< 1983 info: \n 1984 - msb = 6 1985 - lsb = 0 1986 - i2c_size = 1 1987 1988 fields: \n 1989 - [6:0] = shadow_sd_config__initial_phase_sd1 1990 */ 1991 uint8_t gph__sd_config__first_order_select; 1992 /*!< 1993 info: \n 1994 - msb = 1 1995 - lsb = 0 1996 - i2c_size = 1 1997 1998 fields: \n 1999 - [0] = shadow_sd_config__first_order_select_rtn 2000 - [1] = shadow_sd_config__first_order_select_ref 2001 */ 2002 uint8_t gph__sd_config__quantifier; 2003 /*!< 2004 info: \n 2005 - msb = 3 2006 - lsb = 0 2007 - i2c_size = 1 2008 2009 fields: \n 2010 - [3:0] = shadow_sd_config__quantifier 2011 */ 2012 uint8_t gph__roi_config__user_roi_centre_spad; 2013 /*!< 2014 info: \n 2015 - msb = 7 2016 - lsb = 0 2017 - i2c_size = 1 2018 2019 fields: \n 2020 - [7:0] = shadow_user_roi_center_spad_q0 2021 */ 2022 uint8_t gph__roi_config__user_roi_requested_global_xy_size; 2023 /*!< 2024 info: \n 2025 - msb = 7 2026 - lsb = 0 2027 - i2c_size = 1 2028 2029 fields: \n 2030 - [7:0] = shadow_user_roi_requested_global_xy_size 2031 */ 2032 uint8_t gph__system__sequence_config; 2033 /*!< 2034 info: \n 2035 - msb = 7 2036 - lsb = 0 2037 - i2c_size = 1 2038 2039 fields: \n 2040 - [0] = shadow_sequence_vhv_en 2041 - [1] = shadow_sequence_phasecal_en 2042 - [2] = shadow_sequence_reference_phase_en 2043 - [3] = shadow_sequence_dss1_en 2044 - [4] = shadow_sequence_dss2_en 2045 - [5] = shadow_sequence_mm1_en 2046 - [6] = shadow_sequence_mm2_en 2047 - [7] = shadow_sequence_range_en 2048 */ 2049 uint8_t gph__gph_id; 2050 /*!< 2051 info: \n 2052 - msb = 0 2053 - lsb = 0 2054 - i2c_size = 1 2055 2056 fields: \n 2057 - [0] = shadow_gph_id 2058 */ 2059 uint8_t system__interrupt_set; 2060 /*!< 2061 info: \n 2062 - msb = 1 2063 - lsb = 0 2064 - i2c_size = 1 2065 2066 fields: \n 2067 - [0] = sys_interrupt_set_range 2068 - [1] = sys_interrupt_set_error 2069 */ 2070 uint8_t interrupt_manager__enables; 2071 /*!< 2072 info: \n 2073 - msb = 4 2074 - lsb = 0 2075 - i2c_size = 1 2076 2077 fields: \n 2078 - [0] = interrupt_enable__single_shot 2079 - [1] = interrupt_enable__back_to_back 2080 - [2] = interrupt_enable__timed 2081 - [3] = interrupt_enable__abort 2082 - [4] = interrupt_enable__test 2083 */ 2084 uint8_t interrupt_manager__clear; 2085 /*!< 2086 info: \n 2087 - msb = 4 2088 - lsb = 0 2089 - i2c_size = 1 2090 2091 fields: \n 2092 - [0] = interrupt_clear__single_shot 2093 - [1] = interrupt_clear__back_to_back 2094 - [2] = interrupt_clear__timed 2095 - [3] = interrupt_clear__abort 2096 - [4] = interrupt_clear__test 2097 */ 2098 uint8_t interrupt_manager__status; 2099 /*!< 2100 info: \n 2101 - msb = 4 2102 - lsb = 0 2103 - i2c_size = 1 2104 2105 fields: \n 2106 - [0] = interrupt_status__single_shot 2107 - [1] = interrupt_status__back_to_back 2108 - [2] = interrupt_status__timed 2109 - [3] = interrupt_status__abort 2110 - [4] = interrupt_status__test 2111 */ 2112 uint8_t mcu_to_host_bank__wr_access_en; 2113 /*!< 2114 info: \n 2115 - msb = 0 2116 - lsb = 0 2117 - i2c_size = 1 2118 2119 fields: \n 2120 - [0] = mcu_to_host_bank_wr_en 2121 */ 2122 uint8_t power_management__go1_reset_status; 2123 /*!< 2124 info: \n 2125 - msb = 0 2126 - lsb = 0 2127 - i2c_size = 1 2128 2129 fields: \n 2130 - [0] = go1_status 2131 */ 2132 uint8_t pad_startup_mode__value_ro; 2133 /*!< 2134 info: \n 2135 - msb = 1 2136 - lsb = 0 2137 - i2c_size = 1 2138 2139 fields: \n 2140 - [0] = pad_atest1_val_ro 2141 - [1] = pad_atest2_val_ro 2142 */ 2143 uint8_t pad_startup_mode__value_ctrl; 2144 /*!< 2145 info: \n 2146 - msb = 5 2147 - lsb = 0 2148 - i2c_size = 1 2149 2150 fields: \n 2151 - [0] = pad_atest1_val 2152 - [1] = pad_atest2_val 2153 - [4] = pad_atest1_dig_enable 2154 - [5] = pad_atest2_dig_enable 2155 */ 2156 uint32_t pll_period_us; 2157 /*!< 2158 info: \n 2159 - msb = 17 2160 - lsb = 0 2161 - i2c_size = 4 2162 2163 fields: \n 2164 - [17:0] = pll_period_us (fixed point 0.24) 2165 */ 2166 uint32_t interrupt_scheduler__data_out; 2167 /*!< 2168 info: \n 2169 - msb = 31 2170 - lsb = 0 2171 - i2c_size = 4 2172 2173 fields: \n 2174 - [31:0] = interrupt_scheduler_data_out 2175 */ 2176 uint8_t nvm_bist__complete; 2177 /*!< 2178 info: \n 2179 - msb = 0 2180 - lsb = 0 2181 - i2c_size = 1 2182 2183 fields: \n 2184 - [0] = nvm_bist__complete 2185 */ 2186 uint8_t nvm_bist__status; 2187 /*!< 2188 info: \n 2189 - msb = 0 2190 - lsb = 0 2191 - i2c_size = 1 2192 2193 fields: \n 2194 - [0] = nvm_bist__status 2195 */ 2196 } VL53L1_debug_results_t; 2197 2198 2199 /** 2200 * @struct VL53L1_nvm_copy_data_t 2201 * 2202 * - registers = 48 2203 * - first_index = 271 (0x010F) 2204 * - last _index = 319 (0x013F) 2205 * - i2c_size = 49 2206 */ 2207 2208 typedef struct { 2209 uint8_t identification__model_id; 2210 /*!< 2211 info: \n 2212 - msb = 7 2213 - lsb = 0 2214 - i2c_size = 1 2215 2216 fields: \n 2217 - [7:0] = model_id 2218 */ 2219 uint8_t identification__module_type; 2220 /*!< 2221 info: \n 2222 - msb = 7 2223 - lsb = 0 2224 - i2c_size = 1 2225 2226 fields: \n 2227 - [7:0] = module_type 2228 */ 2229 uint8_t identification__revision_id; 2230 /*!< 2231 info: \n 2232 - msb = 7 2233 - lsb = 0 2234 - i2c_size = 1 2235 2236 fields: \n 2237 - [3:0] = nvm_revision_id 2238 - [7:4] = mask_revision_id 2239 */ 2240 uint16_t identification__module_id; 2241 /*!< 2242 info: \n 2243 - msb = 15 2244 - lsb = 0 2245 - i2c_size = 2 2246 2247 fields: \n 2248 - [15:0] = module_id 2249 */ 2250 uint8_t ana_config__fast_osc__trim_max; 2251 /*!< 2252 info: \n 2253 - msb = 6 2254 - lsb = 0 2255 - i2c_size = 1 2256 2257 fields: \n 2258 - [6:0] = osc_trim_max 2259 */ 2260 uint8_t ana_config__fast_osc__freq_set; 2261 /*!< 2262 info: \n 2263 - msb = 2 2264 - lsb = 0 2265 - i2c_size = 1 2266 2267 fields: \n 2268 - [2:0] = osc_freq_set 2269 */ 2270 uint8_t ana_config__vcsel_trim; 2271 /*!< 2272 info: \n 2273 - msb = 2 2274 - lsb = 0 2275 - i2c_size = 1 2276 2277 fields: \n 2278 - [2:0] = vcsel_trim 2279 */ 2280 uint8_t ana_config__vcsel_selion; 2281 /*!< 2282 info: \n 2283 - msb = 5 2284 - lsb = 0 2285 - i2c_size = 1 2286 2287 fields: \n 2288 - [5:0] = vcsel_selion 2289 */ 2290 uint8_t ana_config__vcsel_selion_max; 2291 /*!< 2292 info: \n 2293 - msb = 5 2294 - lsb = 0 2295 - i2c_size = 1 2296 2297 fields: \n 2298 - [5:0] = vcsel_selion_max 2299 */ 2300 uint8_t protected_laser_safety__lock_bit; 2301 /*!< 2302 info: \n 2303 - msb = 0 2304 - lsb = 0 2305 - i2c_size = 1 2306 2307 fields: \n 2308 - [0] = laser_safety__lock_bit 2309 */ 2310 uint8_t laser_safety__key; 2311 /*!< 2312 info: \n 2313 - msb = 6 2314 - lsb = 0 2315 - i2c_size = 1 2316 2317 fields: \n 2318 - [6:0] = laser_safety__key 2319 */ 2320 uint8_t laser_safety__key_ro; 2321 /*!< 2322 info: \n 2323 - msb = 0 2324 - lsb = 0 2325 - i2c_size = 1 2326 2327 fields: \n 2328 - [0] = laser_safety__key_ro 2329 */ 2330 uint8_t laser_safety__clip; 2331 /*!< 2332 info: \n 2333 - msb = 5 2334 - lsb = 0 2335 - i2c_size = 1 2336 2337 fields: \n 2338 - [5:0] = vcsel_pulse_width_clip 2339 */ 2340 uint8_t laser_safety__mult; 2341 /*!< 2342 info: \n 2343 - msb = 5 2344 - lsb = 0 2345 - i2c_size = 1 2346 2347 fields: \n 2348 - [5:0] = vcsel_pulse_width_mult 2349 */ 2350 uint8_t global_config__spad_enables_rtn_0; 2351 /*!< 2352 info: \n 2353 - msb = 7 2354 - lsb = 0 2355 - i2c_size = 1 2356 2357 fields: \n 2358 - [7:0] = spad_enables_rtn_0 2359 */ 2360 uint8_t global_config__spad_enables_rtn_1; 2361 /*!< 2362 info: \n 2363 - msb = 7 2364 - lsb = 0 2365 - i2c_size = 1 2366 2367 fields: \n 2368 - [7:0] = spad_enables_rtn_1 2369 */ 2370 uint8_t global_config__spad_enables_rtn_2; 2371 /*!< 2372 info: \n 2373 - msb = 7 2374 - lsb = 0 2375 - i2c_size = 1 2376 2377 fields: \n 2378 - [7:0] = spad_enables_rtn_2 2379 */ 2380 uint8_t global_config__spad_enables_rtn_3; 2381 /*!< 2382 info: \n 2383 - msb = 7 2384 - lsb = 0 2385 - i2c_size = 1 2386 2387 fields: \n 2388 - [7:0] = spad_enables_rtn_3 2389 */ 2390 uint8_t global_config__spad_enables_rtn_4; 2391 /*!< 2392 info: \n 2393 - msb = 7 2394 - lsb = 0 2395 - i2c_size = 1 2396 2397 fields: \n 2398 - [7:0] = spad_enables_rtn_4 2399 */ 2400 uint8_t global_config__spad_enables_rtn_5; 2401 /*!< 2402 info: \n 2403 - msb = 7 2404 - lsb = 0 2405 - i2c_size = 1 2406 2407 fields: \n 2408 - [7:0] = spad_enables_rtn_5 2409 */ 2410 uint8_t global_config__spad_enables_rtn_6; 2411 /*!< 2412 info: \n 2413 - msb = 7 2414 - lsb = 0 2415 - i2c_size = 1 2416 2417 fields: \n 2418 - [7:0] = spad_enables_rtn_6 2419 */ 2420 uint8_t global_config__spad_enables_rtn_7; 2421 /*!< 2422 info: \n 2423 - msb = 7 2424 - lsb = 0 2425 - i2c_size = 1 2426 2427 fields: \n 2428 - [7:0] = spad_enables_rtn_7 2429 */ 2430 uint8_t global_config__spad_enables_rtn_8; 2431 /*!< 2432 info: \n 2433 - msb = 7 2434 - lsb = 0 2435 - i2c_size = 1 2436 2437 fields: \n 2438 - [7:0] = spad_enables_rtn_8 2439 */ 2440 uint8_t global_config__spad_enables_rtn_9; 2441 /*!< 2442 info: \n 2443 - msb = 7 2444 - lsb = 0 2445 - i2c_size = 1 2446 2447 fields: \n 2448 - [7:0] = spad_enables_rtn_9 2449 */ 2450 uint8_t global_config__spad_enables_rtn_10; 2451 /*!< 2452 info: \n 2453 - msb = 7 2454 - lsb = 0 2455 - i2c_size = 1 2456 2457 fields: \n 2458 - [7:0] = spad_enables_rtn_10 2459 */ 2460 uint8_t global_config__spad_enables_rtn_11; 2461 /*!< 2462 info: \n 2463 - msb = 7 2464 - lsb = 0 2465 - i2c_size = 1 2466 2467 fields: \n 2468 - [7:0] = spad_enables_rtn_11 2469 */ 2470 uint8_t global_config__spad_enables_rtn_12; 2471 /*!< 2472 info: \n 2473 - msb = 7 2474 - lsb = 0 2475 - i2c_size = 1 2476 2477 fields: \n 2478 - [7:0] = spad_enables_rtn_12 2479 */ 2480 uint8_t global_config__spad_enables_rtn_13; 2481 /*!< 2482 info: \n 2483 - msb = 7 2484 - lsb = 0 2485 - i2c_size = 1 2486 2487 fields: \n 2488 - [7:0] = spad_enables_rtn_13 2489 */ 2490 uint8_t global_config__spad_enables_rtn_14; 2491 /*!< 2492 info: \n 2493 - msb = 7 2494 - lsb = 0 2495 - i2c_size = 1 2496 2497 fields: \n 2498 - [7:0] = spad_enables_rtn_14 2499 */ 2500 uint8_t global_config__spad_enables_rtn_15; 2501 /*!< 2502 info: \n 2503 - msb = 7 2504 - lsb = 0 2505 - i2c_size = 1 2506 2507 fields: \n 2508 - [7:0] = spad_enables_rtn_15 2509 */ 2510 uint8_t global_config__spad_enables_rtn_16; 2511 /*!< 2512 info: \n 2513 - msb = 7 2514 - lsb = 0 2515 - i2c_size = 1 2516 2517 fields: \n 2518 - [7:0] = spad_enables_rtn_16 2519 */ 2520 uint8_t global_config__spad_enables_rtn_17; 2521 /*!< 2522 info: \n 2523 - msb = 7 2524 - lsb = 0 2525 - i2c_size = 1 2526 2527 fields: \n 2528 - [7:0] = spad_enables_rtn_17 2529 */ 2530 uint8_t global_config__spad_enables_rtn_18; 2531 /*!< 2532 info: \n 2533 - msb = 7 2534 - lsb = 0 2535 - i2c_size = 1 2536 2537 fields: \n 2538 - [7:0] = spad_enables_rtn_18 2539 */ 2540 uint8_t global_config__spad_enables_rtn_19; 2541 /*!< 2542 info: \n 2543 - msb = 7 2544 - lsb = 0 2545 - i2c_size = 1 2546 2547 fields: \n 2548 - [7:0] = spad_enables_rtn_19 2549 */ 2550 uint8_t global_config__spad_enables_rtn_20; 2551 /*!< 2552 info: \n 2553 - msb = 7 2554 - lsb = 0 2555 - i2c_size = 1 2556 2557 fields: \n 2558 - [7:0] = spad_enables_rtn_20 2559 */ 2560 uint8_t global_config__spad_enables_rtn_21; 2561 /*!< 2562 info: \n 2563 - msb = 7 2564 - lsb = 0 2565 - i2c_size = 1 2566 2567 fields: \n 2568 - [7:0] = spad_enables_rtn_21 2569 */ 2570 uint8_t global_config__spad_enables_rtn_22; 2571 /*!< 2572 info: \n 2573 - msb = 7 2574 - lsb = 0 2575 - i2c_size = 1 2576 2577 fields: \n 2578 - [7:0] = spad_enables_rtn_22 2579 */ 2580 uint8_t global_config__spad_enables_rtn_23; 2581 /*!< 2582 info: \n 2583 - msb = 7 2584 - lsb = 0 2585 - i2c_size = 1 2586 2587 fields: \n 2588 - [7:0] = spad_enables_rtn_23 2589 */ 2590 uint8_t global_config__spad_enables_rtn_24; 2591 /*!< 2592 info: \n 2593 - msb = 7 2594 - lsb = 0 2595 - i2c_size = 1 2596 2597 fields: \n 2598 - [7:0] = spad_enables_rtn_24 2599 */ 2600 uint8_t global_config__spad_enables_rtn_25; 2601 /*!< 2602 info: \n 2603 - msb = 7 2604 - lsb = 0 2605 - i2c_size = 1 2606 2607 fields: \n 2608 - [7:0] = spad_enables_rtn_25 2609 */ 2610 uint8_t global_config__spad_enables_rtn_26; 2611 /*!< 2612 info: \n 2613 - msb = 7 2614 - lsb = 0 2615 - i2c_size = 1 2616 2617 fields: \n 2618 - [7:0] = spad_enables_rtn_26 2619 */ 2620 uint8_t global_config__spad_enables_rtn_27; 2621 /*!< 2622 info: \n 2623 - msb = 7 2624 - lsb = 0 2625 - i2c_size = 1 2626 2627 fields: \n 2628 - [7:0] = spad_enables_rtn_27 2629 */ 2630 uint8_t global_config__spad_enables_rtn_28; 2631 /*!< 2632 info: \n 2633 - msb = 7 2634 - lsb = 0 2635 - i2c_size = 1 2636 2637 fields: \n 2638 - [7:0] = spad_enables_rtn_28 2639 */ 2640 uint8_t global_config__spad_enables_rtn_29; 2641 /*!< 2642 info: \n 2643 - msb = 7 2644 - lsb = 0 2645 - i2c_size = 1 2646 2647 fields: \n 2648 - [7:0] = spad_enables_rtn_29 2649 */ 2650 uint8_t global_config__spad_enables_rtn_30; 2651 /*!< 2652 info: \n 2653 - msb = 7 2654 - lsb = 0 2655 - i2c_size = 1 2656 2657 fields: \n 2658 - [7:0] = spad_enables_rtn_30 2659 */ 2660 uint8_t global_config__spad_enables_rtn_31; 2661 /*!< 2662 info: \n 2663 - msb = 7 2664 - lsb = 0 2665 - i2c_size = 1 2666 2667 fields: \n 2668 - [7:0] = spad_enables_rtn_31 2669 */ 2670 uint8_t roi_config__mode_roi_centre_spad; 2671 /*!< 2672 info: \n 2673 - msb = 7 2674 - lsb = 0 2675 - i2c_size = 1 2676 2677 fields: \n 2678 - [7:0] = mode_roi_center_spad 2679 */ 2680 uint8_t roi_config__mode_roi_xy_size; 2681 /*!< 2682 info: \n 2683 - msb = 7 2684 - lsb = 0 2685 - i2c_size = 1 2686 2687 fields: \n 2688 - [7:0] = mode_roi_xy_size 2689 */ 2690 } VL53L1_nvm_copy_data_t; 2691 2692 2693 /** 2694 * @struct VL53L1_prev_shadow_system_results_t 2695 * 2696 * - registers = 24 2697 * - first_index = 3792 (0x0ED0) 2698 * - last _index = 3834 (0x0EFA) 2699 * - i2c_size = 44 2700 */ 2701 2702 typedef struct { 2703 uint8_t prev_shadow_result__interrupt_status; 2704 /*!< 2705 info: \n 2706 - msb = 5 2707 - lsb = 0 2708 - i2c_size = 1 2709 2710 fields: \n 2711 - [2:0] = prev_shadow_int_status 2712 - [4:3] = prev_shadow_int_error_status 2713 - [5] = prev_shadow_gph_id_gpio_status 2714 */ 2715 uint8_t prev_shadow_result__range_status; 2716 /*!< 2717 info: \n 2718 - msb = 7 2719 - lsb = 0 2720 - i2c_size = 1 2721 2722 fields: \n 2723 - [4:0] = prev_shadow_range_status 2724 - [5] = prev_shadow_max_threshold_hit 2725 - [6] = prev_shadow_min_threshold_hit 2726 - [7] = prev_shadow_gph_id_range_status 2727 */ 2728 uint8_t prev_shadow_result__report_status; 2729 /*!< 2730 info: \n 2731 - msb = 3 2732 - lsb = 0 2733 - i2c_size = 1 2734 2735 fields: \n 2736 - [3:0] = prev_shadow_report_status 2737 */ 2738 uint8_t prev_shadow_result__stream_count; 2739 /*!< 2740 info: \n 2741 - msb = 7 2742 - lsb = 0 2743 - i2c_size = 1 2744 2745 fields: \n 2746 - [7:0] = prev_shadow_result__stream_count 2747 */ 2748 uint16_t prev_shadow_result__dss_actual_effective_spads_sd0; 2749 /*!< 2750 info: \n 2751 - msb = 15 2752 - lsb = 0 2753 - i2c_size = 2 2754 2755 fields: \n 2756 - [15:0] = prev_shadow_result__dss_actual_effective_spads_sd0 (fixed point 8.8) 2757 */ 2758 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd0; 2759 /*!< 2760 info: \n 2761 - msb = 15 2762 - lsb = 0 2763 - i2c_size = 2 2764 2765 fields: \n 2766 - [15:0] = prev_shadow_result__peak_signal_count_rate_mcps_sd0 (fixed point 9.7) 2767 */ 2768 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd0; 2769 /*!< 2770 info: \n 2771 - msb = 15 2772 - lsb = 0 2773 - i2c_size = 2 2774 2775 fields: \n 2776 - [15:0] = prev_shadow_result__ambient_count_rate_mcps_sd0 (fixed point 9.7) 2777 */ 2778 uint16_t prev_shadow_result__sigma_sd0; 2779 /*!< 2780 info: \n 2781 - msb = 15 2782 - lsb = 0 2783 - i2c_size = 2 2784 2785 fields: \n 2786 - [15:0] = prev_shadow_result__sigma_sd0 (fixed point 14.2) 2787 */ 2788 uint16_t prev_shadow_result__phase_sd0; 2789 /*!< 2790 info: \n 2791 - msb = 15 2792 - lsb = 0 2793 - i2c_size = 2 2794 2795 fields: \n 2796 - [15:0] = prev_shadow_result__phase_sd0 (fixed point 5.11) 2797 */ 2798 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd0; 2799 /*!< 2800 info: \n 2801 - msb = 15 2802 - lsb = 0 2803 - i2c_size = 2 2804 2805 fields: \n 2806 - [15:0] = prev_shadow_result__final_crosstalk_corrected_range_mm_sd0 2807 */ 2808 uint16_t prev_shadow_result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 2809 /*!< 2810 info: \n 2811 - msb = 15 2812 - lsb = 0 2813 - i2c_size = 2 2814 2815 fields: \n 2816 - [15:0] = prev_shadow_result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0 (fixed point 9.7) 2817 */ 2818 uint16_t prev_shadow_result__mm_inner_actual_effective_spads_sd0; 2819 /*!< 2820 info: \n 2821 - msb = 15 2822 - lsb = 0 2823 - i2c_size = 2 2824 2825 fields: \n 2826 - [15:0] = prev_shadow_result__mm_inner_actual_effective_spads_sd0 (fixed point 8.8) 2827 */ 2828 uint16_t prev_shadow_result__mm_outer_actual_effective_spads_sd0; 2829 /*!< 2830 info: \n 2831 - msb = 15 2832 - lsb = 0 2833 - i2c_size = 2 2834 2835 fields: \n 2836 - [15:0] = prev_shadow_result__mm_outer_actual_effective_spads_sd0 (fixed point 8.8) 2837 */ 2838 uint16_t prev_shadow_result__avg_signal_count_rate_mcps_sd0; 2839 /*!< 2840 info: \n 2841 - msb = 15 2842 - lsb = 0 2843 - i2c_size = 2 2844 2845 fields: \n 2846 - [15:0] = prev_shadow_result__avg_signal_count_rate_mcps_sd0 (fixed point 9.7) 2847 */ 2848 uint16_t prev_shadow_result__dss_actual_effective_spads_sd1; 2849 /*!< 2850 info: \n 2851 - msb = 15 2852 - lsb = 0 2853 - i2c_size = 2 2854 2855 fields: \n 2856 - [15:0] = prev_shadow_result__dss_actual_effective_spads_sd1 (fixed point 8.8) 2857 */ 2858 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd1; 2859 /*!< 2860 info: \n 2861 - msb = 15 2862 - lsb = 0 2863 - i2c_size = 2 2864 2865 fields: \n 2866 - [15:0] = prev_shadow_result__peak_signal_count_rate_mcps_sd1 (fixed point 9.7) 2867 */ 2868 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd1; 2869 /*!< 2870 info: \n 2871 - msb = 15 2872 - lsb = 0 2873 - i2c_size = 2 2874 2875 fields: \n 2876 - [15:0] = prev_shadow_result__ambient_count_rate_mcps_sd1 (fixed point 9.7) 2877 */ 2878 uint16_t prev_shadow_result__sigma_sd1; 2879 /*!< 2880 info: \n 2881 - msb = 15 2882 - lsb = 0 2883 - i2c_size = 2 2884 2885 fields: \n 2886 - [15:0] = prev_shadow_result__sigma_sd1 (fixed point 14.2) 2887 */ 2888 uint16_t prev_shadow_result__phase_sd1; 2889 /*!< 2890 info: \n 2891 - msb = 15 2892 - lsb = 0 2893 - i2c_size = 2 2894 2895 fields: \n 2896 - [15:0] = prev_shadow_result__phase_sd1 (fixed point 5.11) 2897 */ 2898 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd1; 2899 /*!< 2900 info: \n 2901 - msb = 15 2902 - lsb = 0 2903 - i2c_size = 2 2904 2905 fields: \n 2906 - [15:0] = prev_shadow_result__final_crosstalk_corrected_range_mm_sd1 2907 */ 2908 uint16_t prev_shadow_result__spare_0_sd1; 2909 /*!< 2910 info: \n 2911 - msb = 15 2912 - lsb = 0 2913 - i2c_size = 2 2914 2915 fields: \n 2916 - [15:0] = prev_shadow_result__spare_0_sd1 2917 */ 2918 uint16_t prev_shadow_result__spare_1_sd1; 2919 /*!< 2920 info: \n 2921 - msb = 15 2922 - lsb = 0 2923 - i2c_size = 2 2924 2925 fields: \n 2926 - [15:0] = prev_shadow_result__spare_1_sd1 2927 */ 2928 uint16_t prev_shadow_result__spare_2_sd1; 2929 /*!< 2930 info: \n 2931 - msb = 15 2932 - lsb = 0 2933 - i2c_size = 2 2934 2935 fields: \n 2936 - [15:0] = prev_shadow_result__spare_2_sd1 2937 */ 2938 uint16_t prev_shadow_result__spare_3_sd1; 2939 /*!< 2940 info: \n 2941 - msb = 15 2942 - lsb = 0 2943 - i2c_size = 2 2944 2945 fields: \n 2946 - [15:0] = prev_shadow_result__spare_3_sd1 2947 */ 2948 } VL53L1_prev_shadow_system_results_t; 2949 2950 2951 /** 2952 * @struct VL53L1_prev_shadow_core_results_t 2953 * 2954 * - registers = 9 2955 * - first_index = 3836 (0x0EFC) 2956 * - last _index = 3868 (0x0F1C) 2957 * - i2c_size = 33 2958 */ 2959 2960 typedef struct { 2961 uint32_t prev_shadow_result_core__ambient_window_events_sd0; 2962 /*!< 2963 info: \n 2964 - msb = 31 2965 - lsb = 0 2966 - i2c_size = 4 2967 2968 fields: \n 2969 - [31:0] = prev_shadow_result_core__ambient_window_events_sd0 2970 */ 2971 uint32_t prev_shadow_result_core__ranging_total_events_sd0; 2972 /*!< 2973 info: \n 2974 - msb = 31 2975 - lsb = 0 2976 - i2c_size = 4 2977 2978 fields: \n 2979 - [31:0] = prev_shadow_result_core__ranging_total_events_sd0 2980 */ 2981 int32_t prev_shadow_result_core__signal_total_events_sd0; 2982 /*!< 2983 info: \n 2984 - msb = 31 2985 - lsb = 0 2986 - i2c_size = 4 2987 2988 fields: \n 2989 - [31:0] = prev_shadow_result_core__signal_total_events_sd0 2990 */ 2991 uint32_t prev_shadow_result_core__total_periods_elapsed_sd0; 2992 /*!< 2993 info: \n 2994 - msb = 31 2995 - lsb = 0 2996 - i2c_size = 4 2997 2998 fields: \n 2999 - [31:0] = prev_shadow_result_core__total_periods_elapsed_sd0 3000 */ 3001 uint32_t prev_shadow_result_core__ambient_window_events_sd1; 3002 /*!< 3003 info: \n 3004 - msb = 31 3005 - lsb = 0 3006 - i2c_size = 4 3007 3008 fields: \n 3009 - [31:0] = prev_shadow_result_core__ambient_window_events_sd1 3010 */ 3011 uint32_t prev_shadow_result_core__ranging_total_events_sd1; 3012 /*!< 3013 info: \n 3014 - msb = 31 3015 - lsb = 0 3016 - i2c_size = 4 3017 3018 fields: \n 3019 - [31:0] = prev_shadow_result_core__ranging_total_events_sd1 3020 */ 3021 int32_t prev_shadow_result_core__signal_total_events_sd1; 3022 /*!< 3023 info: \n 3024 - msb = 31 3025 - lsb = 0 3026 - i2c_size = 4 3027 3028 fields: \n 3029 - [31:0] = prev_shadow_result_core__signal_total_events_sd1 3030 */ 3031 uint32_t prev_shadow_result_core__total_periods_elapsed_sd1; 3032 /*!< 3033 info: \n 3034 - msb = 31 3035 - lsb = 0 3036 - i2c_size = 4 3037 3038 fields: \n 3039 - [31:0] = prev_shadow_result_core__total_periods_elapsed_sd1 3040 */ 3041 uint8_t prev_shadow_result_core__spare_0; 3042 /*!< 3043 info: \n 3044 - msb = 7 3045 - lsb = 0 3046 - i2c_size = 1 3047 3048 fields: \n 3049 - [7:0] = prev_shadow_result_core__spare_0 3050 */ 3051 } VL53L1_prev_shadow_core_results_t; 3052 3053 3054 /** 3055 * @struct VL53L1_patch_debug_t 3056 * 3057 * - registers = 2 3058 * - first_index = 3872 (0x0F20) 3059 * - last _index = 3873 (0x0F21) 3060 * - i2c_size = 2 3061 */ 3062 3063 typedef struct { 3064 uint8_t result__debug_status; 3065 /*!< 3066 info: \n 3067 - msb = 7 3068 - lsb = 0 3069 - i2c_size = 1 3070 3071 fields: \n 3072 - [7:0] = result_debug_status 3073 */ 3074 uint8_t result__debug_stage; 3075 /*!< 3076 info: \n 3077 - msb = 7 3078 - lsb = 0 3079 - i2c_size = 1 3080 3081 fields: \n 3082 - [7:0] = result_debug_stage 3083 */ 3084 } VL53L1_patch_debug_t; 3085 3086 3087 /** 3088 * @struct VL53L1_gph_general_config_t 3089 * 3090 * - registers = 3 3091 * - first_index = 3876 (0x0F24) 3092 * - last _index = 3880 (0x0F28) 3093 * - i2c_size = 5 3094 */ 3095 3096 typedef struct { 3097 uint16_t gph__system__thresh_rate_high; 3098 /*!< 3099 info: \n 3100 - msb = 15 3101 - lsb = 0 3102 - i2c_size = 2 3103 3104 fields: \n 3105 - [15:0] = gph__system_thresh_rate_high (fixed point 9.7) 3106 */ 3107 uint16_t gph__system__thresh_rate_low; 3108 /*!< 3109 info: \n 3110 - msb = 15 3111 - lsb = 0 3112 - i2c_size = 2 3113 3114 fields: \n 3115 - [15:0] = gph__system_thresh_rate_low (fixed point 9.7) 3116 */ 3117 uint8_t gph__system__interrupt_config_gpio; 3118 /*!< 3119 info: \n 3120 - msb = 7 3121 - lsb = 0 3122 - i2c_size = 1 3123 3124 fields: \n 3125 - [1:0] = gph__int_mode_distance 3126 - [3:2] = gph__int_mode_rate 3127 - [4] = gph__int_spare 3128 - [5] = gph__int_new_measure_ready 3129 - [6] = gph__int_no_target_en 3130 - [7] = gph__int_combined_mode 3131 */ 3132 } VL53L1_gph_general_config_t; 3133 3134 3135 /** 3136 * @struct VL53L1_gph_static_config_t 3137 * 3138 * - registers = 5 3139 * - first_index = 3887 (0x0F2F) 3140 * - last _index = 3892 (0x0F34) 3141 * - i2c_size = 6 3142 */ 3143 3144 typedef struct { 3145 uint8_t gph__dss_config__roi_mode_control; 3146 /*!< 3147 info: \n 3148 - msb = 2 3149 - lsb = 0 3150 - i2c_size = 1 3151 3152 fields: \n 3153 - [1:0] = gph__dss_config__input_mode 3154 - [2] = gph__calculate_roi_enable 3155 */ 3156 uint16_t gph__dss_config__manual_effective_spads_select; 3157 /*!< 3158 info: \n 3159 - msb = 15 3160 - lsb = 0 3161 - i2c_size = 2 3162 3163 fields: \n 3164 - [15:0] = gph__dss_config__manual_effective_spads_select 3165 */ 3166 uint8_t gph__dss_config__manual_block_select; 3167 /*!< 3168 info: \n 3169 - msb = 7 3170 - lsb = 0 3171 - i2c_size = 1 3172 3173 fields: \n 3174 - [7:0] = gph__dss_config__manual_block_select 3175 */ 3176 uint8_t gph__dss_config__max_spads_limit; 3177 /*!< 3178 info: \n 3179 - msb = 7 3180 - lsb = 0 3181 - i2c_size = 1 3182 3183 fields: \n 3184 - [7:0] = gph__dss_config__max_spads_limit 3185 */ 3186 uint8_t gph__dss_config__min_spads_limit; 3187 /*!< 3188 info: \n 3189 - msb = 7 3190 - lsb = 0 3191 - i2c_size = 1 3192 3193 fields: \n 3194 - [7:0] = gph__dss_config__min_spads_limit 3195 */ 3196 } VL53L1_gph_static_config_t; 3197 3198 3199 /** 3200 * @struct VL53L1_gph_timing_config_t 3201 * 3202 * - registers = 14 3203 * - first_index = 3894 (0x0F36) 3204 * - last _index = 3909 (0x0F45) 3205 * - i2c_size = 16 3206 */ 3207 3208 typedef struct { 3209 uint8_t gph__mm_config__timeout_macrop_a_hi; 3210 /*!< 3211 info: \n 3212 - msb = 3 3213 - lsb = 0 3214 - i2c_size = 1 3215 3216 fields: \n 3217 - [3:0] = gph_mm_config__config_timeout_macrop_a_hi 3218 */ 3219 uint8_t gph__mm_config__timeout_macrop_a_lo; 3220 /*!< 3221 info: \n 3222 - msb = 7 3223 - lsb = 0 3224 - i2c_size = 1 3225 3226 fields: \n 3227 - [7:0] = gph_mm_config__config_timeout_macrop_a_lo 3228 */ 3229 uint8_t gph__mm_config__timeout_macrop_b_hi; 3230 /*!< 3231 info: \n 3232 - msb = 3 3233 - lsb = 0 3234 - i2c_size = 1 3235 3236 fields: \n 3237 - [3:0] = gph_mm_config__config_timeout_macrop_b_hi 3238 */ 3239 uint8_t gph__mm_config__timeout_macrop_b_lo; 3240 /*!< 3241 info: \n 3242 - msb = 7 3243 - lsb = 0 3244 - i2c_size = 1 3245 3246 fields: \n 3247 - [7:0] = gph_mm_config__config_timeout_macrop_b_lo 3248 */ 3249 uint8_t gph__range_config__timeout_macrop_a_hi; 3250 /*!< 3251 info: \n 3252 - msb = 3 3253 - lsb = 0 3254 - i2c_size = 1 3255 3256 fields: \n 3257 - [3:0] = gph_range_timeout_overall_periods_macrop_a_hi 3258 */ 3259 uint8_t gph__range_config__timeout_macrop_a_lo; 3260 /*!< 3261 info: \n 3262 - msb = 7 3263 - lsb = 0 3264 - i2c_size = 1 3265 3266 fields: \n 3267 - [7:0] = gph_range_timeout_overall_periods_macrop_a_lo 3268 */ 3269 uint8_t gph__range_config__vcsel_period_a; 3270 /*!< 3271 info: \n 3272 - msb = 5 3273 - lsb = 0 3274 - i2c_size = 1 3275 3276 fields: \n 3277 - [5:0] = gph_range_config__vcsel_period_a 3278 */ 3279 uint8_t gph__range_config__vcsel_period_b; 3280 /*!< 3281 info: \n 3282 - msb = 5 3283 - lsb = 0 3284 - i2c_size = 1 3285 3286 fields: \n 3287 - [5:0] = gph_range_config__vcsel_period_b 3288 */ 3289 uint8_t gph__range_config__timeout_macrop_b_hi; 3290 /*!< 3291 info: \n 3292 - msb = 3 3293 - lsb = 0 3294 - i2c_size = 1 3295 3296 fields: \n 3297 - [3:0] = gph_range_timeout_overall_periods_macrop_b_hi 3298 */ 3299 uint8_t gph__range_config__timeout_macrop_b_lo; 3300 /*!< 3301 info: \n 3302 - msb = 7 3303 - lsb = 0 3304 - i2c_size = 1 3305 3306 fields: \n 3307 - [7:0] = gph_range_timeout_overall_periods_macrop_b_lo 3308 */ 3309 uint16_t gph__range_config__sigma_thresh; 3310 /*!< 3311 info: \n 3312 - msb = 15 3313 - lsb = 0 3314 - i2c_size = 2 3315 3316 fields: \n 3317 - [15:0] = gph_range_config__sigma_thresh (fixed point 14.2) 3318 */ 3319 uint16_t gph__range_config__min_count_rate_rtn_limit_mcps; 3320 /*!< 3321 info: \n 3322 - msb = 15 3323 - lsb = 0 3324 - i2c_size = 2 3325 3326 fields: \n 3327 - [15:0] = gph_range_config__min_count_rate_rtn_limit_mcps (fixed point 9.7) 3328 */ 3329 uint8_t gph__range_config__valid_phase_low; 3330 /*!< 3331 info: \n 3332 - msb = 7 3333 - lsb = 0 3334 - i2c_size = 1 3335 3336 fields: \n 3337 - [7:0] = gph_range_config__valid_phase_low (fixed point 5.3) 3338 */ 3339 uint8_t gph__range_config__valid_phase_high; 3340 /*!< 3341 info: \n 3342 - msb = 7 3343 - lsb = 0 3344 - i2c_size = 1 3345 3346 fields: \n 3347 - [7:0] = gph_range_config__valid_phase_high (fixed point 5.3) 3348 */ 3349 } VL53L1_gph_timing_config_t; 3350 3351 3352 /** 3353 * @struct VL53L1_fw_internal_t 3354 * 3355 * - registers = 2 3356 * - first_index = 3910 (0x0F46) 3357 * - last _index = 3911 (0x0F47) 3358 * - i2c_size = 2 3359 */ 3360 3361 typedef struct { 3362 uint8_t firmware__internal_stream_count_div; 3363 /*!< 3364 info: \n 3365 - msb = 7 3366 - lsb = 0 3367 - i2c_size = 1 3368 3369 fields: \n 3370 - [7:0] = fw__internal_stream_count_div 3371 */ 3372 uint8_t firmware__internal_stream_counter_val; 3373 /*!< 3374 info: \n 3375 - msb = 7 3376 - lsb = 0 3377 - i2c_size = 1 3378 3379 fields: \n 3380 - [7:0] = fw__internal_stream_counter_val 3381 */ 3382 } VL53L1_fw_internal_t; 3383 3384 3385 /** 3386 * @struct VL53L1_patch_results_t 3387 * 3388 * - registers = 60 3389 * - first_index = 3924 (0x0F54) 3390 * - last _index = 4012 (0x0FAC) 3391 * - i2c_size = 90 3392 */ 3393 3394 typedef struct { 3395 uint8_t dss_calc__roi_ctrl; 3396 /*!< 3397 info: \n 3398 - msb = 1 3399 - lsb = 0 3400 - i2c_size = 1 3401 3402 fields: \n 3403 - [0] = dss_calc__roi_intersect_enable 3404 - [1] = dss_calc__roi_subtract_enable 3405 */ 3406 uint8_t dss_calc__spare_1; 3407 /*!< 3408 info: \n 3409 - msb = 7 3410 - lsb = 0 3411 - i2c_size = 1 3412 3413 fields: \n 3414 - [7:0] = dss_calc__spare_1 3415 */ 3416 uint8_t dss_calc__spare_2; 3417 /*!< 3418 info: \n 3419 - msb = 7 3420 - lsb = 0 3421 - i2c_size = 1 3422 3423 fields: \n 3424 - [7:0] = dss_calc__spare_2 3425 */ 3426 uint8_t dss_calc__spare_3; 3427 /*!< 3428 info: \n 3429 - msb = 7 3430 - lsb = 0 3431 - i2c_size = 1 3432 3433 fields: \n 3434 - [7:0] = dss_calc__spare_3 3435 */ 3436 uint8_t dss_calc__spare_4; 3437 /*!< 3438 info: \n 3439 - msb = 7 3440 - lsb = 0 3441 - i2c_size = 1 3442 3443 fields: \n 3444 - [7:0] = dss_calc__spare_4 3445 */ 3446 uint8_t dss_calc__spare_5; 3447 /*!< 3448 info: \n 3449 - msb = 7 3450 - lsb = 0 3451 - i2c_size = 1 3452 3453 fields: \n 3454 - [7:0] = dss_calc__spare_5 3455 */ 3456 uint8_t dss_calc__spare_6; 3457 /*!< 3458 info: \n 3459 - msb = 7 3460 - lsb = 0 3461 - i2c_size = 1 3462 3463 fields: \n 3464 - [7:0] = dss_calc__spare_6 3465 */ 3466 uint8_t dss_calc__spare_7; 3467 /*!< 3468 info: \n 3469 - msb = 7 3470 - lsb = 0 3471 - i2c_size = 1 3472 3473 fields: \n 3474 - [7:0] = dss_calc__spare_7 3475 */ 3476 uint8_t dss_calc__user_roi_spad_en_0; 3477 /*!< 3478 info: \n 3479 - msb = 7 3480 - lsb = 0 3481 - i2c_size = 1 3482 3483 fields: \n 3484 - [7:0] = dss_calc__user_roi_spad_en_0 3485 */ 3486 uint8_t dss_calc__user_roi_spad_en_1; 3487 /*!< 3488 info: \n 3489 - msb = 7 3490 - lsb = 0 3491 - i2c_size = 1 3492 3493 fields: \n 3494 - [7:0] = dss_calc__user_roi_spad_en_1 3495 */ 3496 uint8_t dss_calc__user_roi_spad_en_2; 3497 /*!< 3498 info: \n 3499 - msb = 7 3500 - lsb = 0 3501 - i2c_size = 1 3502 3503 fields: \n 3504 - [7:0] = dss_calc__user_roi_spad_en_2 3505 */ 3506 uint8_t dss_calc__user_roi_spad_en_3; 3507 /*!< 3508 info: \n 3509 - msb = 7 3510 - lsb = 0 3511 - i2c_size = 1 3512 3513 fields: \n 3514 - [7:0] = dss_calc__user_roi_spad_en_3 3515 */ 3516 uint8_t dss_calc__user_roi_spad_en_4; 3517 /*!< 3518 info: \n 3519 - msb = 7 3520 - lsb = 0 3521 - i2c_size = 1 3522 3523 fields: \n 3524 - [7:0] = dss_calc__user_roi_spad_en_4 3525 */ 3526 uint8_t dss_calc__user_roi_spad_en_5; 3527 /*!< 3528 info: \n 3529 - msb = 7 3530 - lsb = 0 3531 - i2c_size = 1 3532 3533 fields: \n 3534 - [7:0] = dss_calc__user_roi_spad_en_5 3535 */ 3536 uint8_t dss_calc__user_roi_spad_en_6; 3537 /*!< 3538 info: \n 3539 - msb = 7 3540 - lsb = 0 3541 - i2c_size = 1 3542 3543 fields: \n 3544 - [7:0] = dss_calc__user_roi_spad_en_6 3545 */ 3546 uint8_t dss_calc__user_roi_spad_en_7; 3547 /*!< 3548 info: \n 3549 - msb = 7 3550 - lsb = 0 3551 - i2c_size = 1 3552 3553 fields: \n 3554 - [7:0] = dss_calc__user_roi_spad_en_7 3555 */ 3556 uint8_t dss_calc__user_roi_spad_en_8; 3557 /*!< 3558 info: \n 3559 - msb = 7 3560 - lsb = 0 3561 - i2c_size = 1 3562 3563 fields: \n 3564 - [7:0] = dss_calc__user_roi_spad_en_8 3565 */ 3566 uint8_t dss_calc__user_roi_spad_en_9; 3567 /*!< 3568 info: \n 3569 - msb = 7 3570 - lsb = 0 3571 - i2c_size = 1 3572 3573 fields: \n 3574 - [7:0] = dss_calc__user_roi_spad_en_9 3575 */ 3576 uint8_t dss_calc__user_roi_spad_en_10; 3577 /*!< 3578 info: \n 3579 - msb = 7 3580 - lsb = 0 3581 - i2c_size = 1 3582 3583 fields: \n 3584 - [7:0] = dss_calc__user_roi_spad_en_10 3585 */ 3586 uint8_t dss_calc__user_roi_spad_en_11; 3587 /*!< 3588 info: \n 3589 - msb = 7 3590 - lsb = 0 3591 - i2c_size = 1 3592 3593 fields: \n 3594 - [7:0] = dss_calc__user_roi_spad_en_11 3595 */ 3596 uint8_t dss_calc__user_roi_spad_en_12; 3597 /*!< 3598 info: \n 3599 - msb = 7 3600 - lsb = 0 3601 - i2c_size = 1 3602 3603 fields: \n 3604 - [7:0] = dss_calc__user_roi_spad_en_12 3605 */ 3606 uint8_t dss_calc__user_roi_spad_en_13; 3607 /*!< 3608 info: \n 3609 - msb = 7 3610 - lsb = 0 3611 - i2c_size = 1 3612 3613 fields: \n 3614 - [7:0] = dss_calc__user_roi_spad_en_13 3615 */ 3616 uint8_t dss_calc__user_roi_spad_en_14; 3617 /*!< 3618 info: \n 3619 - msb = 7 3620 - lsb = 0 3621 - i2c_size = 1 3622 3623 fields: \n 3624 - [7:0] = dss_calc__user_roi_spad_en_14 3625 */ 3626 uint8_t dss_calc__user_roi_spad_en_15; 3627 /*!< 3628 info: \n 3629 - msb = 7 3630 - lsb = 0 3631 - i2c_size = 1 3632 3633 fields: \n 3634 - [7:0] = dss_calc__user_roi_spad_en_15 3635 */ 3636 uint8_t dss_calc__user_roi_spad_en_16; 3637 /*!< 3638 info: \n 3639 - msb = 7 3640 - lsb = 0 3641 - i2c_size = 1 3642 3643 fields: \n 3644 - [7:0] = dss_calc__user_roi_spad_en_16 3645 */ 3646 uint8_t dss_calc__user_roi_spad_en_17; 3647 /*!< 3648 info: \n 3649 - msb = 7 3650 - lsb = 0 3651 - i2c_size = 1 3652 3653 fields: \n 3654 - [7:0] = dss_calc__user_roi_spad_en_17 3655 */ 3656 uint8_t dss_calc__user_roi_spad_en_18; 3657 /*!< 3658 info: \n 3659 - msb = 7 3660 - lsb = 0 3661 - i2c_size = 1 3662 3663 fields: \n 3664 - [7:0] = dss_calc__user_roi_spad_en_18 3665 */ 3666 uint8_t dss_calc__user_roi_spad_en_19; 3667 /*!< 3668 info: \n 3669 - msb = 7 3670 - lsb = 0 3671 - i2c_size = 1 3672 3673 fields: \n 3674 - [7:0] = dss_calc__user_roi_spad_en_19 3675 */ 3676 uint8_t dss_calc__user_roi_spad_en_20; 3677 /*!< 3678 info: \n 3679 - msb = 7 3680 - lsb = 0 3681 - i2c_size = 1 3682 3683 fields: \n 3684 - [7:0] = dss_calc__user_roi_spad_en_20 3685 */ 3686 uint8_t dss_calc__user_roi_spad_en_21; 3687 /*!< 3688 info: \n 3689 - msb = 7 3690 - lsb = 0 3691 - i2c_size = 1 3692 3693 fields: \n 3694 - [7:0] = dss_calc__user_roi_spad_en_21 3695 */ 3696 uint8_t dss_calc__user_roi_spad_en_22; 3697 /*!< 3698 info: \n 3699 - msb = 7 3700 - lsb = 0 3701 - i2c_size = 1 3702 3703 fields: \n 3704 - [7:0] = dss_calc__user_roi_spad_en_22 3705 */ 3706 uint8_t dss_calc__user_roi_spad_en_23; 3707 /*!< 3708 info: \n 3709 - msb = 7 3710 - lsb = 0 3711 - i2c_size = 1 3712 3713 fields: \n 3714 - [7:0] = dss_calc__user_roi_spad_en_23 3715 */ 3716 uint8_t dss_calc__user_roi_spad_en_24; 3717 /*!< 3718 info: \n 3719 - msb = 7 3720 - lsb = 0 3721 - i2c_size = 1 3722 3723 fields: \n 3724 - [7:0] = dss_calc__user_roi_spad_en_24 3725 */ 3726 uint8_t dss_calc__user_roi_spad_en_25; 3727 /*!< 3728 info: \n 3729 - msb = 7 3730 - lsb = 0 3731 - i2c_size = 1 3732 3733 fields: \n 3734 - [7:0] = dss_calc__user_roi_spad_en_25 3735 */ 3736 uint8_t dss_calc__user_roi_spad_en_26; 3737 /*!< 3738 info: \n 3739 - msb = 7 3740 - lsb = 0 3741 - i2c_size = 1 3742 3743 fields: \n 3744 - [7:0] = dss_calc__user_roi_spad_en_26 3745 */ 3746 uint8_t dss_calc__user_roi_spad_en_27; 3747 /*!< 3748 info: \n 3749 - msb = 7 3750 - lsb = 0 3751 - i2c_size = 1 3752 3753 fields: \n 3754 - [7:0] = dss_calc__user_roi_spad_en_27 3755 */ 3756 uint8_t dss_calc__user_roi_spad_en_28; 3757 /*!< 3758 info: \n 3759 - msb = 7 3760 - lsb = 0 3761 - i2c_size = 1 3762 3763 fields: \n 3764 - [7:0] = dss_calc__user_roi_spad_en_28 3765 */ 3766 uint8_t dss_calc__user_roi_spad_en_29; 3767 /*!< 3768 info: \n 3769 - msb = 7 3770 - lsb = 0 3771 - i2c_size = 1 3772 3773 fields: \n 3774 - [7:0] = dss_calc__user_roi_spad_en_29 3775 */ 3776 uint8_t dss_calc__user_roi_spad_en_30; 3777 /*!< 3778 info: \n 3779 - msb = 7 3780 - lsb = 0 3781 - i2c_size = 1 3782 3783 fields: \n 3784 - [7:0] = dss_calc__user_roi_spad_en_30 3785 */ 3786 uint8_t dss_calc__user_roi_spad_en_31; 3787 /*!< 3788 info: \n 3789 - msb = 7 3790 - lsb = 0 3791 - i2c_size = 1 3792 3793 fields: \n 3794 - [7:0] = dss_calc__user_roi_spad_en_31 3795 */ 3796 uint8_t dss_calc__user_roi_0; 3797 /*!< 3798 info: \n 3799 - msb = 7 3800 - lsb = 0 3801 - i2c_size = 1 3802 3803 fields: \n 3804 - [7:0] = dss_calc__user_roi_0 3805 */ 3806 uint8_t dss_calc__user_roi_1; 3807 /*!< 3808 info: \n 3809 - msb = 7 3810 - lsb = 0 3811 - i2c_size = 1 3812 3813 fields: \n 3814 - [7:0] = dss_calc__user_roi_1 3815 */ 3816 uint8_t dss_calc__mode_roi_0; 3817 /*!< 3818 info: \n 3819 - msb = 7 3820 - lsb = 0 3821 - i2c_size = 1 3822 3823 fields: \n 3824 - [7:0] = dss_calc__mode_roi_0 3825 */ 3826 uint8_t dss_calc__mode_roi_1; 3827 /*!< 3828 info: \n 3829 - msb = 7 3830 - lsb = 0 3831 - i2c_size = 1 3832 3833 fields: \n 3834 - [7:0] = dss_calc__mode_roi_1 3835 */ 3836 uint8_t sigma_estimator_calc__spare_0; 3837 /*!< 3838 info: \n 3839 - msb = 7 3840 - lsb = 0 3841 - i2c_size = 1 3842 3843 fields: \n 3844 - [7:0] = sigma_estimator_calc__spare_0 3845 */ 3846 uint16_t vhv_result__peak_signal_rate_mcps; 3847 /*!< 3848 info: \n 3849 - msb = 15 3850 - lsb = 0 3851 - i2c_size = 2 3852 3853 fields: \n 3854 - [15:0] = vhv_result__peak_signal_rate_mcps 3855 */ 3856 uint32_t vhv_result__signal_total_events_ref; 3857 /*!< 3858 info: \n 3859 - msb = 31 3860 - lsb = 0 3861 - i2c_size = 4 3862 3863 fields: \n 3864 - [31:0] = vhv_result__signal_total_events_ref 3865 */ 3866 uint16_t phasecal_result__phase_output_ref; 3867 /*!< 3868 info: \n 3869 - msb = 15 3870 - lsb = 0 3871 - i2c_size = 2 3872 3873 fields: \n 3874 - [15:0] = phasecal_result__normalised_phase_ref 3875 */ 3876 uint16_t dss_result__total_rate_per_spad; 3877 /*!< 3878 info: \n 3879 - msb = 15 3880 - lsb = 0 3881 - i2c_size = 2 3882 3883 fields: \n 3884 - [15:0] = dss_result__total_rate_per_spad 3885 */ 3886 uint8_t dss_result__enabled_blocks; 3887 /*!< 3888 info: \n 3889 - msb = 7 3890 - lsb = 0 3891 - i2c_size = 1 3892 3893 fields: \n 3894 - [7:0] = dss_result__enabled_blocks 3895 */ 3896 uint16_t dss_result__num_requested_spads; 3897 /*!< 3898 info: \n 3899 - msb = 15 3900 - lsb = 0 3901 - i2c_size = 2 3902 3903 fields: \n 3904 - [15:0] = dss_result__num_requested_spads (fixed point 8.8) 3905 */ 3906 uint16_t mm_result__inner_intersection_rate; 3907 /*!< 3908 info: \n 3909 - msb = 15 3910 - lsb = 0 3911 - i2c_size = 2 3912 3913 fields: \n 3914 - [15:0] = mm_result__inner_intersection_rate 3915 */ 3916 uint16_t mm_result__outer_complement_rate; 3917 /*!< 3918 info: \n 3919 - msb = 15 3920 - lsb = 0 3921 - i2c_size = 2 3922 3923 fields: \n 3924 - [15:0] = mm_result__outer_complement_rate 3925 */ 3926 uint16_t mm_result__total_offset; 3927 /*!< 3928 info: \n 3929 - msb = 15 3930 - lsb = 0 3931 - i2c_size = 2 3932 3933 fields: \n 3934 - [15:0] = mm_result__total_offset 3935 */ 3936 uint32_t xtalk_calc__xtalk_for_enabled_spads; 3937 /*!< 3938 info: \n 3939 - msb = 23 3940 - lsb = 0 3941 - i2c_size = 4 3942 3943 fields: \n 3944 - [23:0] = xtalk_calc__xtalk_for_enabled_spads (fixed point 11.13) 3945 */ 3946 uint32_t xtalk_result__avg_xtalk_user_roi_kcps; 3947 /*!< 3948 info: \n 3949 - msb = 23 3950 - lsb = 0 3951 - i2c_size = 4 3952 3953 fields: \n 3954 - [23:0] = xtalk_result__avg_xtalk_user_roi_kcps (fixed point 11.13) 3955 */ 3956 uint32_t xtalk_result__avg_xtalk_mm_inner_roi_kcps; 3957 /*!< 3958 info: \n 3959 - msb = 23 3960 - lsb = 0 3961 - i2c_size = 4 3962 3963 fields: \n 3964 - [23:0] = xtalk_result__avg_xtalk_mm_inner_roi_kcps (fixed point 11.13) 3965 */ 3966 uint32_t xtalk_result__avg_xtalk_mm_outer_roi_kcps; 3967 /*!< 3968 info: \n 3969 - msb = 23 3970 - lsb = 0 3971 - i2c_size = 4 3972 3973 fields: \n 3974 - [23:0] = xtalk_result__avg_xtalk_mm_outer_roi_kcps (fixed point 11.13) 3975 */ 3976 uint32_t range_result__accum_phase; 3977 /*!< 3978 info: \n 3979 - msb = 31 3980 - lsb = 0 3981 - i2c_size = 4 3982 3983 fields: \n 3984 - [31:0] = range_result__accum_phase 3985 */ 3986 uint16_t range_result__offset_corrected_range; 3987 /*!< 3988 info: \n 3989 - msb = 15 3990 - lsb = 0 3991 - i2c_size = 2 3992 3993 fields: \n 3994 - [15:0] = range_result__offset_corrected_range 3995 */ 3996 } VL53L1_patch_results_t; 3997 3998 3999 /** 4000 * @struct VL53L1_shadow_system_results_t 4001 * 4002 * - registers = 28 4003 * - first_index = 4014 (0x0FAE) 4004 * - last _index = 4095 (0x0FFF) 4005 * - i2c_size = 82 4006 */ 4007 4008 typedef struct { 4009 uint8_t shadow_phasecal_result__vcsel_start; 4010 /*!< 4011 info: \n 4012 - msb = 7 4013 - lsb = 0 4014 - i2c_size = 1 4015 4016 fields: \n 4017 - [7:0] = shadow_phasecal_result__vcsel_start 4018 */ 4019 uint8_t shadow_result__interrupt_status; 4020 /*!< 4021 info: \n 4022 - msb = 5 4023 - lsb = 0 4024 - i2c_size = 1 4025 4026 fields: \n 4027 - [2:0] = shadow_int_status 4028 - [4:3] = shadow_int_error_status 4029 - [5] = shadow_gph_id_gpio_status 4030 */ 4031 uint8_t shadow_result__range_status; 4032 /*!< 4033 info: \n 4034 - msb = 7 4035 - lsb = 0 4036 - i2c_size = 1 4037 4038 fields: \n 4039 - [4:0] = shadow_range_status 4040 - [5] = shadow_max_threshold_hit 4041 - [6] = shadow_min_threshold_hit 4042 - [7] = shadow_gph_id_range_status 4043 */ 4044 uint8_t shadow_result__report_status; 4045 /*!< 4046 info: \n 4047 - msb = 3 4048 - lsb = 0 4049 - i2c_size = 1 4050 4051 fields: \n 4052 - [3:0] = shadow_report_status 4053 */ 4054 uint8_t shadow_result__stream_count; 4055 /*!< 4056 info: \n 4057 - msb = 7 4058 - lsb = 0 4059 - i2c_size = 1 4060 4061 fields: \n 4062 - [7:0] = shadow_result__stream_count 4063 */ 4064 uint16_t shadow_result__dss_actual_effective_spads_sd0; 4065 /*!< 4066 info: \n 4067 - msb = 15 4068 - lsb = 0 4069 - i2c_size = 2 4070 4071 fields: \n 4072 - [15:0] = shadow_result__dss_actual_effective_spads_sd0 (fixed point 8.8) 4073 */ 4074 uint16_t shadow_result__peak_signal_count_rate_mcps_sd0; 4075 /*!< 4076 info: \n 4077 - msb = 15 4078 - lsb = 0 4079 - i2c_size = 2 4080 4081 fields: \n 4082 - [15:0] = shadow_result__peak_signal_count_rate_mcps_sd0 (fixed point 9.7) 4083 */ 4084 uint16_t shadow_result__ambient_count_rate_mcps_sd0; 4085 /*!< 4086 info: \n 4087 - msb = 15 4088 - lsb = 0 4089 - i2c_size = 2 4090 4091 fields: \n 4092 - [15:0] = shadow_result__ambient_count_rate_mcps_sd0 (fixed point 9.7) 4093 */ 4094 uint16_t shadow_result__sigma_sd0; 4095 /*!< 4096 info: \n 4097 - msb = 15 4098 - lsb = 0 4099 - i2c_size = 2 4100 4101 fields: \n 4102 - [15:0] = shadow_result__sigma_sd0 (fixed point 14.2) 4103 */ 4104 uint16_t shadow_result__phase_sd0; 4105 /*!< 4106 info: \n 4107 - msb = 15 4108 - lsb = 0 4109 - i2c_size = 2 4110 4111 fields: \n 4112 - [15:0] = shadow_result__phase_sd0 (fixed point 5.11) 4113 */ 4114 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd0; 4115 /*!< 4116 info: \n 4117 - msb = 15 4118 - lsb = 0 4119 - i2c_size = 2 4120 4121 fields: \n 4122 - [15:0] = shadow_result__final_crosstalk_corrected_range_mm_sd0 4123 */ 4124 uint16_t shadow_result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 4125 /*!< 4126 info: \n 4127 - msb = 15 4128 - lsb = 0 4129 - i2c_size = 2 4130 4131 fields: \n 4132 - [15:0] = shadow_result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0 (fixed point 9.7) 4133 */ 4134 uint16_t shadow_result__mm_inner_actual_effective_spads_sd0; 4135 /*!< 4136 info: \n 4137 - msb = 15 4138 - lsb = 0 4139 - i2c_size = 2 4140 4141 fields: \n 4142 - [15:0] = shadow_result__mm_inner_actual_effective_spads_sd0 (fixed point 8.8) 4143 */ 4144 uint16_t shadow_result__mm_outer_actual_effective_spads_sd0; 4145 /*!< 4146 info: \n 4147 - msb = 15 4148 - lsb = 0 4149 - i2c_size = 2 4150 4151 fields: \n 4152 - [15:0] = shadow_result__mm_outer_actual_effective_spads_sd0 (fixed point 8.8) 4153 */ 4154 uint16_t shadow_result__avg_signal_count_rate_mcps_sd0; 4155 /*!< 4156 info: \n 4157 - msb = 15 4158 - lsb = 0 4159 - i2c_size = 2 4160 4161 fields: \n 4162 - [15:0] = shadow_result__avg_signal_count_rate_mcps_sd0 (fixed point 9.7) 4163 */ 4164 uint16_t shadow_result__dss_actual_effective_spads_sd1; 4165 /*!< 4166 info: \n 4167 - msb = 15 4168 - lsb = 0 4169 - i2c_size = 2 4170 4171 fields: \n 4172 - [15:0] = shadow_result__dss_actual_effective_spads_sd1 (fixed point 8.8) 4173 */ 4174 uint16_t shadow_result__peak_signal_count_rate_mcps_sd1; 4175 /*!< 4176 info: \n 4177 - msb = 15 4178 - lsb = 0 4179 - i2c_size = 2 4180 4181 fields: \n 4182 - [15:0] = shadow_result__peak_signal_count_rate_mcps_sd1 (fixed point 9.7) 4183 */ 4184 uint16_t shadow_result__ambient_count_rate_mcps_sd1; 4185 /*!< 4186 info: \n 4187 - msb = 15 4188 - lsb = 0 4189 - i2c_size = 2 4190 4191 fields: \n 4192 - [15:0] = shadow_result__ambient_count_rate_mcps_sd1 (fixed point 9.7) 4193 */ 4194 uint16_t shadow_result__sigma_sd1; 4195 /*!< 4196 info: \n 4197 - msb = 15 4198 - lsb = 0 4199 - i2c_size = 2 4200 4201 fields: \n 4202 - [15:0] = shadow_result__sigma_sd1 (fixed point 14.2) 4203 */ 4204 uint16_t shadow_result__phase_sd1; 4205 /*!< 4206 info: \n 4207 - msb = 15 4208 - lsb = 0 4209 - i2c_size = 2 4210 4211 fields: \n 4212 - [15:0] = shadow_result__phase_sd1 (fixed point 5.11) 4213 */ 4214 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd1; 4215 /*!< 4216 info: \n 4217 - msb = 15 4218 - lsb = 0 4219 - i2c_size = 2 4220 4221 fields: \n 4222 - [15:0] = shadow_result__final_crosstalk_corrected_range_mm_sd1 4223 */ 4224 uint16_t shadow_result__spare_0_sd1; 4225 /*!< 4226 info: \n 4227 - msb = 15 4228 - lsb = 0 4229 - i2c_size = 2 4230 4231 fields: \n 4232 - [15:0] = shadow_result__spare_0_sd1 4233 */ 4234 uint16_t shadow_result__spare_1_sd1; 4235 /*!< 4236 info: \n 4237 - msb = 15 4238 - lsb = 0 4239 - i2c_size = 2 4240 4241 fields: \n 4242 - [15:0] = shadow_result__spare_1_sd1 4243 */ 4244 uint16_t shadow_result__spare_2_sd1; 4245 /*!< 4246 info: \n 4247 - msb = 15 4248 - lsb = 0 4249 - i2c_size = 2 4250 4251 fields: \n 4252 - [15:0] = shadow_result__spare_2_sd1 4253 */ 4254 uint8_t shadow_result__spare_3_sd1; 4255 /*!< 4256 info: \n 4257 - msb = 7 4258 - lsb = 0 4259 - i2c_size = 1 4260 4261 fields: \n 4262 - [7:0] = shadow_result__spare_3_sd1 4263 */ 4264 uint8_t shadow_result__thresh_info; 4265 /*!< 4266 info: \n 4267 - msb = 7 4268 - lsb = 0 4269 - i2c_size = 1 4270 4271 fields: \n 4272 - [3:0] = shadow_result__distance_int_info 4273 - [7:4] = shadow_result__rate_int_info 4274 */ 4275 uint8_t shadow_phasecal_result__reference_phase_hi; 4276 /*!< 4277 info: \n 4278 - msb = 7 4279 - lsb = 0 4280 - i2c_size = 1 4281 4282 fields: \n 4283 - [7:0] = shadow_phasecal_result__reference_phase_hi 4284 */ 4285 uint8_t shadow_phasecal_result__reference_phase_lo; 4286 /*!< 4287 info: \n 4288 - msb = 7 4289 - lsb = 0 4290 - i2c_size = 1 4291 4292 fields: \n 4293 - [7:0] = shadow_phasecal_result__reference_phase_lo 4294 */ 4295 } VL53L1_shadow_system_results_t; 4296 4297 4298 /** 4299 * @struct VL53L1_shadow_core_results_t 4300 * 4301 * - registers = 9 4302 * - first_index = 4060 (0x0FDC) 4303 * - last _index = 4092 (0x0FFC) 4304 * - i2c_size = 33 4305 */ 4306 4307 typedef struct { 4308 uint32_t shadow_result_core__ambient_window_events_sd0; 4309 /*!< 4310 info: \n 4311 - msb = 31 4312 - lsb = 0 4313 - i2c_size = 4 4314 4315 fields: \n 4316 - [31:0] = shadow_result_core__ambient_window_events_sd0 4317 */ 4318 uint32_t shadow_result_core__ranging_total_events_sd0; 4319 /*!< 4320 info: \n 4321 - msb = 31 4322 - lsb = 0 4323 - i2c_size = 4 4324 4325 fields: \n 4326 - [31:0] = shadow_result_core__ranging_total_events_sd0 4327 */ 4328 int32_t shadow_result_core__signal_total_events_sd0; 4329 /*!< 4330 info: \n 4331 - msb = 31 4332 - lsb = 0 4333 - i2c_size = 4 4334 4335 fields: \n 4336 - [31:0] = shadow_result_core__signal_total_events_sd0 4337 */ 4338 uint32_t shadow_result_core__total_periods_elapsed_sd0; 4339 /*!< 4340 info: \n 4341 - msb = 31 4342 - lsb = 0 4343 - i2c_size = 4 4344 4345 fields: \n 4346 - [31:0] = shadow_result_core__total_periods_elapsed_sd0 4347 */ 4348 uint32_t shadow_result_core__ambient_window_events_sd1; 4349 /*!< 4350 info: \n 4351 - msb = 31 4352 - lsb = 0 4353 - i2c_size = 4 4354 4355 fields: \n 4356 - [31:0] = shadow_result_core__ambient_window_events_sd1 4357 */ 4358 uint32_t shadow_result_core__ranging_total_events_sd1; 4359 /*!< 4360 info: \n 4361 - msb = 31 4362 - lsb = 0 4363 - i2c_size = 4 4364 4365 fields: \n 4366 - [31:0] = shadow_result_core__ranging_total_events_sd1 4367 */ 4368 int32_t shadow_result_core__signal_total_events_sd1; 4369 /*!< 4370 info: \n 4371 - msb = 31 4372 - lsb = 0 4373 - i2c_size = 4 4374 4375 fields: \n 4376 - [31:0] = shadow_result_core__signal_total_events_sd1 4377 */ 4378 uint32_t shadow_result_core__total_periods_elapsed_sd1; 4379 /*!< 4380 info: \n 4381 - msb = 31 4382 - lsb = 0 4383 - i2c_size = 4 4384 4385 fields: \n 4386 - [31:0] = shadow_result_core__total_periods_elapsed_sd1 4387 */ 4388 uint8_t shadow_result_core__spare_0; 4389 /*!< 4390 info: \n 4391 - msb = 7 4392 - lsb = 0 4393 - i2c_size = 1 4394 4395 fields: \n 4396 - [7:0] = shadow_result_core__spare_0 4397 */ 4398 } VL53L1_shadow_core_results_t; 4399 4400 4401 #endif 4402 4403
