1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define PLATFORM_MASK GENMASK(27U, 24U) 16 #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17 18 /* number of interrupt handlers. increase as required */ 19 #define MAX_INTR_EL3 2 20 /* List all consoles */ 21 #define VERSAL_CONSOLE_ID_pl011 1 22 #define VERSAL_CONSOLE_ID_pl011_0 1 23 #define VERSAL_CONSOLE_ID_pl011_1 2 24 #define VERSAL_CONSOLE_ID_dcc 3 25 26 #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 27 28 /* List all supported platforms */ 29 #define VERSAL_PLATFORM_ID_versal_virt 1 30 #define VERSAL_PLATFORM_ID_spp_itr6 2 31 #define VERSAL_PLATFORM_ID_emu_itr6 3 32 #define VERSAL_PLATFORM_ID_silicon 4 33 34 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 35 36 /* Firmware Image Package */ 37 #define VERSAL_PRIMARY_CPU 0 38 39 /******************************************************************************* 40 * memory map related constants 41 ******************************************************************************/ 42 #define DEVICE0_BASE 0xFF000000 43 #define DEVICE0_SIZE 0x00E00000 44 #define DEVICE1_BASE 0xF9000000 45 #define DEVICE1_SIZE 0x00800000 46 47 /******************************************************************************* 48 * IRQ constants 49 ******************************************************************************/ 50 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 51 #define ARM_IRQ_SEC_PHY_TIMER 29 52 53 /******************************************************************************* 54 * CCI-400 related constants 55 ******************************************************************************/ 56 #define PLAT_ARM_CCI_BASE 0xFD000000 57 #define PLAT_ARM_CCI_SIZE 0x00100000 58 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 59 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 60 61 /******************************************************************************* 62 * UART related constants 63 ******************************************************************************/ 64 #define VERSAL_UART0_BASE 0xFF000000 65 #define VERSAL_UART1_BASE 0xFF010000 66 67 #if CONSOLE_IS(pl011) || CONSOLE_IS(dcc) 68 # define UART_BASE VERSAL_UART0_BASE 69 #elif CONSOLE_IS(pl011_1) 70 # define UART_BASE VERSAL_UART1_BASE 71 #else 72 # error "invalid VERSAL_CONSOLE" 73 #endif 74 75 /******************************************************************************* 76 * Platform related constants 77 ******************************************************************************/ 78 #if VERSAL_PLATFORM_IS(versal_virt) 79 # define PLATFORM_NAME "Versal Virt" 80 # define UART_CLOCK 25000000 81 # define UART_BAUDRATE 115200 82 # define VERSAL_CPU_CLOCK 2720000 83 #elif VERSAL_PLATFORM_IS(silicon) 84 # define PLATFORM_NAME "Versal Silicon" 85 # define UART_CLOCK 100000000 86 # define UART_BAUDRATE 115200 87 # define VERSAL_CPU_CLOCK 100000000 88 #elif VERSAL_PLATFORM_IS(spp_itr6) 89 # define PLATFORM_NAME "SPP ITR6" 90 # define UART_CLOCK 25000000 91 # define UART_BAUDRATE 115200 92 # define VERSAL_CPU_CLOCK 2720000 93 #elif VERSAL_PLATFORM_IS(emu_itr6) 94 # define PLATFORM_NAME "EMU ITR6" 95 # define UART_CLOCK 212000 96 # define UART_BAUDRATE 9600 97 # define VERSAL_CPU_CLOCK 212000 98 #endif 99 100 /* Access control register defines */ 101 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 102 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 103 104 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 105 #define CRF_BASE 0xFD1A0000 106 #define CRF_SIZE 0x00600000 107 108 /* CRF registers and bitfields */ 109 #define CRF_RST_APU (CRF_BASE + 0X00000300) 110 111 #define CRF_RST_APU_ACPU_RESET (1 << 0) 112 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 113 114 /* APU registers and bitfields */ 115 #define FPD_APU_BASE 0xFD5C0000U 116 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 117 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 118 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 119 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 120 121 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 122 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 123 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 124 125 /* PMC registers and bitfields */ 126 #define PMC_GLOBAL_BASE 0xF1110000U 127 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 128 129 #endif /* VERSAL_DEF_H */ 130
