1 /* Copyright (c) 2021 Intel Corporation 2 * SPDX-License-Identifier: Apache-2.0 3 */ 4 #ifndef _ZEPHYR_SOC_INTEL_ADSP_VECTORS 5 #define _ZEPHYR_SOC_INTEL_ADSP_VECTORS 6 7 #include <xtensa/config/core-isa.h> 8 9 /* This is the base address of all the vectors defined in SRAM */ 10 #define VECBASE_RESET_PADDR_SRAM \ 11 (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE) 12 13 #define MEM_VECBASE_LIT_SIZE 0x178 14 15 /* The addresses of the vectors in SRAM. 16 * Only the memerror vector continues to point to its ROM address. 17 */ 18 #define INTLEVEL2_VECTOR_PADDR_SRAM \ 19 (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL2_VECOFS) 20 21 #define INTLEVEL3_VECTOR_PADDR_SRAM \ 22 (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL3_VECOFS) 23 24 #define INTLEVEL4_VECTOR_PADDR_SRAM \ 25 (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL4_VECOFS) 26 27 #ifndef SOC_SERIES_INTEL_ADSP_ACE 28 #define INTLEVEL5_VECTOR_PADDR_SRAM \ 29 (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL5_VECOFS) 30 31 #define INTLEVEL6_VECTOR_PADDR_SRAM \ 32 (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL6_VECOFS) 33 #endif /* SOC_SERIES_INTEL_ADSP_ACE */ 34 35 36 #define INTLEVEL7_VECTOR_PADDR_SRAM \ 37 (VECBASE_RESET_PADDR_SRAM + XCHAL_NMI_VECOFS) 38 39 #define KERNEL_VECTOR_PADDR_SRAM \ 40 (VECBASE_RESET_PADDR_SRAM + XCHAL_KERNEL_VECOFS) 41 42 #define USER_VECTOR_PADDR_SRAM \ 43 (VECBASE_RESET_PADDR_SRAM + XCHAL_USER_VECOFS) 44 45 #define DOUBLEEXC_VECTOR_PADDR_SRAM \ 46 (VECBASE_RESET_PADDR_SRAM + XCHAL_DOUBLEEXC_VECOFS) 47 48 #define VECTOR_TBL_SIZE 0x1000 49 50 /* Vector and literal sizes */ 51 #define MEM_VECT_LIT_SIZE 0x8 52 #define MEM_VECT_TEXT_SIZE 0x38 53 54 #define MEM_ERROR_TEXT_SIZE 0x180 55 #define MEM_ERROR_LIT_SIZE 0x8 56 57 #endif /* _ZEPHYR_SOC_INTEL_ADSP_VECTORS */ 58
