1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_VCI_V1_H 7 #define _MEC5_VCI_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief VBAT Control interface (MEC_VCI) 15 */ 16 17 typedef struct mec_vci_regs { /*!< (@ 0x4000AE00) MEC_VCI Structure */ 18 __IOM uint32_t CONFIG; /*!< (@ 0x00000000) VCI config */ 19 __IOM uint32_t LATCH_EN; /*!< (@ 0x00000004) Preserves state of signal events: VCI_IN, Week 20 alarm, and RTC alarm */ 21 __IOM uint32_t LATCH_RESET; /*!< (@ 0x00000008) Clear latched values of VCI_IN, Week Alarm, or 22 RTC Alarm */ 23 __IOM uint32_t VCI_INPUT_EN; /*!< (@ 0x0000000C) Selects VCI_IN pins used in VCI_OUT generation 24 logic */ 25 __IOM uint32_t HOLD_OFF_CNT; /*!< (@ 0x00000010) Hold off asserting VCI_OUT. Units of 125 ms */ 26 __IOM uint32_t VCI_POLARITY; /*!< (@ 0x00000014) Select active polarity of VCI_IN pins */ 27 __IOM uint32_t VCI_IN_POSED_STS; /*!< (@ 0x00000018) Positive edge detect status for VCI_IN pins */ 28 __IOM uint32_t VCI_IN_NEGED_STS; /*!< (@ 0x0000001C) Positive edge detect status for VCI_IN pins */ 29 __IOM uint32_t VCI_IN_VBAT_BUFEN; /*!< (@ 0x00000020) VCI_IN VBAT powered buffer enables. No effect 30 when VTR_CORE is on */ 31 __IOM uint32_t VCI_LID_OPEN_DET_EN; /*!< (@ 0x00000024) VCI_IN2 open lid detection feature enable */ 32 } MEC_VCI_Type; /*!< Size = 40 (0x28) */ 33 34 /** @} */ /* End of group Device_Peripheral_peripherals */ 35 36 /** @addtogroup PosMask_peripherals 37 * @{ 38 */ 39 /* ======================================================== CONFIG ========================================================= */ 40 #define MEC_VCI_CONFIG_LATCHED_VCI_IN0_N_Pos (0UL) /*!< LATCHED_VCI_IN0_N (Bit 0) */ 41 #define MEC_VCI_CONFIG_LATCHED_VCI_IN0_N_Msk (0x1UL) /*!< LATCHED_VCI_IN0_N (Bitfield-Mask: 0x01) */ 42 #define MEC_VCI_CONFIG_LATCHED_VCI_IN1_N_Pos (1UL) /*!< LATCHED_VCI_IN1_N (Bit 1) */ 43 #define MEC_VCI_CONFIG_LATCHED_VCI_IN1_N_Msk (0x2UL) /*!< LATCHED_VCI_IN1_N (Bitfield-Mask: 0x01) */ 44 #define MEC_VCI_CONFIG_LATCHED_VCI_IN2_N_Pos (2UL) /*!< LATCHED_VCI_IN2_N (Bit 2) */ 45 #define MEC_VCI_CONFIG_LATCHED_VCI_IN2_N_Msk (0x4UL) /*!< LATCHED_VCI_IN2_N (Bitfield-Mask: 0x01) */ 46 #define MEC_VCI_CONFIG_LATCHED_VCI_IN3_N_Pos (3UL) /*!< LATCHED_VCI_IN3_N (Bit 3) */ 47 #define MEC_VCI_CONFIG_LATCHED_VCI_IN3_N_Msk (0x8UL) /*!< LATCHED_VCI_IN3_N (Bitfield-Mask: 0x01) */ 48 #define MEC_VCI_CONFIG_LATCHED_VCI_IN4_N_Pos (4UL) /*!< LATCHED_VCI_IN4_N (Bit 4) */ 49 #define MEC_VCI_CONFIG_LATCHED_VCI_IN4_N_Msk (0x10UL) /*!< LATCHED_VCI_IN4_N (Bitfield-Mask: 0x01) */ 50 #define MEC_VCI_CONFIG_LATCHED_VCI_IN5_N_Pos (5UL) /*!< LATCHED_VCI_IN5_N (Bit 5) */ 51 #define MEC_VCI_CONFIG_LATCHED_VCI_IN5_N_Msk (0x20UL) /*!< LATCHED_VCI_IN5_N (Bitfield-Mask: 0x01) */ 52 #define MEC_VCI_CONFIG_LATCHED_VCI_IN6_N_Pos (6UL) /*!< LATCHED_VCI_IN6_N (Bit 6) */ 53 #define MEC_VCI_CONFIG_LATCHED_VCI_IN6_N_Msk (0x40UL) /*!< LATCHED_VCI_IN6_N (Bitfield-Mask: 0x01) */ 54 #define MEC_VCI_CONFIG_VCI_OVRD_IN_Pos (8UL) /*!< VCI_OVRD_IN (Bit 8) */ 55 #define MEC_VCI_CONFIG_VCI_OVRD_IN_Msk (0x100UL) /*!< VCI_OVRD_IN (Bitfield-Mask: 0x01) */ 56 #define MEC_VCI_CONFIG_VCI_OUT_Pos (9UL) /*!< VCI_OUT (Bit 9) */ 57 #define MEC_VCI_CONFIG_VCI_OUT_Msk (0x200UL) /*!< VCI_OUT (Bitfield-Mask: 0x01) */ 58 #define MEC_VCI_CONFIG_FW_VCI_OUT_Pos (10UL) /*!< FW_VCI_OUT (Bit 10) */ 59 #define MEC_VCI_CONFIG_FW_VCI_OUT_Msk (0x400UL) /*!< FW_VCI_OUT (Bitfield-Mask: 0x01) */ 60 #define MEC_VCI_CONFIG_VCI_OUT_SRC_Pos (11UL) /*!< VCI_OUT_SRC (Bit 11) */ 61 #define MEC_VCI_CONFIG_VCI_OUT_SRC_Msk (0x800UL) /*!< VCI_OUT_SRC (Bitfield-Mask: 0x01) */ 62 #define MEC_VCI_CONFIG_VCI_FILT_Pos (12UL) /*!< VCI_FILT (Bit 12) */ 63 #define MEC_VCI_CONFIG_VCI_FILT_Msk (0x1000UL) /*!< VCI_FILT (Bitfield-Mask: 0x01) */ 64 #define MEC_VCI_CONFIG_WEEK_ALARM_STS_Pos (16UL) /*!< WEEK_ALARM_STS (Bit 16) */ 65 #define MEC_VCI_CONFIG_WEEK_ALARM_STS_Msk (0x10000UL) /*!< WEEK_ALARM_STS (Bitfield-Mask: 0x01) */ 66 #define MEC_VCI_CONFIG_RTC_ALARM_STS_Pos (17UL) /*!< RTC_ALARM_STS (Bit 17) */ 67 #define MEC_VCI_CONFIG_RTC_ALARM_STS_Msk (0x20000UL) /*!< RTC_ALARM_STS (Bitfield-Mask: 0x01) */ 68 #define MEC_VCI_CONFIG_SYSPWR_SEL_Pos (18UL) /*!< SYSPWR_SEL (Bit 18) */ 69 #define MEC_VCI_CONFIG_SYSPWR_SEL_Msk (0x40000UL) /*!< SYSPWR_SEL (Bitfield-Mask: 0x01) */ 70 /* ======================================================= LATCH_EN ======================================================== */ 71 #define MEC_VCI_LATCH_EN_VCI_IN0_Pos (0UL) /*!< VCI_IN0 (Bit 0) */ 72 #define MEC_VCI_LATCH_EN_VCI_IN0_Msk (0x1UL) /*!< VCI_IN0 (Bitfield-Mask: 0x01) */ 73 #define MEC_VCI_LATCH_EN_VCI_IN1_Pos (1UL) /*!< VCI_IN1 (Bit 1) */ 74 #define MEC_VCI_LATCH_EN_VCI_IN1_Msk (0x2UL) /*!< VCI_IN1 (Bitfield-Mask: 0x01) */ 75 #define MEC_VCI_LATCH_EN_VCI_IN2_Pos (2UL) /*!< VCI_IN2 (Bit 2) */ 76 #define MEC_VCI_LATCH_EN_VCI_IN2_Msk (0x4UL) /*!< VCI_IN2 (Bitfield-Mask: 0x01) */ 77 #define MEC_VCI_LATCH_EN_VCI_IN3_Pos (3UL) /*!< VCI_IN3 (Bit 3) */ 78 #define MEC_VCI_LATCH_EN_VCI_IN3_Msk (0x8UL) /*!< VCI_IN3 (Bitfield-Mask: 0x01) */ 79 #define MEC_VCI_LATCH_EN_VCI_IN4_Pos (4UL) /*!< VCI_IN4 (Bit 4) */ 80 #define MEC_VCI_LATCH_EN_VCI_IN4_Msk (0x10UL) /*!< VCI_IN4 (Bitfield-Mask: 0x01) */ 81 #define MEC_VCI_LATCH_EN_VCI_IN5_Pos (5UL) /*!< VCI_IN5 (Bit 5) */ 82 #define MEC_VCI_LATCH_EN_VCI_IN5_Msk (0x20UL) /*!< VCI_IN5 (Bitfield-Mask: 0x01) */ 83 #define MEC_VCI_LATCH_EN_VCI_IN6_Pos (6UL) /*!< VCI_IN6 (Bit 6) */ 84 #define MEC_VCI_LATCH_EN_VCI_IN6_Msk (0x40UL) /*!< VCI_IN6 (Bitfield-Mask: 0x01) */ 85 #define MEC_VCI_LATCH_EN_WEEK_ALARM_Pos (16UL) /*!< WEEK_ALARM (Bit 16) */ 86 #define MEC_VCI_LATCH_EN_WEEK_ALARM_Msk (0x10000UL) /*!< WEEK_ALARM (Bitfield-Mask: 0x01) */ 87 #define MEC_VCI_LATCH_EN_RTC_ALARM_Pos (17UL) /*!< RTC_ALARM (Bit 17) */ 88 #define MEC_VCI_LATCH_EN_RTC_ALARM_Msk (0x20000UL) /*!< RTC_ALARM (Bitfield-Mask: 0x01) */ 89 /* ====================================================== LATCH_RESET ====================================================== */ 90 #define MEC_VCI_LATCH_RESET_VCI_IN0_Pos (0UL) /*!< VCI_IN0 (Bit 0) */ 91 #define MEC_VCI_LATCH_RESET_VCI_IN0_Msk (0x1UL) /*!< VCI_IN0 (Bitfield-Mask: 0x01) */ 92 #define MEC_VCI_LATCH_RESET_VCI_IN1_Pos (1UL) /*!< VCI_IN1 (Bit 1) */ 93 #define MEC_VCI_LATCH_RESET_VCI_IN1_Msk (0x2UL) /*!< VCI_IN1 (Bitfield-Mask: 0x01) */ 94 #define MEC_VCI_LATCH_RESET_VCI_IN2_Pos (2UL) /*!< VCI_IN2 (Bit 2) */ 95 #define MEC_VCI_LATCH_RESET_VCI_IN2_Msk (0x4UL) /*!< VCI_IN2 (Bitfield-Mask: 0x01) */ 96 #define MEC_VCI_LATCH_RESET_VCI_IN3_Pos (3UL) /*!< VCI_IN3 (Bit 3) */ 97 #define MEC_VCI_LATCH_RESET_VCI_IN3_Msk (0x8UL) /*!< VCI_IN3 (Bitfield-Mask: 0x01) */ 98 #define MEC_VCI_LATCH_RESET_VCI_IN4_Pos (4UL) /*!< VCI_IN4 (Bit 4) */ 99 #define MEC_VCI_LATCH_RESET_VCI_IN4_Msk (0x10UL) /*!< VCI_IN4 (Bitfield-Mask: 0x01) */ 100 #define MEC_VCI_LATCH_RESET_VCI_IN5_Pos (5UL) /*!< VCI_IN5 (Bit 5) */ 101 #define MEC_VCI_LATCH_RESET_VCI_IN5_Msk (0x20UL) /*!< VCI_IN5 (Bitfield-Mask: 0x01) */ 102 #define MEC_VCI_LATCH_RESET_VCI_IN6_Pos (6UL) /*!< VCI_IN6 (Bit 6) */ 103 #define MEC_VCI_LATCH_RESET_VCI_IN6_Msk (0x40UL) /*!< VCI_IN6 (Bitfield-Mask: 0x01) */ 104 #define MEC_VCI_LATCH_RESET_WEEK_ALARM_Pos (16UL) /*!< WEEK_ALARM (Bit 16) */ 105 #define MEC_VCI_LATCH_RESET_WEEK_ALARM_Msk (0x10000UL) /*!< WEEK_ALARM (Bitfield-Mask: 0x01) */ 106 #define MEC_VCI_LATCH_RESET_RTC_ALARM_Pos (17UL) /*!< RTC_ALARM (Bit 17) */ 107 #define MEC_VCI_LATCH_RESET_RTC_ALARM_Msk (0x20000UL) /*!< RTC_ALARM (Bitfield-Mask: 0x01) */ 108 /* ===================================================== VCI_INPUT_EN ====================================================== */ 109 #define MEC_VCI_VCI_INPUT_EN_VCI_IN0_Pos (0UL) /*!< VCI_IN0 (Bit 0) */ 110 #define MEC_VCI_VCI_INPUT_EN_VCI_IN0_Msk (0x1UL) /*!< VCI_IN0 (Bitfield-Mask: 0x01) */ 111 #define MEC_VCI_VCI_INPUT_EN_VCI_IN1_Pos (1UL) /*!< VCI_IN1 (Bit 1) */ 112 #define MEC_VCI_VCI_INPUT_EN_VCI_IN1_Msk (0x2UL) /*!< VCI_IN1 (Bitfield-Mask: 0x01) */ 113 #define MEC_VCI_VCI_INPUT_EN_VCI_IN2_Pos (2UL) /*!< VCI_IN2 (Bit 2) */ 114 #define MEC_VCI_VCI_INPUT_EN_VCI_IN2_Msk (0x4UL) /*!< VCI_IN2 (Bitfield-Mask: 0x01) */ 115 #define MEC_VCI_VCI_INPUT_EN_VCI_IN3_Pos (3UL) /*!< VCI_IN3 (Bit 3) */ 116 #define MEC_VCI_VCI_INPUT_EN_VCI_IN3_Msk (0x8UL) /*!< VCI_IN3 (Bitfield-Mask: 0x01) */ 117 #define MEC_VCI_VCI_INPUT_EN_VCI_IN4_Pos (4UL) /*!< VCI_IN4 (Bit 4) */ 118 #define MEC_VCI_VCI_INPUT_EN_VCI_IN4_Msk (0x10UL) /*!< VCI_IN4 (Bitfield-Mask: 0x01) */ 119 #define MEC_VCI_VCI_INPUT_EN_VCI_IN5_Pos (5UL) /*!< VCI_IN5 (Bit 5) */ 120 #define MEC_VCI_VCI_INPUT_EN_VCI_IN5_Msk (0x20UL) /*!< VCI_IN5 (Bitfield-Mask: 0x01) */ 121 #define MEC_VCI_VCI_INPUT_EN_VCI_IN6_Pos (6UL) /*!< VCI_IN6 (Bit 6) */ 122 #define MEC_VCI_VCI_INPUT_EN_VCI_IN6_Msk (0x40UL) /*!< VCI_IN6 (Bitfield-Mask: 0x01) */ 123 /* ===================================================== HOLD_OFF_CNT ====================================================== */ 124 /* ===================================================== VCI_POLARITY ====================================================== */ 125 #define MEC_VCI_VCI_POLARITY_VCI_IN0_ACTIVE_HI_Pos (0UL) /*!< VCI_IN0_ACTIVE_HI (Bit 0) */ 126 #define MEC_VCI_VCI_POLARITY_VCI_IN0_ACTIVE_HI_Msk (0x1UL) /*!< VCI_IN0_ACTIVE_HI (Bitfield-Mask: 0x01) */ 127 #define MEC_VCI_VCI_POLARITY_VCI_IN1_ACTIVE_HI_Pos (1UL) /*!< VCI_IN1_ACTIVE_HI (Bit 1) */ 128 #define MEC_VCI_VCI_POLARITY_VCI_IN1_ACTIVE_HI_Msk (0x2UL) /*!< VCI_IN1_ACTIVE_HI (Bitfield-Mask: 0x01) */ 129 #define MEC_VCI_VCI_POLARITY_VCI_IN2_ACTIVE_HI_Pos (2UL) /*!< VCI_IN2_ACTIVE_HI (Bit 2) */ 130 #define MEC_VCI_VCI_POLARITY_VCI_IN2_ACTIVE_HI_Msk (0x4UL) /*!< VCI_IN2_ACTIVE_HI (Bitfield-Mask: 0x01) */ 131 #define MEC_VCI_VCI_POLARITY_VCI_IN3_ACTIVE_HI_Pos (3UL) /*!< VCI_IN3_ACTIVE_HI (Bit 3) */ 132 #define MEC_VCI_VCI_POLARITY_VCI_IN3_ACTIVE_HI_Msk (0x8UL) /*!< VCI_IN3_ACTIVE_HI (Bitfield-Mask: 0x01) */ 133 #define MEC_VCI_VCI_POLARITY_VCI_IN4_ACTIVE_HI_Pos (4UL) /*!< VCI_IN4_ACTIVE_HI (Bit 4) */ 134 #define MEC_VCI_VCI_POLARITY_VCI_IN4_ACTIVE_HI_Msk (0x10UL) /*!< VCI_IN4_ACTIVE_HI (Bitfield-Mask: 0x01) */ 135 #define MEC_VCI_VCI_POLARITY_VCI_IN5_ACTIVE_HI_Pos (5UL) /*!< VCI_IN5_ACTIVE_HI (Bit 5) */ 136 #define MEC_VCI_VCI_POLARITY_VCI_IN5_ACTIVE_HI_Msk (0x20UL) /*!< VCI_IN5_ACTIVE_HI (Bitfield-Mask: 0x01) */ 137 #define MEC_VCI_VCI_POLARITY_VCI_IN6_ACTIVE_HI_Pos (6UL) /*!< VCI_IN6_ACTIVE_HI (Bit 6) */ 138 #define MEC_VCI_VCI_POLARITY_VCI_IN6_ACTIVE_HI_Msk (0x40UL) /*!< VCI_IN6_ACTIVE_HI (Bitfield-Mask: 0x01) */ 139 /* =================================================== VCI_IN_POSED_STS ==================================================== */ 140 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN0_Pos (0UL) /*!< VCI_IN0 (Bit 0) */ 141 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN0_Msk (0x1UL) /*!< VCI_IN0 (Bitfield-Mask: 0x01) */ 142 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN1_Pos (1UL) /*!< VCI_IN1 (Bit 1) */ 143 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN1_Msk (0x2UL) /*!< VCI_IN1 (Bitfield-Mask: 0x01) */ 144 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN2_Pos (2UL) /*!< VCI_IN2 (Bit 2) */ 145 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN2_Msk (0x4UL) /*!< VCI_IN2 (Bitfield-Mask: 0x01) */ 146 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN3_Pos (3UL) /*!< VCI_IN3 (Bit 3) */ 147 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN3_Msk (0x8UL) /*!< VCI_IN3 (Bitfield-Mask: 0x01) */ 148 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN4_Pos (4UL) /*!< VCI_IN4 (Bit 4) */ 149 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN4_Msk (0x10UL) /*!< VCI_IN4 (Bitfield-Mask: 0x01) */ 150 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN5_Pos (5UL) /*!< VCI_IN5 (Bit 5) */ 151 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN5_Msk (0x20UL) /*!< VCI_IN5 (Bitfield-Mask: 0x01) */ 152 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN6_Pos (6UL) /*!< VCI_IN6 (Bit 6) */ 153 #define MEC_VCI_VCI_IN_POSED_STS_VCI_IN6_Msk (0x40UL) /*!< VCI_IN6 (Bitfield-Mask: 0x01) */ 154 /* =================================================== VCI_IN_NEGED_STS ==================================================== */ 155 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN0_Pos (0UL) /*!< VCI_IN0 (Bit 0) */ 156 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN0_Msk (0x1UL) /*!< VCI_IN0 (Bitfield-Mask: 0x01) */ 157 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN1_Pos (1UL) /*!< VCI_IN1 (Bit 1) */ 158 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN1_Msk (0x2UL) /*!< VCI_IN1 (Bitfield-Mask: 0x01) */ 159 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN2_Pos (2UL) /*!< VCI_IN2 (Bit 2) */ 160 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN2_Msk (0x4UL) /*!< VCI_IN2 (Bitfield-Mask: 0x01) */ 161 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN3_Pos (3UL) /*!< VCI_IN3 (Bit 3) */ 162 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN3_Msk (0x8UL) /*!< VCI_IN3 (Bitfield-Mask: 0x01) */ 163 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN4_Pos (4UL) /*!< VCI_IN4 (Bit 4) */ 164 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN4_Msk (0x10UL) /*!< VCI_IN4 (Bitfield-Mask: 0x01) */ 165 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN5_Pos (5UL) /*!< VCI_IN5 (Bit 5) */ 166 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN5_Msk (0x20UL) /*!< VCI_IN5 (Bitfield-Mask: 0x01) */ 167 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN6_Pos (6UL) /*!< VCI_IN6 (Bit 6) */ 168 #define MEC_VCI_VCI_IN_NEGED_STS_VCI_IN6_Msk (0x40UL) /*!< VCI_IN6 (Bitfield-Mask: 0x01) */ 169 /* =================================================== VCI_IN_VBAT_BUFEN =================================================== */ 170 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN0_Pos (0UL) /*!< VCI_IN0 (Bit 0) */ 171 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN0_Msk (0x1UL) /*!< VCI_IN0 (Bitfield-Mask: 0x01) */ 172 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN1_Pos (1UL) /*!< VCI_IN1 (Bit 1) */ 173 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN1_Msk (0x2UL) /*!< VCI_IN1 (Bitfield-Mask: 0x01) */ 174 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN2_Pos (2UL) /*!< VCI_IN2 (Bit 2) */ 175 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN2_Msk (0x4UL) /*!< VCI_IN2 (Bitfield-Mask: 0x01) */ 176 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN3_Pos (3UL) /*!< VCI_IN3 (Bit 3) */ 177 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN3_Msk (0x8UL) /*!< VCI_IN3 (Bitfield-Mask: 0x01) */ 178 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN4_Pos (4UL) /*!< VCI_IN4 (Bit 4) */ 179 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN4_Msk (0x10UL) /*!< VCI_IN4 (Bitfield-Mask: 0x01) */ 180 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN5_Pos (5UL) /*!< VCI_IN5 (Bit 5) */ 181 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN5_Msk (0x20UL) /*!< VCI_IN5 (Bitfield-Mask: 0x01) */ 182 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN6_Pos (6UL) /*!< VCI_IN6 (Bit 6) */ 183 #define MEC_VCI_VCI_IN_VBAT_BUFEN_VCI_IN6_Msk (0x40UL) /*!< VCI_IN6 (Bitfield-Mask: 0x01) */ 184 /* ================================================== VCI_LID_OPEN_DET_EN ================================================== */ 185 #define MEC_VCI_VCI_LID_OPEN_DET_EN_VCI_LID_EN_Pos (0UL) /*!< VCI_LID_EN (Bit 0) */ 186 #define MEC_VCI_VCI_LID_OPEN_DET_EN_VCI_LID_EN_Msk (0x1UL) /*!< VCI_LID_EN (Bitfield-Mask: 0x01) */ 187 188 /** @} */ /* End of group PosMask_peripherals */ 189 190 /** @addtogroup EnumValue_peripherals 191 * @{ 192 */ 193 /* ======================================================== CONFIG ========================================================= */ 194 /* =========================================== MEC_VCI CONFIG VCI_OVRD_IN [8..8] =========================================== */ 195 typedef enum { /*!< MEC_VCI_CONFIG_VCI_OVRD_IN */ 196 MEC_VCI_CONFIG_VCI_OVRD_IN_HI = 1, /*!< HI : High */ 197 } MEC_VCI_CONFIG_VCI_OVRD_IN_Enum; 198 199 /* ============================================= MEC_VCI CONFIG VCI_OUT [9..9] ============================================= */ 200 typedef enum { /*!< MEC_VCI_CONFIG_VCI_OUT */ 201 MEC_VCI_CONFIG_VCI_OUT_HI = 1, /*!< HI : High */ 202 } MEC_VCI_CONFIG_VCI_OUT_Enum; 203 204 /* ========================================== MEC_VCI CONFIG FW_VCI_OUT [10..10] =========================================== */ 205 typedef enum { /*!< MEC_VCI_CONFIG_FW_VCI_OUT */ 206 MEC_VCI_CONFIG_FW_VCI_OUT_HI = 1, /*!< HI : High */ 207 } MEC_VCI_CONFIG_FW_VCI_OUT_Enum; 208 209 /* ========================================== MEC_VCI CONFIG VCI_OUT_SRC [11..11] ========================================== */ 210 typedef enum { /*!< MEC_VCI_CONFIG_VCI_OUT_SRC */ 211 MEC_VCI_CONFIG_VCI_OUT_SRC_EXT = 0, /*!< EXT : External inputs */ 212 MEC_VCI_CONFIG_VCI_OUT_SRC_FW = 1, /*!< FW : Software controlled */ 213 } MEC_VCI_CONFIG_VCI_OUT_SRC_Enum; 214 215 /* =========================================== MEC_VCI CONFIG VCI_FILT [12..12] ============================================ */ 216 typedef enum { /*!< MEC_VCI_CONFIG_VCI_FILT */ 217 MEC_VCI_CONFIG_VCI_FILT_DIS = 1, /*!< DIS : Disable */ 218 } MEC_VCI_CONFIG_VCI_FILT_Enum; 219 220 /* ======================================== MEC_VCI CONFIG WEEK_ALARM_STS [16..16] ========================================= */ 221 typedef enum { /*!< MEC_VCI_CONFIG_WEEK_ALARM_STS */ 222 MEC_VCI_CONFIG_WEEK_ALARM_STS_ACTIVE = 1, /*!< ACTIVE : Active */ 223 } MEC_VCI_CONFIG_WEEK_ALARM_STS_Enum; 224 225 /* ========================================= MEC_VCI CONFIG RTC_ALARM_STS [17..17] ========================================= */ 226 typedef enum { /*!< MEC_VCI_CONFIG_RTC_ALARM_STS */ 227 MEC_VCI_CONFIG_RTC_ALARM_STS_ACTIVE = 1, /*!< ACTIVE : Active */ 228 } MEC_VCI_CONFIG_RTC_ALARM_STS_Enum; 229 230 /* ========================================== MEC_VCI CONFIG SYSPWR_SEL [18..18] =========================================== */ 231 typedef enum { /*!< MEC_VCI_CONFIG_SYSPWR_SEL */ 232 MEC_VCI_CONFIG_SYSPWR_SEL_VCI_IN3 = 0, /*!< VCI_IN3 : Select VCI_IN */ 233 MEC_VCI_CONFIG_SYSPWR_SEL_SYSPWR = 1, /*!< SYSPWR : Select SYSPWR */ 234 } MEC_VCI_CONFIG_SYSPWR_SEL_Enum; 235 236 /** @} */ /* End of group EnumValue_peripherals */ 237 238 #endif /* _MEC5_VCI_V1_H */ 239
