1 /****************************************************************************** 2 * @file sl_si91x_gpio_common.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 #ifndef SL_SI91X_GPIO_COMMONH 30 #define SL_SI91X_GPIO_COMMONH 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 //// Includes 37 /// 38 #include "si91x_device.h" 39 /***************************************************************************/ /** 40 * @addtogroup GPIO 41 * @ingroup SI91X_PERIPHERAL_APIS 42 * @{ 43 * 44 ******************************************************************************/ 45 /******************************************************************************* 46 *************************** Defines / Macros ******************************** 47 ******************************************************************************/ 48 #define PAD_REG_BASE 0x46004000UL ///< PAD configuration register base address 49 #define NPSS_INT_BASE 0x12080000UL ///< UULP INTR base address 50 #define ULP_PAD_REG_BASE 0x2404A000UL ///< ULP PAD configuration base address 51 52 #define GPIO ((EGPIO_Type *)EGPIO_BASE) ///< MCU HP base address 53 #define ULP_GPIO ((EGPIO_Type *)EGPIO1_BASE) ///< MCU ULP base address 54 #define UULP_GPIO_FSM ((MCU_FSM_Type *)MCU_FSM_BASE) ///< SLEEP FSM base address 55 #define UULP_GPIO ((MCU_RET_Type *)MCU_RET_BASE) ///< MCU retention base address 56 57 #define PAD_REG(x) ((PAD_CONFIG_Type *)(PAD_REG_BASE + (4 * x))) ///< PAD configuration register for GPIO_n(n = 0 t0 63) 58 #define ULP_PAD_CONFIG0_REG ((ULP_PAD_CONFIG_Type0 *)(ULP_PAD_REG_BASE + 0x0)) ///< ULP PAD configuration register 0 59 #define ULP_PAD_CONFIG1_REG ((ULP_PAD_CONFIG_Type1 *)(ULP_PAD_REG_BASE + 0x4)) ///< ULP PAD configuration register 1 60 #define ULP_PAD_CONFIG2_REG ((ULP_PAD_CONFIG_Type2 *)(ULP_PAD_REG_BASE + 0x8)) ///< ULP PAD configuration register 2 61 62 #define UULP_PAD_CONFIG_REG(x) \ 63 ((UULP_PAD_CONFIG_Type *)(0x2404861C + 4 * x)) ///< UULP V_bat PAD configuration base address 64 #define PADSELECTION \ 65 (*(volatile uint32_t *)(0x41300000 + 0x610)) ///< PAD selection (0 to 21) A value of 1 on this gives control to M4SS 66 #define PADSELECTION_1 \ 67 (*(volatile uint32_t *)(0x41300000 + 0x618)) ///< PAD selection (22 to 33) A value of 1 on this gives control to M4SS 68 #define HOST_PADS_GPIO_MODE (*(volatile uint32_t *)(0x46008000 + 0x44)) ///< MISC host base address 69 #define ULP_PAD_CONFIG_REG (*(volatile uint32_t *)(0x2404A008)) ///< ULP PAD register 70 71 #define GPIO_NPSS_INTERRUPT_MASK_SET_REG \ 72 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x00)) ///< NPSS mask set register base address 73 #define GPIO_NPSS_INTERRUPT_MASK_CLR_REG \ 74 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x04)) ///< NPSS mask clear register base address 75 #define GPIO_NPSS_INTERRUPT_CLEAR_REG \ 76 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x08)) ///< NPSS clear register base address 77 #define GPIO_NPSS_INTERRUPT_STATUS_REG \ 78 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x0C)) ///< NPSS status register base address 79 #define GPIO_NPSS_GPIO_CONFIG_REG \ 80 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x10)) ///< NPSS GPIO configuration register base address 81 #define UULP_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INT_BASE + 0x14)) ///< UULP GPIO status base address 82 #define GPIO_25_30_CONFIG_REG (*(volatile uint32_t *)(0X46008000 + 0x0C)) ///< GPIO(25-30) pin configuration register 83 84 #define CLR 0 85 #define SET 1 86 87 #define SL_DEBUG_ASSERT 88 89 #define NIBBLE_SHIFT 4 ///< Nibble shift for interrupt 90 #define BYTE_SHIFT 8 ///< Byte shift for interrupt 91 #define WORD_SHIFT 16 ///< Word shift for interrupt 92 #define LSB_WORD_MASK 0x00FF ///< GPIO LSB word mask 93 #define LSB_NIBBLE_MASK 0x0F ///< GPIO LSB nibble mask 94 95 #define MAX_GPIO_PORT_PIN 16 ///< GPIO maximum port pins 96 #define HOST_PAD 12 ///< GPIO Host PAD 97 98 #define GPIO_PA_COUNT 16 ///< GPIO port A maximum pins 99 #define GPIO_PB_COUNT 16 ///< GPIO port B maximum pins 100 #define GPIO_PC_COUNT 16 ///< GPIO port C maximum pins 101 #define GPIO_PD_COUNT 9 ///< GPIO port D maximum pins 102 #define GPIO_PE_COUNT 12 ///< GPIO port E maximum pins 103 104 #define GPIO_PA_MASK 0xFFFFUL ///< GPIO port A mask 105 #define GPIO_PB_MASK 0xFFFFUL ///< GPIO port B mask 106 #define GPIO_PC_MASK 0xFFFFUL ///< GPIO port C mask 107 #define GPIO_PD_MASK 0x01FFUL ///< GPIO port D mask 108 109 #define SL_PERIPHERAL_CLK M4CLK ///< GPIO instance clock 110 111 #define UNUSED_VAR(expr) ((void)(expr)) 112 113 #define GPIO_PA_PIN_MAX_VALIDATE 75 ///< GPIO port A maximum pins to validate 114 #define GPIO_PB_PIN_MAX_VALIDATE 59 ///< GPIO port B maximum pins to validate 115 #define GPIO_PC_PIN_MAX_VALIDATE 43 ///< GPIO port C maximum pins to validate 116 #define GPIO_PD_PIN_MAX_VALIDATE 27 ///< GPIO port D maximum pins to validate 117 118 #ifdef SL_DEBUG_ASSERT 119 #define SL_GPIO_ASSERT(expr) ((expr) ? (void)0U : sl_assert_failed((uint8_t *)__FILE__, __LINE__)) 120 #else 121 #define SL_GPIO_ASSERT(expr) ((void)(expr)) 122 #endif 123 124 #define SL_GPIO_VALIDATE_STRENGTH(strength) (strength > 3 ? 0 : 1) ///< Validate driver strength 125 #define SL_GPIO_VALIDATE_PARAMETER(value) (value > 1 ? 0 : 1) ///< Validate GPIO parameters 126 #define SL_GPIO_VALIDATE_DISABLE_STATE(disable_state) (disable_state > 3 ? 0 : 1) ///< Validate driver disable state 127 #define SL_GPIO_VALIDATE_PAD(pad_num) ((pad_num > 34) && (pad_num < 1) ? 0 : 1) ///< Validate GPIO HP pad selection 128 #define SL_GPIO_VALIDATE_PIN(pin_num) ((pin_num > 63) ? 0 : 1) ///< Validate GPIO HP pin number 129 #define SL_GPIO_VALIDATE_FLAG(flag) ((flag > 0x0F) ? 0 : 1) ///< Validate GPIO flags 130 #define SL_GPIO_VALIDATE_ULP_INTR(ulp_intr) ((ulp_intr > 12) ? 0 : 1) ///< Validate ULP interrupts 131 #define SL_GPIO_VALIDATE_ULP_PIN(pin_num) ((pin_num > 12) ? 0 : 1) ///< Validate ULP pins 132 #define SL_GPIO_VALIDATE_UULP_PIN(pin_num) ((pin_num) > 5 ? 0 : 1) ///< Validate UULP pins 133 #define SL_GPIO_VALIDATE_MODE_PARAMETER(mode) ((mode) > 10 ? 0 : 1) ///< Validate UULP, ULP mode 134 #define SL_GPIO_VALIDATE_UULP_INTR(interrupt) ((interrupt) > 16 ? 0 : 1) ///< Validate UULP interrupt 135 #define SL_GPIO_VALIDATE_PORT(port) ((port) > 5 ? 0 : 1) ///< Validate GPIO port 136 #define SL_GPIO_VALIDATE_MODE(mode) ((mode) > 15 ? 0 : 1) ///< Validate GPIO mode 137 #define SL_GPIO_VALIDATE_INTR(interrupt) ((interrupt > 8) ? 0 : 1) ///< Validate GPIO interrupt 138 ///< Validate GPIO port and pin 139 #define SL_GPIO_NDEBUG_PORT_PIN(port, pin) \ 140 (port == 0 ? ((pin > GPIO_PA_PIN_MAX_VALIDATE) ? 0 : 1) \ 141 : port == 1 ? ((pin > GPIO_PB_PIN_MAX_VALIDATE) ? 0 : 1) \ 142 : port == 2 ? ((pin > GPIO_PC_PIN_MAX_VALIDATE) ? 0 : 1) \ 143 : port == 3 ? ((pin > GPIO_PD_PIN_MAX_VALIDATE) ? 0 : 1) \ 144 : 0) 145 ///< Validate GPIO host pad port and pin 146 #define SL_GPIO_VALIDATE_HOST_PIN(port, pin) \ 147 (port == SL_GPIO_PORT_A ? (((pin >= HOST_PAD_MIN) && (pin <= HOST_PAD_MAX)) ? TRUE : FALSE) \ 148 : port == SL_GPIO_PORT_B ? (((pin >= GPIO_PIN_NUMBER9) && (pin <= GPIO_PIN_NUMBER14)) ? TRUE : FALSE) \ 149 : FALSE) 150 #define SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin) (port == 4 ? ((pin > 11) ? 0 : 1) : 0) ///< Validate ULP port and pin 151 #define SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin) (port == 5 ? ((pin > 5) ? 0 : 1) : 0) ///< Validate UULP port and pin 152 153 #define GRP_IRQ0_Handler IRQ050_Handler ///< GPIO Group Interrupt 0 154 #define GRP_IRQ1_Handler IRQ051_Handler ///< GPIO Group Interrupt 1 155 156 #define PIN_IRQ0_Handler IRQ052_Handler ///< GPIO Pin Interrupt 0 157 #define PIN_IRQ1_Handler IRQ053_Handler ///< GPIO Pin Interrupt 1 158 #define PIN_IRQ2_Handler IRQ054_Handler ///< GPIO Pin Interrupt 2 159 #define PIN_IRQ3_Handler IRQ055_Handler ///< GPIO Pin Interrupt 3 160 #define PIN_IRQ4_Handler IRQ056_Handler ///< GPIO Pin Interrupt 4 161 #define PIN_IRQ5_Handler IRQ057_Handler ///< GPIO Pin Interrupt 5 162 #define PIN_IRQ6_Handler IRQ058_Handler ///< GPIO Pin Interrupt 6 163 #define PIN_IRQ7_Handler IRQ059_Handler ///< GPIO Pin Interrupt 7 164 165 #define UULP_PIN_IRQ_Handler IRQ021_Handler ///< UULP Pin Interrupt 0 166 167 #define ULP_PIN_IRQ_Handler IRQ018_Handler ///< ULP Pin Interrupt 168 #define ULP_GROUP_IRQ_Handler IRQ019_Handler ///< ULP Group Interrupt 169 170 #define PIN_INTR_0 0 ///< HP GPIO pin interrupt 0 171 #define PIN_INTR_1 1 ///< HP GPIO pin interrupt 1 172 #define PIN_INTR_2 2 ///< HP GPIO pin interrupt 2 173 #define PIN_INTR_3 3 ///< HP GPIO pin interrupt 3 174 #define PIN_INTR_4 4 ///< HP GPIO pin interrupt 4 175 #define PIN_INTR_5 5 ///< HP GPIO pin interrupt 5 176 #define PIN_INTR_6 6 ///< HP GPIO pin interrupt 6 177 #define PIN_INTR_7 7 ///< HP GPIO pin interrupt 7 178 179 #define UULP_MASK 0x00 ///< UULP GPIO pin mask 180 #define ULP_STATUS 0x01 ///< ULP GPIO pin status 181 #define UULP_INTR_1 0x01 ///< UULP GPIO pin interrupt 1 182 #define UULP_INTR_2 0x02 ///< UULP GPIO pin interrupt 2 183 #define UULP_INTR_3 0x04 ///< UULP GPIO pin interrupt 3 184 #define UULP_INTR_4 0x08 ///< UULP GPIO pin interrupt 4 185 #define UULP_INTR_5 0x10 ///< UULP GPIO pin interrupt 5 186 187 #define ULP_PIN_INTR_0 0 ///< ULP GPIO pin interrupt 0 188 #define ULP_PIN_INTR_1 1 ///< ULP GPIO pin interrupt 1 189 #define ULP_PIN_INTR_2 2 ///< ULP GPIO pin interrupt 2 190 #define ULP_PIN_INTR_3 3 ///< ULP GPIO pin interrupt 3 191 #define ULP_PIN_INTR_4 4 ///< ULP GPIO pin interrupt 4 192 #define ULP_PIN_INTR_5 5 ///< ULP GPIO pin interrupt 5 193 #define ULP_PIN_INTR_6 6 ///< ULP GPIO pin interrupt 6 194 #define ULP_PIN_INTR_7 7 ///< ULP GPIO pin interrupt 7 195 196 #define ULP_GROUP_INTR_0 0 ///< ULP GPIO group interrupt 0 197 #define ULP_GROUP_INTR_1 1 ///< ULP GPIO group interrupt 1 198 199 #define MAX_GPIO_PIN_INT 8 ///< Maximum HP GPIO pin interrupts 200 201 #define PININT0_NVIC_NAME EGPIO_PIN_0_IRQn ///< HP GPIO pin interrupt 0 number 202 #define PININT1_NVIC_NAME EGPIO_PIN_1_IRQn ///< HP GPIO pin interrupt 1 number 203 #define PININT2_NVIC_NAME EGPIO_PIN_2_IRQn ///< HP GPIO pin interrupt 2 number 204 #define PININT3_NVIC_NAME EGPIO_PIN_3_IRQn ///< HP GPIO pin interrupt 3 number 205 #define PININT4_NVIC_NAME EGPIO_PIN_4_IRQn ///< HP GPIO pin interrupt 4 number 206 #define PININT5_NVIC_NAME EGPIO_PIN_5_IRQn ///< HP GPIO pin interrupt 5 number 207 #define PININT6_NVIC_NAME EGPIO_PIN_6_IRQn ///< HP GPIO pin interrupt 6 number 208 #define PININT7_NVIC_NAME EGPIO_PIN_7_IRQn ///< HP GPIO pin interrupt 7 number 209 210 #define GROUP_0_INTERRUPT_NAME EGPIO_GROUP_0_IRQn ///< HP GPIO group interrupt 1 number 211 #define GROUP_1_INTERRUPT_NAME EGPIO_GROUP_1_IRQn ///< HP GPIO group interrupt 2 number 212 213 #define ULP_PININT0_NVIC_NAME ULP_EGPIO_PIN_IRQn ///< ULP GPIO pin interrupt number 214 #define ULP_GROUP_INTERRUPT_NAME ULP_EGPIO_GROUP_IRQn ///< ULP GPIO group interrupt number 215 216 #define UULP_PININT_NVIC_NAME NPSS_TO_MCU_GPIO_INTR_IRQn ///< UULP GPIO pin interrupt number 217 218 #define SL_GPIO_GROUP_INTERRUPT_OR 1 ///< GPIO group interrupt AND/OR 219 #define SL_GPIO_GROUP_INTERRUPT_WAKEUP 4 ///< GPIO group interrupt wakeup 220 #define SL_GPIO_ULP_PORT 4 ///< ULP GPIO port number 221 #define SL_GPIO_UULP_PORT 5 ///< Initializing UULP GPIO port value 222 #define SL_ULP_GPIO_PORT 4 ///< Refers to ULP Port 223 224 #define _MODE0 0 ///< GPIO mode 0 225 #define _MODE1 1 ///< GPIO mode 1 226 #define _MODE2 2 ///< GPIO mode 2 227 #define _MODE3 3 ///< GPIO mode 3 228 #define _MODE4 4 ///< GPIO mode 4 229 #define _MODE5 5 ///< GPIO mode 5 230 #define _MODE6 6 ///< GPIO mode 6 231 #define _MODE7 7 ///< GPIO mode 7 232 #define _MODE8 8 ///< GPIO mode 8 233 #define _MODE9 9 ///< GPIO mode 9 234 #define _MODE10 10 ///< GPIO mode 10 235 #define _MODE14 14 ///< GPIO mode 14 236 237 #define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL ///< Mode DISABLED for GPIO_P_MODEL 238 #define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL ///< Mode INPUT for GPIO_P_MODEL 239 #define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL ///< Mode INPUTPULL for GPIO_P_MODEL 240 #define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL ///< Mode INPUTPULLFILTER for GPIO_P_MODEL 241 #define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL ///< Mode PUSHPULL for GPIO_P_MODEL 242 #define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL ///< Mode PUSHPULLALT for GPIO_P_MODEL 243 #define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL ///< Mode WIREDOR for GPIO_P_MODEL 244 #define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL ///< Mode WIREDORPULLDOWN for GPIO_P_MODEL 245 #define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL ///< Mode WIREDAND for GPIO_P_MODEL 246 #define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL ///< Mode WIREDANDFILTER for GPIO_P_MODEL 247 #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL ///< Mode WIREDANDPULLUP for GPIO_P_MODEL 248 #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL ///< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL 249 #define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL ///< Mode WIREDANDALT for GPIO_P_MODEL 250 #define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL ///< Mode WIREDANDALTFILTER for GPIO_P_MODEL 251 #define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL ///< Mode WIREDANDALTPULLUP for GPIO_P_MODEL 252 #define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL ///< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL 253 254 #define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) ///< Shifted mode DISABLED for GPIO_P_MODEL 255 #define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) ///< Shifted mode INPUT for GPIO_P_MODEL 256 #define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) ///< Shifted mode INPUTPULL for GPIO_P_MODEL 257 #define GPIO_P_MODEL_MODE0_INPUTPULLFILTER \ 258 (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) ///< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL 259 #define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) ///< Shifted mode PUSHPULL for GPIO_P_MODEL 260 #define GPIO_P_MODEL_MODE0_PUSHPULLALT \ 261 (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) ///< Shifted mode PUSHPULLALT for GPIO_P_MODEL 262 #define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) ///< Shifted mode WIREDOR for GPIO_P_MODEL 263 #define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN \ 264 (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) ///< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL 265 #define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) ///< Shifted mode WIREDAND for GPIO_P_MODEL 266 #define GPIO_P_MODEL_MODE0_WIREDANDFILTER \ 267 (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) ///< Shifted mode WIREDANDFILTER for GPIO_P_MODEL 268 #define GPIO_P_MODEL_MODE0_WIREDANDPULLUP \ 269 (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) ///< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL 270 #define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER \ 271 (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) ///< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL 272 #define GPIO_P_MODEL_MODE0_WIREDANDALT \ 273 (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) ///< Shifted mode WIREDANDALT for GPIO_P_MODEL 274 #define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER \ 275 (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) ///< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL 276 #define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP \ 277 (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) ///< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL 278 #define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER \ 279 (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) ///< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL 280 281 #define GPIO_PAD_0 0 ///< GPIO PAD number 0 282 #define GPIO_PAD_3 3 ///< GPIO PAD number 3 283 #define GPIO_PAD_4 4 ///< GPIO PAD number 4 284 #define GPIO_PAD_7 7 ///< GPIO PAD number 7 285 #define GPIO_PAD_8 8 ///< GPIO PAD number 8 286 287 #define HOST_PAD_SELECT 12 ///< GPIO Host PAD selection 288 #define PAD_SELECT 22 ///< GPIO PAD number 22 289 #define HOST_PAD_MIN 25 ///< GPIO Host PAD number 25 290 #define HOST_PAD_MAX 30 ///< GPIO Host PAD number 30 291 292 #define PRIORITY_19 19 ///< GPIO ulp group Interrupt priority 293 #define PRIORITY_21 21 ///< GPIO uulp group Interrupt priority 294 #define PRIORITY_50 50 ///< GPIO m4 group 0 Interrupt priority 295 #define PRIORITY_51 51 ///< GPIO m4 group 1 Interrupt priority 296 297 #define ULP_PORT_NUM 0 ///< GPIO ULP port number 298 #define UULP_PIN_MASK 0x1F ///< GPIO UULP pin mask 299 300 #define BIT_0 0 ///< GPIO bit 0 in configuration register 301 #define BIT_8 8 ///< GPIO bit 8 in configuration register 302 #define BIT_16 16 ///< GPIO bit 16 in configuration register 303 #define BIT_24 24 ///< GPIO bit 24 in configuration register 304 305 #define PORT_MASK 0xFFFF ///< GPIO port mask 306 #define INTR_CLR 0x07 ///< GPIO interrupt clear 307 #define INTERRUPT_MASK 0x0F ///< GPIO interrupt mask 308 #define MASK_CTRL 0x03 309 #define MASK_INTR 0x01 ///< GPIO interrupt mask 310 311 /** =========================================================================================================================== **/ 312 /** ================ GPIO ==================**/ 313 /** =========================================================================================================================== **/ 314 ///@brief HP GPIO PAD configuration register fields 315 typedef struct { 316 union { 317 __IOM uint32_t PAD_CONFIG_REG; ///< (@ 0x46004000) GPIO PAD configuration register 318 319 struct { 320 __IOM uint32_t PADCONFIG_E1_E2 : 2; ///< [1..0] Drive strength selector 321 __IOM uint32_t PADCONFIG_POS : 1; ///< [2..2] Power-on-Start enable 322 __IOM uint32_t PADCONFIG_SMT : 1; ///< [3..3] Active high Schmitt trigger (Hysteresis) select 323 __IOM uint32_t PADCONFIG_REN : 1; ///< [4..4] Active high receiver enable 324 __IOM uint32_t PADCONFIG_SR : 1; ///< [5..5] Slew Rate Control 325 __IOM uint32_t PADCONFIG_P1_P2 : 2; ///< [7..6] Driver disabled state control 326 __IOM uint32_t RESERVED1 : 24; ///< [31..8] Reserved1 327 } GPIO_PAD_CONFIG_REG_b; 328 }; 329 } PAD_CONFIG_Type; 330 331 ///@brief UULP GPIO PAD configuration register fields 332 typedef struct { 333 union { 334 __IOM uint32_t UULP_PAD_CONFIG_REG; ///< (@ 0x2404861C) UULP VBAT GPIO configuration register 335 336 struct { 337 __IOM uint32_t GPIO_MODE : 3; ///< [2..0] GPIO Mode for UULP_VBAT_GPIO_n(n=0:4) 338 __IOM uint32_t GPIO_REN : 1; ///< [3..3] Receiver of PAD enable 339 __IOM uint32_t GPIO_OEN : 1; ///< [4..4] Direction of PAD 340 __IOM uint32_t GPIO_OUTPUT : 1; ///< [5..5] Value driven on PAD in OUTPUT mode 341 __IOM uint32_t GPIO_PAD_SELECT : 1; ///< [6..6] PAD selection between M4,NWP 342 __IOM uint32_t RESERVED : 1; ///< [7..7] Reserved 343 __IOM uint32_t GPIO_POLARITY : 1; ///< [8..8] Polarity of UULP GPIO 344 __IOM uint32_t RESERVED1 : 23; ///< [31..9] Reserved1 345 } UULP_GPIO_PAD_CONFIG_REG_b; 346 }; 347 } UULP_PAD_CONFIG_Type; 348 349 ///@brief ULP GPIO PAD configuration register0 fields 350 typedef struct { 351 union { 352 __IOM uint32_t ULP_PAD_CONFIG_REG0; 353 354 struct { 355 __IOM uint32_t PADCONFIG_E1_E2_1 : 2; ///< [1..0] Drive strength selector for ULP_GPIO_0 - ULP_GPIO_3 356 __IOM uint32_t PADCONFIG_POS_1 : 1; ///< [2..2] Power on start enable for ULP_GPIO_0 - ULP_GPIO_3 357 __IOM uint32_t PADCONFIG_SMT_1 : 1; ///< [3..3] Active high schmitt trigger for ULP_GPIO_0 - ULP_GPIO_3 358 __IOM uint32_t RESERVED : 1; ///< [4..4] Reserved 359 __IOM uint32_t PADCONFIG_SR_1 : 1; ///< [5..5] Slew rate control for ULP_GPIO_0 - ULP_GPIO_3 360 __IOM uint32_t PADCONFIG_P1_P2_1 : 2; ///< [7..6] Driver disabled state control for ULP_GPIO_0 - ULP_GPIO_3 361 __IOM uint32_t PADCONFIG_E1_E2_2 : 2; ///< [9..8] Drive strength selector for ULP_GPIO_4 - ULP_GPIO_7 362 __IOM uint32_t PADCONFIG_POS_2 : 1; ///< [10..10] Power on start enable for ULP_GPIO_4 - ULP_GPIO_7 363 __IOM uint32_t PADCONFIG_SMT_2 : 1; ///< [11..11] Active high schmitt trigger for ULP_GPIO_4 - ULP_GPIO_7 364 __IOM uint32_t RESERVED1 : 1; ///< [12..12] Reserved1 365 __IOM uint32_t PADCONFIG_SR_2 : 1; ///< [13..13] Slew rate control for ULP_GPIO_4 - ULP_GPIO_7 366 __IOM uint32_t PADCONFIG_P1_P2_2 : 2; ///< [15..14] Driver disabled state control for ULP_GPIO_4 - ULP_GPIO_7 367 __IOM uint32_t RESERVED2 : 16; ///< [31..16] Reserved2 368 } ULP_GPIO_PAD_CONFIG_REG_0; 369 }; 370 } ULP_PAD_CONFIG_Type0; 371 372 ///@brief ULP GPIO PAD configuration register1 fields 373 typedef struct { 374 union { 375 __IOM uint32_t ULP_PAD_CONFIG_REG1; 376 377 struct { 378 __IOM uint32_t PADCONFIG_E1_E2_1 : 2; ///< [1..0] Drive strength selector for ULP_GPIO_8 - ULP_GPIO_11 379 __IOM uint32_t PADCONFIG_POS_1 : 1; ///< [2..2] Power on start enable for ULP_GPIO_8 - ULP_GPIO_11 380 __IOM uint32_t PADCONFIG_SMT_1 : 1; ///< [3..3] Active high schmitt trigger for ULP_GPIO_8 - ULP_GPIO_11 381 __IOM uint32_t RESERVED : 1; ///< [4..4] Reserved 382 __IOM uint32_t PADCONFIG_SR_1 : 1; ///< [5..5] Slew rate control for ULP_GPIO_8 - ULP_GPIO_11 383 __IOM uint32_t PADCONFIG_P1_P2_1 : 2; ///< [7..6] Driver disabled state control for ULP_GPIO_8 - ULP_GPIO_11 384 __IOM uint32_t RESERVED1 : 8; ///< [15..8] Reserved1 385 __IOM uint32_t RESERVED2 : 16; ///< [31..16] Reserved2 386 } ULP_GPIO_PAD_CONFIG_REG_1; 387 }; 388 } ULP_PAD_CONFIG_Type1; 389 390 ///@brief ULP GPIO PAD configuration register2 fields 391 typedef struct { 392 union { 393 __IOM uint32_t ULP_PAD_CONFIG_REG2; 394 395 struct { 396 __IOM uint32_t PADCONFIG_REN : 12; ///< [11..0] Active high receiver enable for ULP_GPIO_11 - ULP_GPIO_0 397 __IOM uint32_t RESERVED : 20; ///< [31..12] Reserved 398 } ULP_GPIO_PAD_CONFIG_REG_2; 399 }; 400 } ULP_PAD_CONFIG_Type2; 401 402 /** @} (end addtogroup GPIO) */ 403 404 #ifdef __cplusplus 405 } 406 #endif 407 408 #endif ///< SL_SI91X_GPIO_COMMONH 409 /**************************************************************************************************/ 410
