1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef UFS_H 8 #define UFS_H 9 10 #include <lib/utils_def.h> 11 12 /* register map of UFSHCI */ 13 /* Controller Capabilities */ 14 #define CAP 0x00 15 #define CAP_NUTRS_MASK 0x1F 16 17 /* UFS Version */ 18 #define VER 0x08 19 /* Host Controller Identification - Product ID */ 20 #define HCDDID 0x10 21 /* Host Controller Identification Descriptor - Manufacturer ID */ 22 #define HCPMID 0x14 23 /* Auto-Hibernate Idle Timer */ 24 #define AHIT 0x18 25 /* Interrupt Status */ 26 #define IS 0x20 27 /* Interrupt Enable */ 28 #define IE 0x24 29 /* System Bus Fatal Error Status */ 30 #define UFS_INT_SBFES (1 << 17) 31 /* Host Controller Fatal Error Status */ 32 #define UFS_INT_HCFES (1 << 16) 33 /* UTP Error Status */ 34 #define UFS_INT_UTPES (1 << 12) 35 /* Device Fatal Error Status */ 36 #define UFS_INT_DFES (1 << 11) 37 /* UIC Command Completion Status */ 38 #define UFS_INT_UCCS (1 << 10) 39 /* UTP Task Management Request Completion Status */ 40 #define UFS_INT_UTMRCS (1 << 9) 41 /* UIC Link Startup Status */ 42 #define UFS_INT_ULSS (1 << 8) 43 /* UIC Link Lost Status */ 44 #define UFS_INT_ULLS (1 << 7) 45 /* UIC Hibernate Enter Status */ 46 #define UFS_INT_UHES (1 << 6) 47 /* UIC Hibernate Exit Status */ 48 #define UFS_INT_UHXS (1 << 5) 49 /* UIC Power Mode Status */ 50 #define UFS_INT_UPMS (1 << 4) 51 /* UIC Test Mode Status */ 52 #define UFS_INT_UTMS (1 << 3) 53 /* UIC Error */ 54 #define UFS_INT_UE (1 << 2) 55 /* UIC DME_ENDPOINTRESET Indication */ 56 #define UFS_INT_UDEPRI (1 << 1) 57 /* UTP Transfer Request Completion Status */ 58 #define UFS_INT_UTRCS (1 << 0) 59 60 #define UFS_INT_FATAL (UFS_INT_DFES |\ 61 UFS_INT_HCFES |\ 62 UFS_INT_SBFES) 63 #define UFS_INT_ERR (UFS_INT_FATAL |\ 64 UFS_INT_UE) 65 66 #define UFS_UIC_PA_ERROR_MASK 0x8000001F 67 #define UFS_UIC_DL_ERROR_MASK 0x8000FFFF 68 #define UFS_UIC_NL_ERROR_MASK 0x80000007 69 #define UFS_UIC_TL_ERROR_MASK 0x8000007F 70 #define UFS_UIC_DME_ERROR_MASK 0x80000001 71 72 #define PA_INIT_ERR (1 << 13) 73 #define PA_LAYER_GEN_ERR (1 << 4) 74 75 /* Host Controller Status */ 76 #define HCS 0x30 77 #define HCS_UPMCRS_MASK (7 << 8) 78 #define HCS_PWR_LOCAL (1 << 8) 79 #define HCS_UCRDY (1 << 3) 80 #define HCS_UTMRLRDY (1 << 2) 81 #define HCS_UTRLRDY (1 << 1) 82 #define HCS_DP (1 << 0) 83 84 /* Host Controller Enable */ 85 #define HCE 0x34 86 #define HCE_ENABLE 1 87 #define HCE_DISABLE 0 88 89 /* Host UIC Error Code PHY Adapter Layer */ 90 #define UECPA 0x38 91 /* Host UIC Error Code Data Link Layer */ 92 #define UECDL 0x3C 93 /* Host UIC Error Code Network Layer */ 94 #define UECN 0x40 95 /* Host UIC Error Code Transport Layer */ 96 #define UECT 0x44 97 /* Host UIC Error Code */ 98 #define UECDME 0x48 99 /* UTP Transfer Request Interrupt Aggregation Control Register */ 100 #define UTRIACR 0x4C 101 #define UTRIACR_IAEN (1U << 31) 102 #define UTRIACR_IAPWEN (1 << 24) 103 #define UTRIACR_IASB (1 << 20) 104 #define UTRIACR_CTR (1 << 16) 105 #define UTRIACR_IACTH(x) (((x) & 0x1F) << 8) 106 #define UTRIACR_IATOVAL(x) ((x) & 0xFF) 107 108 /* UTP Transfer Request List Base Address */ 109 #define UTRLBA 0x50 110 /* UTP Transfer Request List Base Address Upper 32-bits */ 111 #define UTRLBAU 0x54 112 /* UTP Transfer Request List Door Bell Register */ 113 #define UTRLDBR 0x58 114 /* UTP Transfer Request List Clear Register */ 115 #define UTRLCLR 0x5C 116 /* UTP Transfer Request List Run Stop Register */ 117 #define UTRLRSR 0x60 118 #define UTMRLBA 0x70 119 #define UTMRLBAU 0x74 120 #define UTMRLDBR 0x78 121 #define UTMRLCLR 0x7C 122 #define UTMRLRSR 0x80 123 /* UIC Command */ 124 #define UICCMD 0x90 125 /* UIC Command Argument 1 */ 126 #define UCMDARG1 0x94 127 /* UIC Command Argument 2 */ 128 #define UCMDARG2 0x98 129 /* UIC Command Argument 3 */ 130 #define UCMDARG3 0x9C 131 132 #define UFS_BLOCK_SHIFT 12 /* 4KB */ 133 #define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT) 134 #define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1) 135 #define UFS_MAX_LUNS 8 136 137 /* UTP Transfer Request Descriptor */ 138 /* Command Type */ 139 #define CT_UFS_STORAGE 1 140 #define CT_SCSI 0 141 142 /* Data Direction */ 143 #define DD_OUT 2 /* Device --> Host */ 144 #define DD_IN 1 /* Host --> Device */ 145 #define DD_NO_DATA_TRANSFER 0 146 147 #define UTP_TRD_SIZE 32 148 149 /* Transaction Type */ 150 #define TRANS_TYPE_HD (1 << 7) /* E2ECRC */ 151 #define TRANS_TYPE_DD (1 << 6) 152 #define TRANS_TYPE_CODE_MASK 0x3F 153 #define QUERY_RESPONSE_UPIU (0x36 << 0) 154 #define READY_TO_TRANSACTION_UPIU (0x31 << 0) 155 #define DATA_IN_UPIU (0x22 << 0) 156 #define RESPONSE_UPIU (0x21 << 0) 157 #define NOP_IN_UPIU (0x20 << 0) 158 #define QUERY_REQUEST_UPIU (0x16 << 0) 159 #define DATA_OUT_UPIU (0x02 << 0) 160 #define CMD_UPIU (0x01 << 0) 161 #define NOP_OUT_UPIU (0x00 << 0) 162 163 #define OCS_SUCCESS 0x0 164 #define OCS_INVALID_FUNC_ATTRIBUTE 0x1 165 #define OCS_MISMATCH_REQUEST_SIZE 0x2 166 #define OCS_MISMATCH_RESPONSE_SIZE 0x3 167 #define OCS_PEER_COMMUNICATION_FAILURE 0x4 168 #define OCS_ABORTED 0x5 169 #define OCS_FATAL_ERROR 0x6 170 #define OCS_MASK 0xF 171 172 /* UIC Command */ 173 #define DME_GET 0x01 174 #define DME_SET 0x02 175 #define DME_PEER_GET 0x03 176 #define DME_PEER_SET 0x04 177 #define DME_POWERON 0x10 178 #define DME_POWEROFF 0x11 179 #define DME_ENABLE 0x12 180 #define DME_RESET 0x14 181 #define DME_ENDPOINTRESET 0x15 182 #define DME_LINKSTARTUP 0x16 183 #define DME_HIBERNATE_ENTER 0x17 184 #define DME_HIBERNATE_EXIT 0x18 185 #define DME_TEST_MODE 0x1A 186 187 #define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF) 188 189 #define CONFIG_RESULT_CODE_MASK 0xFF 190 191 #define CDBCMD_TEST_UNIT_READY 0x00 192 #define CDBCMD_READ_6 0x08 193 #define CDBCMD_WRITE_6 0x0A 194 #define CDBCMD_START_STOP_UNIT 0x1B 195 #define CDBCMD_READ_CAPACITY_10 0x25 196 #define CDBCMD_READ_10 0x28 197 #define CDBCMD_WRITE_10 0x2A 198 #define CDBCMD_READ_16 0x88 199 #define CDBCMD_WRITE_16 0x8A 200 #define CDBCMD_READ_CAPACITY_16 0x9E 201 #define CDBCMD_REPORT_LUNS 0xA0 202 203 #define UPIU_FLAGS_R (1 << 6) 204 #define UPIU_FLAGS_W (1 << 5) 205 #define UPIU_FLAGS_ATTR_MASK (3 << 0) 206 #define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */ 207 #define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */ 208 #define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */ 209 #define UPIU_FLAGS_ATTR_ACA (3 << 0) 210 #define UPIU_FLAGS_O (1 << 6) 211 #define UPIU_FLAGS_U (1 << 5) 212 #define UPIU_FLAGS_D (1 << 4) 213 214 #define QUERY_FUNC_STD_READ 0x01 215 #define QUERY_FUNC_STD_WRITE 0x81 216 217 #define QUERY_NOP 0x00 218 #define QUERY_READ_DESC 0x01 219 #define QUERY_WRITE_DESC 0x02 220 #define QUERY_READ_ATTR 0x03 221 #define QUERY_WRITE_ATTR 0x04 222 #define QUERY_READ_FLAG 0x05 223 #define QUERY_SET_FLAG 0x06 224 #define QUERY_CLEAR_FLAG 0x07 225 #define QUERY_TOGGLE_FLAG 0x08 226 227 #define RW_WITHOUT_CACHE 0x18 228 229 #define DESC_TYPE_DEVICE 0x00 230 #define DESC_TYPE_CONFIGURATION 0x01 231 #define DESC_TYPE_UNIT 0x02 232 #define DESC_TYPE_INTERCONNECT 0x04 233 #define DESC_TYPE_STRING 0x05 234 235 #define DESC_DEVICE_MAX_SIZE 0x1F 236 #define DEVICE_DESC_PARAM_MANF_ID 0x18 237 238 #define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */ 239 #define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */ 240 241 #define DEVICE_DESCRIPTOR_LEN 0x40 242 #define UNIT_DESCRIPTOR_LEN 0x23 243 244 #define QUERY_RESP_SUCCESS 0x00 245 #define QUERY_RESP_OPCODE 0xFE 246 #define QUERY_RESP_GENERAL_FAIL 0xFF 247 248 #define SENSE_KEY_NO_SENSE 0x00 249 #define SENSE_KEY_RECOVERED_ERROR 0x01 250 #define SENSE_KEY_NOT_READY 0x02 251 #define SENSE_KEY_MEDIUM_ERROR 0x03 252 #define SENSE_KEY_HARDWARE_ERROR 0x04 253 #define SENSE_KEY_ILLEGAL_REQUEST 0x05 254 #define SENSE_KEY_UNIT_ATTENTION 0x06 255 #define SENSE_KEY_DATA_PROTECT 0x07 256 #define SENSE_KEY_BLANK_CHECK 0x08 257 #define SENSE_KEY_VENDOR_SPECIFIC 0x09 258 #define SENSE_KEY_COPY_ABORTED 0x0A 259 #define SENSE_KEY_ABORTED_COMMAND 0x0B 260 #define SENSE_KEY_VOLUME_OVERFLOW 0x0D 261 #define SENSE_KEY_MISCOMPARE 0x0E 262 263 #define SENSE_DATA_VALID 0x70 264 #define SENSE_DATA_LENGTH 18 265 266 #define READ_CAPACITY_LENGTH 8 267 268 #define FLAG_DEVICE_INIT 0x01 269 270 #define UFS_VENDOR_SKHYNIX U(0x1AD) 271 272 #define MAX_MODEL_LEN 16 273 274 /* maximum number of retries for a general UIC command */ 275 #define UFS_UIC_COMMAND_RETRIES 3 276 277 /* maximum number of retries for a transfer command */ 278 #define UFS_CMD_RETRIES 3 279 280 /* maximum number of retries for reading UFS capacity */ 281 #define UFS_READ_CAPACITY_RETRIES 10 282 283 /* maximum number of link-startup retries */ 284 #define DME_LINKSTARTUP_RETRIES 10 285 286 #define HCE_ENABLE_OUTER_RETRIES 3 287 #define HCE_ENABLE_INNER_RETRIES 50 288 #define HCE_ENABLE_TIMEOUT_US 100 289 #define HCE_DISABLE_TIMEOUT_US 1000 290 291 #define FDEVICEINIT_TIMEOUT_MS 1500 292 293 #define UIC_CMD_TIMEOUT_MS 500 294 #define QUERY_REQ_TIMEOUT_MS 1500 295 #define NOP_OUT_TIMEOUT_MS 50 296 #define CMD_TIMEOUT_MS 5000 297 298 /** 299 * ufs_dev_desc - ufs device details from the device descriptor 300 * @wmanufacturerid: card details 301 * @model: card model 302 */ 303 struct ufs_dev_desc { 304 uint16_t wmanufacturerid; 305 int8_t model[MAX_MODEL_LEN + 1]; 306 }; 307 308 /* UFS Driver Flags */ 309 #define UFS_FLAGS_SKIPINIT (1 << 0) 310 #define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2) 311 312 typedef struct sense_data { 313 uint8_t resp_code : 7; 314 uint8_t valid : 1; 315 uint8_t reserved0; 316 uint8_t sense_key : 4; 317 uint8_t reserved1 : 1; 318 uint8_t ili : 1; 319 uint8_t eom : 1; 320 uint8_t file_mark : 1; 321 uint8_t info[4]; 322 uint8_t asl; 323 uint8_t cmd_spec_len[4]; 324 uint8_t asc; 325 uint8_t ascq; 326 uint8_t fruc; 327 uint8_t sense_key_spec0 : 7; 328 uint8_t sksv : 1; 329 uint8_t sense_key_spec1; 330 uint8_t sense_key_spec2; 331 } sense_data_t; 332 333 /* UTP Transfer Request Descriptor */ 334 typedef struct utrd_header { 335 uint32_t reserved0 : 24; 336 uint32_t i : 1; /* interrupt */ 337 uint32_t dd : 2; /* data direction */ 338 uint32_t reserved1 : 1; 339 uint32_t ct : 4; /* command type */ 340 uint32_t reserved2; 341 uint32_t ocs : 8; /* Overall Command Status */ 342 uint32_t reserved3 : 24; 343 uint32_t reserved4; 344 uint32_t ucdba; /* aligned to 128-byte */ 345 uint32_t ucdbau; /* Upper 32-bits */ 346 uint32_t rul : 16; /* Response UPIU Length */ 347 uint32_t ruo : 16; /* Response UPIU Offset */ 348 uint32_t prdtl : 16; /* PRDT Length */ 349 uint32_t prdto : 16; /* PRDT Offset */ 350 } utrd_header_t; /* 8 words with little endian */ 351 352 /* UTP Task Management Request Descriptor */ 353 typedef struct utp_utmrd { 354 /* 4 words with little endian */ 355 uint32_t reserved0 : 24; 356 uint32_t i : 1; /* interrupt */ 357 uint32_t reserved1 : 7; 358 uint32_t reserved2; 359 uint32_t ocs : 8; /* Overall Command Status */ 360 uint32_t reserved3 : 24; 361 uint32_t reserved4; 362 363 /* followed by 8 words UPIU with big endian */ 364 365 /* followed by 8 words Response UPIU with big endian */ 366 } utp_utmrd_t; 367 368 /* NOP OUT UPIU */ 369 typedef struct nop_out_upiu { 370 uint8_t trans_type; 371 uint8_t flags; 372 uint8_t reserved0; 373 uint8_t task_tag; 374 uint8_t reserved1; 375 uint8_t reserved2; 376 uint8_t reserved3; 377 uint8_t reserved4; 378 uint8_t total_ehs_len; 379 uint8_t reserved5; 380 uint16_t data_segment_len; 381 uint32_t reserved6; 382 uint32_t reserved7; 383 uint32_t reserved8; 384 uint32_t reserved9; 385 uint32_t reserved10; 386 uint32_t e2ecrc; 387 } nop_out_upiu_t; /* 36 bytes with big endian */ 388 389 /* NOP IN UPIU */ 390 typedef struct nop_in_upiu { 391 uint8_t trans_type; 392 uint8_t flags; 393 uint8_t reserved0; 394 uint8_t task_tag; 395 uint8_t reserved1; 396 uint8_t reserved2; 397 uint8_t response; 398 uint8_t reserved3; 399 uint8_t total_ehs_len; 400 uint8_t dev_info; 401 uint16_t data_segment_len; 402 uint32_t reserved4; 403 uint32_t reserved5; 404 uint32_t reserved6; 405 uint32_t reserved7; 406 uint32_t reserved8; 407 uint32_t e2ecrc; 408 } nop_in_upiu_t; /* 36 bytes with big endian */ 409 410 /* Command UPIU */ 411 typedef struct cmd_upiu { 412 uint8_t trans_type; 413 uint8_t flags; 414 uint8_t lun; 415 uint8_t task_tag; 416 uint8_t cmd_set_type; 417 uint8_t reserved0; 418 uint8_t reserved1; 419 uint8_t reserved2; 420 uint8_t total_ehs_len; 421 uint8_t reserved3; 422 uint16_t data_segment_len; 423 uint32_t exp_data_trans_len; 424 /* 425 * A CDB has a fixed length of 16bytes or a variable length 426 * of between 12 and 260 bytes 427 */ 428 uint8_t cdb[16]; /* little endian */ 429 } cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */ 430 431 typedef struct query_desc { 432 uint8_t opcode; 433 uint8_t idn; 434 uint8_t index; 435 uint8_t selector; 436 uint8_t reserved0[2]; 437 uint16_t length; 438 uint32_t reserved2[2]; 439 } query_desc_t; /* 16 bytes with big endian */ 440 441 typedef struct query_flag { 442 uint8_t opcode; 443 uint8_t idn; 444 uint8_t index; 445 uint8_t selector; 446 uint8_t reserved0[7]; 447 uint8_t value; 448 uint32_t reserved8; 449 } query_flag_t; /* 16 bytes with big endian */ 450 451 typedef struct query_attr { 452 uint8_t opcode; 453 uint8_t idn; 454 uint8_t index; 455 uint8_t selector; 456 uint8_t reserved0[4]; 457 uint32_t value; /* little endian */ 458 uint32_t reserved4; 459 } query_attr_t; /* 16 bytes with big endian except for value */ 460 461 /* Query Request UPIU */ 462 typedef struct query_upiu { 463 uint8_t trans_type; 464 uint8_t flags; 465 uint8_t reserved0; 466 uint8_t task_tag; 467 uint8_t reserved1; 468 uint8_t query_func; 469 uint8_t reserved2; 470 uint8_t reserved3; 471 uint8_t total_ehs_len; 472 uint8_t reserved4; 473 uint16_t data_segment_len; 474 /* Transaction Specific Fields */ 475 union { 476 query_desc_t desc; 477 query_flag_t flag; 478 query_attr_t attr; 479 } ts; 480 uint32_t reserved5; 481 } query_upiu_t; /* 32 bytes with big endian */ 482 483 /* Query Response UPIU */ 484 typedef struct query_resp_upiu { 485 uint8_t trans_type; 486 uint8_t flags; 487 uint8_t reserved0; 488 uint8_t task_tag; 489 uint8_t reserved1; 490 uint8_t query_func; 491 uint8_t query_resp; 492 uint8_t reserved2; 493 uint8_t total_ehs_len; 494 uint8_t dev_info; 495 uint16_t data_segment_len; 496 union { 497 query_desc_t desc; 498 query_flag_t flag; 499 query_attr_t attr; 500 } ts; 501 uint32_t reserved3; 502 } query_resp_upiu_t; /* 32 bytes with big endian */ 503 504 /* Response UPIU */ 505 typedef struct resp_upiu { 506 uint8_t trans_type; 507 uint8_t flags; 508 uint8_t lun; 509 uint8_t task_tag; 510 uint8_t cmd_set_type; 511 uint8_t reserved0; 512 uint8_t reserved1; 513 uint8_t status; 514 uint8_t total_ehs_len; 515 uint8_t dev_info; 516 uint16_t data_segment_len; 517 uint32_t res_trans_cnt; /* Residual Transfer Count */ 518 uint32_t reserved2[4]; 519 uint16_t sense_data_len; 520 union { 521 uint8_t sense_data[18]; 522 sense_data_t sense; 523 } sd; 524 } resp_upiu_t; /* 52 bytes with big endian */ 525 526 typedef struct cmd_info { 527 uintptr_t buf; 528 size_t length; 529 int lba; 530 uint8_t op; 531 uint8_t direction; 532 uint8_t lun; 533 } cmd_info_t; 534 535 typedef struct utp_utrd { 536 uintptr_t header; /* utrd_header_t */ 537 uintptr_t upiu; 538 uintptr_t resp_upiu; 539 uintptr_t prdt; 540 size_t size_upiu; 541 size_t size_resp_upiu; 542 size_t prdt_length; 543 int task_tag; 544 } utp_utrd_t; 545 546 /* Physical Region Description Table */ 547 typedef struct prdt { 548 uint32_t dba; /* Data Base Address */ 549 uint32_t dbau; /* Data Base Address Upper 32-bits */ 550 uint32_t reserved0; 551 uint32_t dbc : 18; /* Data Byte Count */ 552 uint32_t reserved1 : 14; 553 } prdt_t; 554 555 typedef struct uic_cmd { 556 uint32_t op; 557 uint32_t arg1; 558 uint32_t arg2; 559 uint32_t arg3; 560 } uic_cmd_t; 561 562 typedef struct ufs_params { 563 uintptr_t reg_base; 564 uintptr_t desc_base; 565 size_t desc_size; 566 unsigned long flags; 567 } ufs_params_t; 568 569 typedef struct ufs_ops { 570 int (*phy_init)(ufs_params_t *params); 571 int (*phy_set_pwr_mode)(ufs_params_t *params); 572 } ufs_ops_t; 573 574 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd); 575 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val); 576 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val); 577 578 unsigned int ufs_read_attr(int idn); 579 void ufs_write_attr(int idn, unsigned int value); 580 unsigned int ufs_read_flag(int idn); 581 void ufs_set_flag(int idn); 582 void ufs_clear_flag(int idn); 583 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size); 584 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size); 585 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size); 586 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size); 587 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params); 588 589 #endif /* UFS_H */ 590
