1 /**************************************************************************//**
2 * @file utcpd.c
3 * @version V1.00
4 * @brief M2L31 series UTCPD driver source file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #include "NuMicro.h"
10 #include "utcpdlib.h"
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17 //uint8_t I2C_ADDR[4] = {0x0, 0x0, 0x0, 0x0};
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup UTCPD_Driver UTCPD Driver
23 @{
24 */
25
26 /** @addtogroup UTCPD_EXPORTED_FUNCTIONS UTCPD Exported Functions
27 @{
28 */
29
30
31 /**
32 * @brief Clear UTCPD Alert Status
33 *
34 * @param[in] port Specify UTCPD port
35 * @param[in] AlertStClr Alert status clear
36 * - \ref UTCPD_ALERT_CCSCHIS
37 * - \ref UTCPD_ALERT_PWRSCHIS
38 * - \ref UTCPD_ALERT_RXSOPIS
39 * - \ref UTCPD_ALERT_RXHRSTIS
40 * - \ref UTCPD_ALERT_TXFAILIS
41 * - \ref UTCPD_ALERT_TXDCUIS
42 * - \ref UTCPD_ALERT_TXOKIS
43 * - \ref UTCPD_ALERT_VBAMHIS
44 * - \ref UTCPD_ALERT_VBAMLIS
45 * - \ref UTCPD_ALERT_FUTIS
46 * - \ref UTCPD_ALERT_RXOFIS
47 * - \ref UTCPD_ALERT_SKDCDTIS
48 * - \ref UTCPD_ALERT_VNDIS
49 * @return 0: Successful, 1: Fail
50 *
51 * @details Write One Clear
52 *
53 */
UTCPD_GetAlertStatus(int port,int * i32AlertSts)54 int32_t UTCPD_GetAlertStatus(int port, int* i32AlertSts)
55 {
56 return tcpc_addr_read16(port, NULL, TCPC_REG_ALERT, i32AlertSts);
57 }
58
59 /**
60 * @brief Get UTCPD Alert Status
61 *
62 * @param[in] port Specify UTCPD port
63 * @param[in] AlertStClr Alert status clear
64 * - \ref UTCPD_ALERT_CCSCHIS
65 * - \ref UTCPD_ALERT_PWRSCHIS
66 * - \ref UTCPD_ALERT_RXSOPIS
67 * - \ref UTCPD_ALERT_RXHRSTIS
68 * - \ref UTCPD_ALERT_TXFAILIS
69 * - \ref UTCPD_ALERT_TXDCUIS
70 * - \ref UTCPD_ALERT_TXOKIS
71 * - \ref UTCPD_ALERT_VBAMHIS
72 * - \ref UTCPD_ALERT_VBAMLIS
73 * - \ref UTCPD_ALERT_FUTIS
74 * - \ref UTCPD_ALERT_RXOFIS
75 * - \ref UTCPD_ALERT_SKDCDTIS
76 * - \ref UTCPD_ALERT_VNDIS
77 * @return 0: Successful, 1: Fail
78 *
79 * @details Write One Clear
80 *
81 */
UTCPD_ClearAlertStatus(int port,int AlertStClr)82 int32_t UTCPD_ClearAlertStatus(int port, int AlertStClr)
83 {
84 return tcpc_update16(port, TCPC_REG_ALERT, AlertStClr, MASK_SET);
85 }
86
87 /**
88 * @brief Enable UTCPD Alert Mask
89 *
90 * @param[in] port Specified UTCPD port
91 * @param[in] mask_set Alert bit mask
92 * - \ref UTCPD_ALERTM_CCSCHIE
93 * - \ref UTCPD_ALERTM_PWRSCHIE
94 * - \ref UTCPD_ALERTM_RXSOPIE
95 * - \ref UTCPD_ALERTM_RXHRSTIE
96 * - \ref UTCPD_ALERTM_TXFAILIE
97 * - \ref UTCPD_ALERTM_TXDCUIE
98 * - \ref UTCPD_ALERTM_TXOKIE
99 * - \ref UTCPD_ALERTM_VBAMHIE
100 * - \ref UTCPD_ALERTM_VBAMLIE
101 * - \ref UTCPD_ALERTM_FUTIE
102 * - \ref UTCPD_ALERTM_RXOFIE
103 * - \ref UTCPD_ALERTM_SKDCDTIE
104 * - \ref UTCPD_ALERTM_VNDIE
105 * @return 0: Successful, 1: Fail
106 *
107 * @details None
108 *
109 */
UTCPD_EnableAlertMask(int port,int mask_set)110 int32_t UTCPD_EnableAlertMask(int port, int mask_set)
111 {
112 return tcpc_update16(port, TCPC_REG_ALERT_MASK, mask_set, MASK_SET);
113 }
114
115
116 /**
117 * @brief Disable UTCPD Alert Mask
118 *
119 * @param[in] port Specify UTCPD port
120 * @param[in] mask_clr Alert bit mask
121 * - \ref UTCPD_ALERTM_CCSCHIE
122 * - \ref UTCPD_ALERTM_PWRSCHIE
123 * - \ref UTCPD_ALERTM_RXSOPIE
124 * - \ref UTCPD_ALERTM_RXHRSTIE
125 * - \ref UTCPD_ALERTM_TXFAILIE
126 * - \ref UTCPD_ALERTM_TXDCUIE
127 * - \ref UTCPD_ALERTM_TXOKIE
128 * - \ref UTCPD_ALERTM_VBAMHIE
129 * - \ref UTCPD_ALERTM_VBAMLIE
130 * - \ref UTCPD_ALERTM_FUTIE
131 * - \ref UTCPD_ALERTM_RXOFIE
132 * - \ref UTCPD_ALERTM_SKDCDTIE
133 * - \ref UTCPD_ALERTM_VNDIE
134 *
135 * @return 0: Successful, 1: Fail
136 *
137 * @details None
138 *
139 */
UTCPD_DisableAlertMask(int port,int mask_clr)140 int32_t UTCPD_DisableAlertMask(int port, int mask_clr)
141 {
142 return tcpc_update16(port, TCPC_REG_ALERT_MASK, mask_clr, MASK_CLR);
143 }
144
145 /**
146 * @brief Enable UTCPD Power Status Mask
147 *
148 * @param[in] port Specified UTCPD port
149 * @param[in] mask_set Power status bit mask
150 * - \ref NPD48_PWRSM_SKVBIE
151 * - \ref NPD48_PWRSM_VCPSIE
152 * - \ref NPD48_PWRSM_VBPSIE
153 * - \ref NPD48_PWRSM_VBDTDGIE
154 * - \ref NPD48_PWRSM_SRVBIE
155 * - \ref NPD48_PWRSM_SRHVIE
156 * - \ref NPD48_PWRSM_DACONIE
157 *
158 * @return 0: Successful, 1: Fail
159 *
160 * @details None
161 *
162 */
UTCPD_EnablePowerStatusMask(int port,int mask_set)163 int32_t UTCPD_EnablePowerStatusMask(int port, int mask_set)
164 {
165 return tcpc_update16(port, TCPC_REG_POWER_STATUS_MASK, mask_set, MASK_SET);
166 }
167
168 /**
169 * @brief Disable UTCPD Power Status Mask
170 *
171 * @param[in] port Specify UTCPD port
172 * @param[in] mask_clr Power bit mask
173 * - \ref UTCPD_PWRSM_SKVBIE
174 * - \ref UTCPD_PWRSM_VCPSIE
175 * - \ref UTCPD_PWRSM_VBPSIE
176 * - \ref UTCPD_PWRSM_VBDTDGIE
177 * - \ref UTCPD_PWRSM_SRVBIE
178 * - \ref UTCPD_PWRSM_SRHVIE
179 * - \ref UTCPD_PWRSM_DACONIE
180 *
181 * @return 0: Successful, 1: Fail
182 *
183 * @details None
184 *
185 */
UTCPD_DisablePowerStatusMask(int port,int mask_clr)186 int32_t UTCPD_DisablePowerStatusMask(int port, int mask_clr)
187 {
188 return tcpc_update16(port, TCPC_REG_POWER_STATUS_MASK, mask_clr, MASK_CLR);
189 }
190
191
192 /**
193 * @brief Enable UTCPD Fault Status Mask
194 *
195 * @param[in] port Specified UTCPD port
196 * @param[in] mask_set Fault Status bit mask
197 * - \ref UTCPD_FAULTSM_VCOCIE
198 * - \ref UTCPD_FAULTSM_VBOVIE
199 * - \ref UTCPD_FAULTSM_VBOCIE
200 * - \ref UTCPD_FAULTSM_FDGFALIE
201 * - \ref UTCPD_FAULTSM_ADGFALIE
202 * - \ref UTCPD_FAULTSM_FOFFVBIE
203 * @return 0: Successful, 1: Fail
204 *
205 * @details None
206 *
207 */
UTCPD_EnableFaultMask(int port,int mask_set)208 int32_t UTCPD_EnableFaultMask(int port, int mask_set)
209 {
210 return tcpc_update16(port, TCPC_REG_FAULT_STATUS_MASK, mask_set, MASK_SET);
211 }
212
213 /**
214 * @brief Disable UTCPD Fault Status Mask
215 *
216 * @param[in] port Specify UTCPD port
217 * @param[in] mask_clr Fault Status bit mask
218 * - \ref UTCPD_FAULTSM_VCOCIE
219 * - \ref UTCPD_FAULTSM_VBOVIE
220 * - \ref UTCPD_FAULTSM_VBOCIE
221 * - \ref UTCPD_FAULTSM_FDGFALIE
222 * - \ref UTCPD_FAULTSM_ADGFALIE
223 * - \ref UTCPD_FAULTSM_FOFFVBIE
224 * @return 0: Successful, 1: Fail
225 *
226 * @details None
227 *
228 */
UTCPD_DisableFaultMask(int port,int mask_clr)229 int32_t UTCPD_DisableFaultMask(int port, int mask_clr)
230 {
231 return tcpc_update16(port, TCPC_REG_FAULT_STATUS_MASK, mask_clr, MASK_CLR);
232 }
233
234 /**
235 * @brief Enable UTCPD Power Control
236 *
237 * @param[in] port Specified UTCPD port
238 * @param[in] mask_set Power Control bit mask
239 * - \ref UTCPD_PWRCTL_VCEN
240 * - \ref UTCPD_PWRCTL_VCPWR
241 * - \ref UTCPD_PWRCTL_FDGEN
242 * - \ref UTCPD_PWRCTL_BDGEN
243 * - \ref UTCPD_PWRCTL_ADGDC
244 * - \ref UTCPD_PWRCTL_DSVBAM_DIS
245 * - \ref UTCPD_PWRCTL_VBMONI_DIS
246 *
247 * @return None
248 *
249 * @details Remember that VBUS Monitor and VBUS Alarm are "0" enabled. And both are "1" disabled
250 *
251 */
UTCPD_EnablePowerCtrl(int port,uint32_t mask_set)252 int32_t UTCPD_EnablePowerCtrl(int port, uint32_t mask_set)
253 {
254 return tcpc_update16(port, TCPC_REG_POWER_CTRL, mask_set, MASK_SET); /* VBUS Monitor and VBUS Alarm are 0 to enable */
255 }
256
257 /**
258 * @brief Disable UTCPD Power Control
259 *
260 * @param[in] port Specified UTCPD port
261 * @param[in] mask_set Power Control bit mask
262 * - \ref UTCPD_PWRCTL_VCEN
263 * - \ref UTCPD_PWRCTL_VCPWR
264 * - \ref UTCPD_PWRCTL_FDGEN
265 * - \ref UTCPD_PWRCTL_BDGEN
266 * - \ref UTCPD_PWRCTL_ADGDC
267 * - \ref UTCPD_PWRCTL_DSVBAM_DIS
268 * - \ref UTCPD_PWRCTL_VBMONI_DIS
269 * @return None
270 *
271 * @details Remember that VBUS Monitor and VBUS Alarm are "0" enabled. And both are "1" disabled
272 *
273 */
UTCPD_DisablePowerCtrl(int port,uint32_t maskclr)274 int32_t UTCPD_DisablePowerCtrl(int port, uint32_t maskclr)
275 {
276 return tcpc_update16(port, TCPC_REG_POWER_CTRL, maskclr, MASK_CLR); /* VBUS Monitor and VBUS Alarm are 1 to disable */
277 }
278
279
280 /**
281 * @brief Enable UTCPD Fault Control
282 *
283 * @param[in] port Specified UTCPD port
284 * @param[in] mask_set Fault bit mask
285 * - \ref UTCPD_FAULTCTL_VCOCDTDS
286 * - \ref UTCPD_FAULTCTL_VBOVDTDS
287 * - \ref UTCPD_FAULTCTL_VBOCDTDS
288 * - \ref UTCPD_FAULTCTL_VBDGTMDS
289 * - \ref UTCPD_FAULTCTL_FOFFVBDS
290 *
291 * @return None
292 *
293 * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .
294 *
295 */
UTCPD_EnableFaultCtrl(int port,uint32_t mask_set)296 int32_t UTCPD_EnableFaultCtrl(int port, uint32_t mask_set)
297 {
298 return tcpc_update16(port, TCPC_REG_FAULT_CTRL, mask_set, MASK_CLR); /* 0 to enable */
299 }
300
301 /**
302 * @brief Disable UTCPD Fault Control
303 *
304 * @param[in] port Specified UTCPD port
305 * @param[in] mask_set Fault bit mask
306 *
307 * @return None
308 *
309 * @details None
310 *
311 */
UTCPD_DisableFaultCtrl(int port,uint32_t maskclr)312 int32_t UTCPD_DisableFaultCtrl(int port, uint32_t maskclr)
313 {
314 return tcpc_update16(port, TCPC_REG_FAULT_CTRL, maskclr, MASK_SET); /* 1 to disable */
315 }
316
317
318
319 /**
320 * @brief Clear UTCPD Power Status
321 *
322 * @param[in] port Specify UTCPD port
323 * @param[in] PowerStClr Power status clear
324 * - \ref UTCPD_PWRSTS_SKVB
325 * - \ref UTCPD_PWRSTS_VCPS
326 * - \ref UTCPD_PWRSTS_VBPS
327 * - \ref UTCPD_PWRSTS_VBPSDTEN
328 * - \ref UTCPD_PWRSTS_SRVB
329 * - \ref UTCPD_PWRSTS_SRHV
330 * - \ref UTCPD_PWRSTS_DACON
331 *
332 * @return 0: Successful, 1: Fail
333 *
334 * @details None
335 *
336 */
UTCPD_ClearPowerStatus(int port,int PowerStClr)337 int32_t UTCPD_ClearPowerStatus(int port, int PowerStClr)
338 {
339 return tcpc_update16(port, TCPC_REG_POWER_STATUS, PowerStClr, MASK_CLR);
340 }
341
342 /**
343 * @brief Enable UTCPD Fault Status Mask
344 *
345 * @param[in] port Specified UTCPD port
346 * @param[in] mask_set Fault status bit mask
347 *
348 * @return 0: Successful, 1: Fail
349 *
350 * @details None
351 *
352 */
UTCPD_EnableFaultStatusMask(int port,int mask_set)353 int32_t UTCPD_EnableFaultStatusMask(int port, int mask_set)
354 {
355 return tcpc_update16(port, TCPC_REG_FAULT_STATUS, mask_set, MASK_SET);
356 }
357
358 /**
359 * @brief Disable UTCPD Fault Status Mask
360 *
361 * @param[in] port Specify UTCPD port
362 * @param[in] mask_clr Fault bit mask
363 *
364 * @return 0: Successful, 1: Fail
365 *
366 * @details None
367 */
UTCPD_DisableFaultStatusMask(int port,int mask_clr)368 int32_t UTCPD_DisableFaultStatusMask(int port, int mask_clr)
369 {
370 return tcpc_update16(port, TCPC_REG_FAULT_STATUS_MASK, mask_clr, MASK_CLR);
371 }
372
373 /**
374 * @brief Get UTCPD Fault Status
375 *
376 * @param[in] port Specify UTCPD port
377 * @param[in] pi32RegData Fault status
378 *
379 * @return 0: Successful, 1: Fail
380 *
381 * @details None
382 *
383 */
UTCPD_GetFaultStatus(int port,int * pi32RegData)384 int32_t UTCPD_GetFaultStatus(int port, int* pi32RegData)
385 {
386 return tcpc_addr_read16(port, NULL, TCPC_REG_FAULT_STATUS, pi32RegData);
387 }
388
389 /**
390 * @brief Clear UTCPD Fault Status
391 *
392 * @param[in] port Specify UTCPD port
393 * @param[in] FaultStClr Fault status clear
394 *
395 * @return 0: Successful, 1: Fail
396 *
397 * @details None
398 *
399 */
UTCPD_ClearFaultStatus(int port,int FaultStClr)400 int32_t UTCPD_ClearFaultStatus(int port, int FaultStClr)
401 {
402 return tcpc_update16(port, TCPC_REG_FAULT_STATUS, FaultStClr, MASK_CLR);
403 }
404
405 /**
406 * @brief Set Role Control
407 *
408 * @param[in] port Specify UTCPD port
409 * @param[in] u32DrpToggle DRP toggling
410 * - \ref UTCPD_ROLECTL_DRP
411 * - \ref NULL,
412 * @param[in] u32RpValue Rp pull up value
413 * - \ref UTCPD_ROLECTL_RPVALUE_DEF
414 * - \ref UTCPD_ROLECTL_RPVALUE_1P5A
415 * - \ref UTCPD_ROLECTL_RPVALUE_3A
416 * @param[in] u32CC2 Force CC2 state
417 * - \ref UTCPD_ROLECTL_CC2_RA
418 * - \ref UTCPD_ROLECTL_CC2_RP
419 * - \ref UTCPD_ROLECTL_CC2_RD
420 * - \ref UTCPD_ROLECTL_CC2_OPEN
421 * @param[in] u32CC1 Force CC1 state
422 * - \ref UTCPD_ROLECTL_CC1_RA
423 * - \ref UTCPD_ROLECTL_CC1_RP
424 * - \ref UTCPD_ROLECTL_CC1_RD
425 * - \ref UTCPD_ROLECTL_CC1_OPEN
426 * @return 0: Successful, 1: Fail
427 *
428 * @details None
429 *
430 */
UTCPD_SetRoleCtrl(int port,uint32_t u32DrpToggle,uint32_t u32Rpvalue,uint32_t u32CC2,uint32_t u32CC1)431 int32_t UTCPD_SetRoleCtrl(int port, uint32_t u32DrpToggle, uint32_t u32Rpvalue, uint32_t u32CC2, uint32_t u32CC1)
432 {
433 uint8_t reg_set = u32DrpToggle | u32Rpvalue | u32CC2 | u32CC1;
434 return tcpc_addr_write16(port, NULL, TCPC_REG_ROLE_CTRL, reg_set);
435 }
436
437 /**
438 * @brief Get Role Control
439 *
440 * @param[in] port Specify UTCPD port
441 * @param[in] u32DrpToggle DRP toggling
442 * - \ref UTCPD_ROLECTL_DRP
443 * - \ref NULL,
444 * @param[in] u32RpValue Rp pull up value
445 * - \ref UTCPD_ROLECTL_RPVALUE_DEF
446 * - \ref UTCPD_ROLECTL_RPVALUE_1P5A
447 * - \ref UTCPD_ROLECTL_RPVALUE_3A
448 * @param[in] u32CC2 Force CC2 state
449 * - \ref UTCPD_ROLECTL_CC2_RA
450 * - \ref UTCPD_ROLECTL_CC2_RP
451 * - \ref UTCPD_ROLECTL_CC2_RD
452 * - \ref UTCPD_ROLECTL_CC2_OPEN
453 * @param[in] u32CC1 Force CC1 state
454 * - \ref UTCPD_ROLECTL_CC1_RA
455 * - \ref UTCPD_ROLECTL_CC1_RP
456 * - \ref UTCPD_ROLECTL_CC1_RD
457 * - \ref UTCPD_ROLECTL_CC1_OPEN
458 * @return 0: Successful, 1: Fail
459 *
460 * @details None
461 */
UTCPD_GetRoleCtrl(int port,uint32_t * pu32DrpToggle,uint32_t * pu32CC1,uint32_t * pu32CC2,uint32_t * pu32Rpvalue)462 int32_t UTCPD_GetRoleCtrl(int port, uint32_t* pu32DrpToggle, uint32_t* pu32CC1, uint32_t* pu32CC2, uint32_t* pu32Rpvalue)
463 {
464 int i32Reg;
465 int32_t rv;
466
467 rv = tcpc_addr_read32(port, NULL, TCPC_REG_ROLE_CTRL, &i32Reg);
468 *pu32DrpToggle = i32Reg & UTCPD_ROLCTL_DRP_Msk;
469 *pu32Rpvalue = i32Reg & UTCPD_ROLCTL_RPVALUE_Msk;
470 *pu32CC2 = i32Reg & UTCPD_ROLCTL_CC2_Msk;
471 *pu32CC1 = i32Reg & UTCPD_ROLCTL_CC1_Msk;
472 return rv;
473 }
474
475 /**
476 * @brief Set Type-C Port Control
477 *
478 * @param[in] port Specify UTCPD port
479 * @param[in] u32BistMode Enable or Disable BIST Mode
480 * - \ref UTCPD_TCPCCTL_BISTEN or 0
481 * @param[in] u32Orient Plug Oritentation
482 * - \ref UTCPD_TCPCCTL_ORIENT or 0
483 *
484 * @return 0: Successful, 1: Fail
485 *
486 * @details None
487 *
488 */
UTCPD_SetTypeCPortCtrl(int port,uint32_t u32BistMode,uint32_t u32Orient)489 int32_t UTCPD_SetTypeCPortCtrl(int port, uint32_t u32BistMode, uint32_t u32Orient)
490 {
491 uint8_t reg_set = u32BistMode | u32Orient;
492 return tcpc_addr_write16(port, NULL, TCPC_REG_TCPC_CTRL, reg_set);
493 }
494
495
496 /**
497 * @brief Get Role Control
498 *
499 * @param[in] port Specify UTCPD port
500 * @param[in] u32BistMode Enable or Disable BIST Mode
501 * - \ref UTCPD_TCPCCTL_BISTEN or 0
502 * @param[in] u32Orient Plug Oritentation
503 * - \ref UTCPD_TCPCCTL_ORIENT or 0
504 * @return 0: Successful, 1: Fail
505 *
506 * @details None
507 */
UTCPD_GetTypeCPortCtrl(int port,uint32_t * pu32BistMode,uint32_t * pu32Orient)508 int32_t UTCPD_GetTypeCPortCtrl(int port, uint32_t* pu32BistMode, uint32_t* pu32Orient)
509 {
510 int i32Reg;
511 int32_t rv;
512
513 rv = tcpc_addr_read32(port, NULL, TCPC_REG_TCPC_CTRL, &i32Reg);
514 *pu32BistMode = i32Reg & UTCPD_TCPCCTL_BISTEN;
515 *pu32Orient = i32Reg & UTCPD_TCPCCTL_ORIENT;
516 return rv;
517 }
518 /**
519 * @brief UTCPD Issue Command
520 *
521 * @param[in] port Specify UTCPD port
522 * @param[in] u8TcpcCtl Type-C Port Control
523 * - \ref UTCPD_CMD_DISABLE_VBUS_DETECT
524 * - \ref UTCPD_CMD_ENABLE_VBUS_DETECT
525 * - \ref UTCPD_CMD_DISABLE_SINK_VBUS
526 * - \ref UTCPD_CMD_SINK_VBUS
527 * - \ref UTCPD_CMD_SRC_VBUS_DEFAULT
528 * - \ref UTCPD_CMD_SRC_VBUS_NONDEFAULT
529 * - \ref UTCPD_CMD_LOOK4CONNECTION
530 * @return 0: Successful, 1: Fail
531 *
532 * @details The command can't be read back.
533 *
534 */
UTCPD_IsssueCmd(int port,uint32_t cmd)535 int32_t UTCPD_IsssueCmd(int port, uint32_t cmd)
536 {
537
538 return tcpc_addr_write16(port, NULL, TCPC_REG_COMMAND, cmd);
539 }
540
541
542
543 /**
544 * @brief Get CC Status
545 *
546 * @param[in] port Specify UTCPD port
547 * @param[in] pu32Look4Con. Under Look for connection or done
548 * - \ref UTCPD_LK4CONN_DONE
549 * - \ref UTCPD_UNDER_LK4CONN
550 * @param[in] pu32ConRlt. Connection result
551 * - \ref UTCPD_CONN_RESULT_RP
552 * - \ref UTCPD_CONN_RESULT_RD
553 * @param[in] pu32CC2Sts is CC2_State. CC2 connection state depends on connection result
554 * |\ref |\ref UTCPD_CCSTS_CC2STATE_SRC_OPEN | \ref UTCPD_CCSTS_CC2STATE_SNK_OPEN |
555 * |\ref |\ref UTCPD_CCSTS_CC2STATE_SRC_RA | \ref UTCPD_CCSTS_CC2STATE_SNK_DEF |
556 * |\ref |\ref UTCPD_CCSTS_CC2STATE_SRC_Rd | \ref UTCPD_CCSTS_CC2STATE_SNK_1P5A |
557 * |\ref |\ref x | \ref UTCPD_CCSTS_CC2STATE_SNK_3A |
558 * @param[in] pu32CC1Sts is CC1_State. CC1 connection state depends on connection result
559 * |\ref |\ref UTCPD_CCSTS_CC1STATE_SRC_OPEN | \ref UTCPD_CCSTS_CC1STATE_SNK_OPEN |
560 * |\ref |\ref UTCPD_CCSTS_CC1STATE_SRC_RA | \ref UTCPD_CCSTS_CC1STATE_SNK_DEF |
561 * |\ref |\ref UTCPD_CCSTS_CC1STATE_SRC_Rd | \ref UTCPD_CCSTS_CC1STATE_SNK_1P5A |
562 * |\ref |\ref x | \ref UTCPD_CCSTS_CC1STATE_SNK_3A |
563 * @return 0: Successful, 1: Fail
564 *
565 * @details None
566 */
UTCPD_GetCCSts(int port,uint32_t * pu32Look4Con,uint32_t * pu32ConRlt,uint32_t * pu32CC2Sts,uint32_t * pu32CC1Sts)567 int32_t UTCPD_GetCCSts(int port, uint32_t* pu32Look4Con, uint32_t* pu32ConRlt, uint32_t* pu32CC2Sts, uint32_t* pu32CC1Sts)
568 {
569 int i32Reg;
570 int32_t rv;
571
572 rv = tcpc_addr_read32(port, NULL, TCPC_REG_CC_STATUS, &i32Reg);
573 *pu32Look4Con = (i32Reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK);
574 *pu32ConRlt = (i32Reg & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK);
575 *pu32CC2Sts = (i32Reg & TCPC_REG_CC_STATUS_CC2_STATE_MASK);
576 *pu32CC1Sts = (i32Reg & TCPC_REG_CC_STATUS_CC1_STATE_MASK);
577 return rv;
578 }
579
580
581 /**
582 * @brief Get Power Status
583 *
584 * @param[in] port Specify UTCPD port
585 * @param[in] pu32VBUSDetEn. pu32VCONNPresent
586 * - \ref UTCPD_PWRSTS_VBPSDTEN
587 * - \ref 0
588 * @param[in] pu32VBUSPresent. VBUS Present or not
589 * - \ref UTCPD_PWRSTS_VBPS
590 * - \ref 0
591 * @param[in] pu32VCONNPresent VCONN Present or not
592 * - \ref UTCPD_PWRSTS_VCPS
593 * - \ref 0 |
594 * @return 0: Successful, 1: Fail
595 *
596 * @details None
597 */
UTCPD_GetPwrSts(int port,uint32_t * pu32VBUSDetEn,uint32_t * pu32VBUSPresent,uint32_t * pu32VCONNPresent,uint32_t * pu32SnkVBUS)598 int32_t UTCPD_GetPwrSts(int port, uint32_t* pu32VBUSDetEn, uint32_t* pu32VBUSPresent, uint32_t* pu32VCONNPresent, uint32_t* pu32SnkVBUS)
599 {
600 int i32Reg;
601 int32_t rv;
602
603 rv = tcpc_addr_read32(port, NULL, TCPC_REG_POWER_STATUS, &i32Reg);
604 *pu32VBUSDetEn = i32Reg & UTCPD_PWRSTS_VBPSDTEN_Msk;
605 *pu32VBUSPresent = i32Reg & UTCPD_PWRSTS_VBPS_Msk;
606 *pu32VCONNPresent = i32Reg & UTCPD_PWRSTS_VCPS_Msk;
607 *pu32SnkVBUS = i32Reg & UTCPD_PWRSTS_SKVB_Msk;
608 return rv;
609 }
610
611 /**
612 * @brief Get Power Status Extention
613 *
614 * @param[in] port Specify UTCPD port
615 * @param[in] pu32DbgAccessory. Debug Accessory Mode
616 * - \ref != 0 Debug Accessory Mode
617 * - \ref 0
618 * @param[in] pu32SrcNonDefVBUS. Source Non-Default VBUS
619 * - \ref != 0 Source Non-Default VBUS
620 * - \ref 0
621 * @param[in] pu32SrcDefVBUS Source Default VBUS
622 * - \ref != 0 Source Default VBUS
623 * - \ref 0
624 * @return 0: Successful, 1: Fail
625 *
626 * @details None
627 */
UTCPD_GetPwrStsExt(int port,uint32_t * pu32DbgAccessory,uint32_t * pu32SrcNonDefVBUS,uint32_t * pu32SrcDefVBUS)628 int32_t UTCPD_GetPwrStsExt(int port, uint32_t* pu32DbgAccessory, uint32_t* pu32SrcNonDefVBUS, uint32_t* pu32SrcDefVBUS)
629 {
630 int i32Reg;
631 int32_t rv;
632
633 rv = tcpc_addr_read32(port, NULL, TCPC_REG_POWER_STATUS, &i32Reg);
634 *pu32DbgAccessory = i32Reg & UTCPD_PWRSTS_DACON_Msk;
635 *pu32SrcNonDefVBUS = i32Reg & UTCPD_PWRSTS_SRHV_Msk;
636 *pu32SrcDefVBUS = i32Reg & UTCPD_PWRSTS_SRVB_Msk;
637 return rv;
638 }
639
640 /**
641 * @brief Get Power Status
642 *
643 * @param[in] port Specify UTCPD port
644 * @param[in] pu32VBUSOverVolt. VBUS Over Voltage Fault
645 * - \ref 1
646 * - \ref 0
647 * @param[in] pu32SrcNonDefVBUS. VCONN Over Current Fault
648 * - \ref 1
649 * - \ref 0
650 * @param[in] pu32SrcDefVBUS I2C Interface Error
651 * - \ref 1
652 * - \ref 0
653 * @return 0: Successful, 1: Fail
654 *
655 * @details None
656 */
UTCPD_GetFaultSts(int port,uint32_t * pu32VBUSOverCurr,uint32_t * pu32VBUSOverVolt,uint32_t * pu32VCONNOverCurr,uint32_t * pu32I2CInfErr)657 int32_t UTCPD_GetFaultSts(int port, uint32_t* pu32VBUSOverCurr, uint32_t* pu32VBUSOverVolt, uint32_t* pu32VCONNOverCurr, uint32_t* pu32I2CInfErr)
658 {
659 int i32Reg;
660 int32_t rv;
661
662 rv = tcpc_addr_read32(port, NULL, TCPC_REG_FAULT_STATUS, &i32Reg);
663 *pu32VBUSOverCurr = i32Reg & UTCPD_FUTSTS_VBOCFUT_Msk;
664 *pu32VBUSOverVolt = i32Reg & UTCPD_FUTSTS_VBOVFUT_Msk;
665 *pu32VCONNOverCurr = i32Reg & UTCPD_FUTSTS_VCOCFUT_Msk;
666 *pu32I2CInfErr = 0; /* M2L31 didn't support I2C */
667 return rv;
668 }
669
670
671 /**
672 * @brief Get Fault Status Extention
673 *
674 * @param[in] port Specify UTCPD port
675 * @param[in] pu32ForceOffFat. Force Off VBUS Fault
676 * - \ref 1
677 * - \ref 0
678 * @param[in] pu32AutoDiscFat. Auto Discharge Fault
679 * - \ref 1
680 * - \ref 0
681 * @param[in] pu32ForceDiscFat Foece Discharge Fault
682 * - \ref 1
683 * - \ref 0 |
684 * @return 0: Successful, 1: Fail
685 *
686 * @details None
687 */
UTCPD_GetFaultStsExt(int port,uint32_t * pu32ForceOffFat,uint32_t * pu32AutoDiscFat,uint32_t * pu32ForceDiscFat)688 int32_t UTCPD_GetFaultStsExt(int port, uint32_t* pu32ForceOffFat, uint32_t* pu32AutoDiscFat, uint32_t* pu32ForceDiscFat)
689 {
690 int i32Reg;
691 int32_t rv;
692
693 rv = tcpc_addr_read32(port, NULL, TCPC_REG_FAULT_STATUS, &i32Reg);
694 *pu32ForceOffFat = i32Reg & UTCPD_FUTSTS_FOFFVB_Msk;
695 *pu32AutoDiscFat = i32Reg & UTCPD_FUTSTS_ADGFAL_Msk;
696 *pu32ForceDiscFat = i32Reg & UTCPD_FUTSTS_FDGFAL_Msk;
697 return rv;
698 }
699
700
701 /**
702 * @brief Set Message Header Information
703 *
704 * @param[in] port Specify UTCPD port
705 * @param[in] u32DataRole Data Role
706 * - \ref UTCPD_MHINFO_DROLE_UFP
707 * - \ref UTCPD_MHINFO_DROLE_DFP
708 * @param[in] u32Revision PD Revision
709 * - \ref UTCPD_MHINFO_PDREV_10
710 * - \ref UTCPD_MHINFO_PDREV_20
711 * - \ref UTCPD_MHINFO_PDREV_30
712 * - \ref UTCPD_MHINFO_PDREV_31
713 * @param[in] u32PwrRole Power Role
714 * - \ref UTCPD_MHINFO_PROLE_SNK
715 * - \ref UTCPD_MHINFO_PROLE_SRC
716 * @return 0: Successful, 1: Fail
717 *
718 * @details None
719 *
720 */
UTCPD_SetMsgHeaderInfo(int port,uint32_t u32DataRole,uint32_t u32Revision,uint32_t u32PwrRole)721 int32_t UTCPD_SetMsgHeaderInfo(int port, uint32_t u32DataRole, uint32_t u32Revision, uint32_t u32PwrRole)
722 {
723 uint8_t reg_set = u32DataRole | u32Revision | u32PwrRole;
724 return tcpc_addr_write16(port, NULL, TCPC_REG_MSG_HDR_INFO, reg_set);
725 }
726
727 /**
728 * @brief Set Message Header Information
729 *
730 * @param[in] port Specify UTCPD port
731 * @param[in] u32RegData Combination from following set
732 * - \ref UTCPD_RDET_SOPEN
733 * - \ref UTCPD_RDET_SOPPEN
734 * - \ref UTCPD_RDET_SOPPPEN
735 * - \ref UTCPD_RDET_SDBGPEN
736 * - \ref UTCPD_RDET_SDBGPEN
737 * - \ref UTCPD_RDET_SDBGPPEN
738 * - \ref UTCPD_RDET_HRSTEN
739 * - \ref UTCPD_RDET_CABRSTEN
740 * @return 0: Successful, 1: Fail
741 *
742 * @details None
743 *
744 */
UTCPD_SetRecDetect(int port,uint32_t u32RegData)745 int32_t UTCPD_SetRecDetect(int port, uint32_t u32RegData)
746 {
747 uint8_t reg_set = u32RegData;
748 return tcpc_addr_write16(port, NULL, TCPC_REG_RX_DETECT, reg_set);
749 }
750
751 /**
752 * @brief Set VBUS Alarm High and Alarm Low Voltage
753 *
754 * @param[in] port Specify UTCPD port
755 * @param[in] u32AlarmH VBUS Alarm High Threshold Voltage
756 * @param[in] u32AlarmL VBUS Alarm Low Threshold Voltage
757 * @return 0: Successful, 1: Fail
758 *
759 * @details None
760 *
761 */
UTCPD_SetVBUSAlarm(int port,uint32_t u32AlarmH,uint32_t u32AlarmL)762 int32_t UTCPD_SetVBUSAlarm(int port, uint32_t u32AlarmH, uint32_t u32AlarmL)
763 {
764 uint8_t u8TxBuf[4];
765 u8TxBuf[0] = u32AlarmH;
766 u8TxBuf[1] = u32AlarmH >> 8;
767 u8TxBuf[2] = u32AlarmL;
768 u8TxBuf[3] = u32AlarmL >> 8;
769 return tcpc_write_block(port, TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG, u8TxBuf, 4);
770 }
771
772 /**
773 * @brief Set Sink Disconnection Voltage
774 *
775 * @param[in] port Specify UTCPD port
776 * @param[in] u32SnkDiscVolt Sink Disconnection Threshold Voltae
777 * @return 0: Successful, 1: Fail
778 *
779 * @details Sink Will start the VBUS auto discharge if VBUS voltage less Sink Disconnection Threshold Level
780 * POWER_CONTROL[Auto Discharge] should set to 1.
781 *
782 */
UTCPD_SetSnkDisconnect(int port,uint32_t u32SnkDiscVolt)783 int32_t UTCPD_SetSnkDisconnect(int port, uint32_t u32SnkDiscVolt)
784 {
785 return tcpc_addr_write16(port, NULL, TCPC_REG_VBUS_SINK_DISCONNECT_THRESH, u32SnkDiscVolt);
786 }
787
788 /**
789 * @brief Set VBUS Stop Discharge Threshold Voltage
790 *
791 * @param[in] port Specify UTCPD port
792 * @param[in] u32StopDischgVolt VBUS Stop Discharge Threshold Voltage
793 * @return 0: Successful, 1: Fail
794 *
795 * @details SRC/SNK Will stop VBUS force discharge if VBUS voltage less VBUS Stop Discharge Threshold Level
796 * POWER_CONTROL[Force Discharge] should set to 1.
797 *
798 */
UTCPD_SetStopDischargeVolt(int port,uint32_t u32StopDischgVolt)799 int32_t UTCPD_SetStopDischargeVolt(int port, uint32_t u32StopDischgVolt)
800 {
801 return tcpc_addr_write16(port, NULL, TCPC_REG_VBUS_STOP_DISCHARGE_THRESH, u32StopDischgVolt);
802 }
803
804
805 /*
806 The CC ststus interupt won't be issued if Enable_VCONN_SRC_CC with wrong VCONN source CC pin
807 */
808 /**
809 * @brief Disable VCONN Power Source to CCx pin
810 *
811 * @param[in] port Specify UTCPD port
812 * @return None
813 *
814 * @details None
815 *
816 */
UTCPD_vconn_disable_src_cc(int port)817 void UTCPD_vconn_disable_src_cc(int port)
818 {
819 tcpc_update16(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_ENABLE_VCONN, MASK_CLR);
820 }
821 /**
822 * @brief Enable VCONN Power Source to CCx pin
823 *
824 * @param[in] port Specify UTCPD port
825 * @return None
826 *
827 * @details None
828 *
829 */
UTCPD_vconn_enable_src_cc(int port)830 void UTCPD_vconn_enable_src_cc(int port)
831 {
832 tcpc_update16(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_ENABLE_VCONN, MASK_SET);
833 }
834
835 /**
836 * @brief VCONN Power Source to CC2 pin
837 *
838 * @param[in] port Specify UTCPD port
839 * @return None
840 *
841 * @details Enable VCONN Source CC2, Communication channel through CC1
842 *
843 */
UTCPD_vconn_enable_from_cc2(int port)844 void UTCPD_vconn_enable_from_cc2(int port)
845 {
846 tcpc_update16(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION, MASK_CLR);
847 }
848
849 /**
850 * @brief VCONN Power Source to CC1 pin
851 *
852 * @param[in] port Specify UTCPD port
853 * @return None
854 *
855 * @details Enable VCONN Source CC2, Communication channel through CC1
856 *
857 */
UTCPD_vconn_enable_from_cc1(int port)858 void UTCPD_vconn_enable_from_cc1(int port)
859 {
860 tcpc_update16(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION, MASK_SET);
861 }
862
863 /**
864 * @brief Set VCONN Active Polarity Low
865 *
866 * @param[in] port Specify UTCPD port
867 * @return None
868 *
869 * @details It depends on the external circuit
870 *
871 */
UTCPD_vconn_polarity_active_low(int port)872 void UTCPD_vconn_polarity_active_low(int port)
873 {
874 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_VCEN, MASK_CLR);
875 }
876
877 /**
878 * @brief Set VCONN Active Polarity High
879 *
880 * @param[in] port Specify UTCPD port
881 * @return None
882 *
883 * @details It depends on the external circuit
884 *
885 */
UTCPD_vconn_polarity_active_high(int port)886 void UTCPD_vconn_polarity_active_high(int port)
887 {/* Set VCONN Polarity Active Low due to CC1VCENS and CC2VCENS default high */
888 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_VCEN, MASK_SET);
889 }
890
891 /**
892 * @brief Disable VCONN OC Fault
893 *
894 * @param[in] port Specify UTCPD port
895 * @return None
896 *
897 * @details
898 *
899 */
UTCPD_vconn_disable_oc_fault(int port)900 void UTCPD_vconn_disable_oc_fault(int port)
901 {
902 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS, MASK_SET);
903 }
904
905 /**
906 * @brief Enable VCONN OC Fault
907 *
908 * @param[in] port Specify UTCPD port
909 * @return None
910 *
911 * @details
912 *
913 */
UTCPD_vconn_enable_oc_fault(int port)914 void UTCPD_vconn_enable_oc_fault(int port)
915 {
916 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS, MASK_CLR);
917 }
918
919 /**
920 * @brief Specified VCONN Enable Multiplex Path
921 *
922 * @param[in] port Specify UTCPD port
923 * @param[in] cc1vcensel It should be 1 default
924 * @param[in] cc2vcensel It should be 1 default
925 *
926 * @details
927 *
928 */
UTCPD_vconn_mux_selection(int port,uint32_t cc1vcensel,uint32_t cc2vcensel)929 void UTCPD_vconn_mux_selection(int port, uint32_t cc1vcensel, uint32_t cc2vcensel)
930 {
931 int data;
932 tcpc_addr_read16(port, NULL, UTCPD_MUXSEL, &data);
933 data = (data & ~(CC2VCENS | CC1VCENS)) | ((cc1vcensel<<24) | (cc2vcensel<<28));
934 tcpc_addr_write32(port, NULL, UTCPD_MUXSEL, (unsigned int)data);
935 }
936
937 /**
938 * @brief Configure VCONN OC source detection
939 *
940 * @param[in] port Specify UTCPD port
941 * @param[in] u32Src Specify VCONN OC Source Detection
942 * - \ref UTCPD_VCONN_OC_EINT0
943 * - \ref UTCPD_VCONN_OC_EINT1
944 * - \ref UTCPD_VCONN_OC_EINT2
945 * - \ref UTCPD_VCONN_OC_EINT3
946 * - \ref UTCPD_VCONN_ADC_CMP0
947 * - \ref UTCPD_VCONN_ACMP0
948 * - \ref UTCPD_VCONN_ACMP1
949 * - \ref UTCPD_VCONN_ACMP2
950 * @details
951 *
952 */
UTCPD_vconn_configure_oc_detection_soruce(int port,uint32_t u32Src)953 void UTCPD_vconn_configure_oc_detection_soruce(int port, uint32_t u32Src)
954 {
955 int data;
956 tcpc_addr_read16(port, NULL, UTCPD_MUXSEL, &data);
957 data = (data & ~VCOCS) | (u32Src<<4);
958 tcpc_addr_write16(port, NULL, UTCPD_MUXSEL, data);
959 }
960
961 /* ============ VBUS SRCEN Polarity ==========*/
UTCPD_vbus_srcen_polarity_active_low(int port)962 void UTCPD_vbus_srcen_polarity_active_low(int port)
963 {/* Set VBUS SRCEN Polarity active Low */
964 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_SRCEN, MASK_CLR);
965 }
UTCPD_vbus_srcen_polarity_active_high(int port)966 void UTCPD_vbus_srcen_polarity_active_high(int port)
967 {/* Set VBUS SRCEN Polarity Active high */
968 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_SRCEN, MASK_SET);
969 }
970 /* ============ VBUS SNKEN Polarity ==========*/
UTCPD_vbus_snken_polarity_active_low(int port)971 void UTCPD_vbus_snken_polarity_active_low(int port)
972 {/* Set VBUS SNKEN Polarity active Low */
973 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_SNKEN, MASK_CLR);
974 }
UTCPD_vbus_snken_polarity_active_high(int port)975 void UTCPD_vbus_snken_polarity_active_high(int port)
976 {/* Set VBUS SNKEN Polarity Active high */
977 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_SNKEN, MASK_SET);
978 }
979
UTCPD_vbus_disable_oc_fault(int port)980 void UTCPD_vbus_disable_oc_fault(int port)
981 {
982 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS, MASK_SET);
983 }
UTCPD_vbus_enable_oc_fault(int port)984 void UTCPD_vbus_enable_oc_fault(int port)
985 {
986 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS, MASK_CLR);
987 }
988
UTCPD_vbus_discharge_polarity_active_low(int port)989 void UTCPD_vbus_discharge_polarity_active_low(int port)
990 {/* Set VBUS discharge Polarity Active low */
991 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_VBDCHG, MASK_CLR);
992 }
UTCPD_vbus_discharge_polarity_active_high(int port)993 void UTCPD_vbus_discharge_polarity_active_high(int port)
994 {/* Set VBUS discharge Polarity Active high */
995 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_VBDCHG, MASK_SET);
996 }
997
998 /**
999 * @brief Configure VBUS OC source detection
1000 *
1001 * @param[in] port Specify UTCPD port
1002 * @param[in] u32Src Specify VBUS OC Source Detection
1003 * - \ref UTCPD_VBUS_OC_EINT0
1004 * - \ref UTCPD_VBUS_OC_EINT1
1005 * - \ref UTCPD_VBUS_OC_EINT2
1006 * - \ref UTCPD_VBUS_OC_EINT3
1007 * - \ref UTCPD_VBUS_ADC_CMP0
1008 * - \ref UTCPD_VBUS_ACMP0
1009 * - \ref UTCPD_VBUS_ACMP1
1010 * - \ref UTCPD_VBUS_ACMP2
1011 * @details
1012 *
1013 */
UTCPD_vbus_configure_oc_soruce(int port,uint32_t u32Src)1014 void UTCPD_vbus_configure_oc_soruce(int port, uint32_t u32Src)
1015 {
1016 int data;
1017 tcpc_addr_read16(port, NULL, UTCPD_MUXSEL, &data);
1018 data = (data & ~VBOCS) | (u32Src<<0);
1019 tcpc_addr_write16(port, NULL, UTCPD_MUXSEL, data);
1020 }
1021
1022 /* VBUS ovp fault */
UTCPD_vbus_disable_ov_fault(int port)1023 void UTCPD_vbus_disable_ov_fault(int port)
1024 {
1025 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, MASK_SET);
1026 }
UTCPD_vbus_enable_ov_fault(int port)1027 void UTCPD_vbus_enable_ov_fault(int port)
1028 {
1029 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, MASK_CLR);
1030 }
1031
1032 /* VBUS force off fault */
UTCPD_vbus_disable_forceoff_fault(int port)1033 void UTCPD_vbus_disable_forceoff_fault(int port)
1034 {
1035 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF_DIS, MASK_SET);
1036 }
UTCPD_vbus_enable_forceoff_fault(int port)1037 void UTCPD_vbus_enable_forceoff_fault(int port)
1038 {
1039 tcpc_update16(port, TCPC_REG_FAULT_CTRL, TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF_DIS, MASK_CLR);
1040 }
1041
1042
UTCPD_vbus_is_source(int port)1043 uint32_t UTCPD_vbus_is_source(int port)
1044 {
1045 int data;
1046 tcpc_addr_read16(port, NULL, TCPC_REG_POWER_STATUS, &data);
1047 if (data & TCPC_REG_POWER_STATUS_SOURCING_VBUS)
1048 return 1;
1049 else
1050 return 0;
1051 }
1052
UTCPD_vbus_is_sink(int port)1053 uint32_t UTCPD_vbus_is_sink(int port)
1054 {
1055 int data;
1056 tcpc_addr_read16(port, NULL, TCPC_REG_POWER_STATUS, &data);
1057 if (data & TCPC_REG_POWER_STATUS_SINKING_VBUS)
1058 return 1;
1059 else
1060 return 0;
1061 }
1062
UTCPD_vbus_is_source_hv(int port)1063 uint32_t UTCPD_vbus_is_source_hv(int port)
1064 {
1065 int data;
1066 tcpc_addr_read16(port, NULL, TCPC_REG_POWER_STATUS, &data);
1067 if (data & TCPC_REG_POWER_STATUS_SOURCING_HIGH_VBUS)
1068 return 1;
1069 else
1070 return 0;
1071 }
1072
1073 //=================================== for VBUS and VCONN
UTCPD_power_enable_monitor(int port)1074 void UTCPD_power_enable_monitor(int port)
1075 {/* 0 enable monitor */
1076 tcpc_update16(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS, MASK_CLR);
1077 }
1078
UTCPD_power_disable_monitor(int port)1079 void UTCPD_power_disable_monitor(int port)
1080 {/* 1 disable monitor */
1081 tcpc_update16(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS, MASK_SET);
1082 }
1083
1084 /* VBUS enable auto discharge */
UTCPD_power_disable_auto_discharge(int port)1085 void UTCPD_power_disable_auto_discharge(int port)
1086 {/* Disable Auto Discharge = 0 */
1087 tcpc_update16(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT, MASK_CLR);
1088 }
UTCPD_power_enable_auto_discharge(int port)1089 void UTCPD_power_enable_auto_discharge(int port)
1090 {/* Enable Auto Discharge = 0 */
1091 tcpc_update16(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT, MASK_SET);
1092 }
1093
UTCPD_frs_tx_polarity_active_low(int port)1094 void UTCPD_frs_tx_polarity_active_low(int port)
1095 {/* Set FRS Polarity Active low */
1096 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_FRSTX, MASK_CLR);
1097 }
UTCPD_frs_tx_polarity_active_high(int port)1098 void UTCPD_frs_tx_polarity_active_high(int port)
1099 {/* Set FRS Polarity Active high */
1100 tcpc_update16(port, TCPC_REG_PINPL, TCPC_REG_PINPL_FRSTX, MASK_SET);
1101 }
1102
UTCPD_frs_mux_selection(int port,uint32_t cc1frssel,uint32_t cc2frssel)1103 void UTCPD_frs_mux_selection(int port, uint32_t cc1frssel, uint32_t cc2frssel)
1104 {
1105 int data;
1106 tcpc_addr_read16(port, NULL, UTCPD_MUXSEL, &data);
1107 data = (data & ~(CC2FRSS|CC1FRSS)) | ((cc1frssel<<25) | (cc2frssel<<29));
1108 tcpc_addr_write32(port, NULL, UTCPD_MUXSEL, data);
1109 }
1110
1111 /**
1112 * @brief Enable specify UTCPD Controller and set Clock Divider
1113 *
1114 * @param[in] UTCPD Specify UTCPD port
1115 * @return Always 0
1116 *
1117 * @details The function needs to enable the I2C Controller and set proper clock divider first.
1118 *
1119 */
UTCPD_Open(int port)1120 uint32_t UTCPD_Open(int port)
1121 {
1122 /* Enable Clock */
1123 /* Set Clock Divider */
1124
1125 /* Reset UTCPD */
1126 SYS->IPRST3 |= SYS_IPRST3_UTCPD0RST_Msk;
1127 SYS->IPRST3 &= ~SYS_IPRST3_UTCPD0RST_Msk;
1128
1129 /* Enable PHY */
1130 SYS->UTCPDCTL = SYS->UTCPDCTL | 0x02;
1131 tcpc_addr_write16(port, NULL, UTCPD_PHYCTL, 0x03);
1132
1133
1134
1135 UTCPD_frs_mux_selection(port, 1, 1);
1136 UTCPD_vconn_mux_selection(port, 1, 1);
1137
1138 return 0;
1139 }
1140
1141
1142 /*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
1143
1144 /*@}*/ /* end of group I2C_Driver */
1145
1146 /*@}*/ /* end of group Standard_Driver */
1147
1148 #ifdef __cplusplus
1149 }
1150 #endif
1151
1152 /*** (C) COPYRIGHT 2023 Nuvoton Technology Corp. ***/
1153
