1 /**************************************************************************//** 2 * @file utcpd_reg.h 3 * @version V1.00 4 * @brief UTCPD register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 10 /** @addtogroup REGISTER Control Register 11 12 @{ 13 14 */ 15 16 17 /*---------------------- USB Type C Power Delivery Controller -------------------------*/ 18 /** 19 @addtogroup UTCPD USB Type C Power Delivery Controller(UTCPD) 20 Memory Mapped Structure for UTCPD Controller 21 @{ */ 22 23 typedef struct 24 { 25 26 27 /** 28 * @var UTCPD_T::VID 29 * Offset: 0x00 UTCPD Vendor ID Register 30 * --------------------------------------------------------------------------------------------------- 31 * |Bits |Field |Descriptions 32 * | :----: | :----: | :---- | 33 * |[15:0] |VID |UTCPD Vendor ID 34 * | | |Vendor identifier is used to identify the TCPC vendor, the VID is a unique 16-bit unsigned integer assigned by USB-IF to the Vendor 35 * @var UTCPD_T::PID 36 * Offset: 0x04 UTCPD Product ID Register 37 * --------------------------------------------------------------------------------------------------- 38 * |Bits |Field |Descriptions 39 * | :----: | :----: | :---- | 40 * |[15:0] |PID |UTCPD Product ID 41 * | | |USB Product ID is used to identify the product 42 * @var UTCPD_T::DID 43 * Offset: 0x08 UTCPD Device ID Register 44 * --------------------------------------------------------------------------------------------------- 45 * |Bits |Field |Descriptions 46 * | :----: | :----: | :---- | 47 * |[15:0] |DID |UTCPD Device ID 48 * | | |USB Device ID is used to identify the release version of the product 49 * @var UTCPD_T::TCREV 50 * Offset: 0x0C UTCPD USB Type C Revision Register 51 * --------------------------------------------------------------------------------------------------- 52 * |Bits |Field |Descriptions 53 * | :----: | :----: | :---- | 54 * |[7:0] |TCREV |UTCPD USB Type C Revision 55 * | | |USB Type-C Cable and Connector Specification Revision 1.3 56 * @var UTCPD_T::PDREV 57 * Offset: 0x10 UTCPD USB PD Revision Register 58 * --------------------------------------------------------------------------------------------------- 59 * |Bits |Field |Descriptions 60 * | :----: | :----: | :---- | 61 * |[7:0] |PDVER |UTCPD USB PD Vision 62 * | | |USB Power Delivery Specification Version 1.1 63 * |[15:8] |PDREV |UTCPD USB PD Revision 64 * | | |USB Power Delivery Specification revision 3.1 65 * @var UTCPD_T::IS 66 * Offset: 0x14 UTCPD Interrupt Status Register 67 * --------------------------------------------------------------------------------------------------- 68 * |Bits |Field |Descriptions 69 * | :----: | :----: | :---- | 70 * |[0] |CCSCHIS |CC Status Changed 71 * | | |0 = CC status not change. 72 * | | |1= CC status changed. 73 * | | |Note: It is cleared by software writing 1 into this bit. 74 * |[1] |PWRSCHIS |Power Status Changed 75 * | | |0 = Power status not change. 76 * | | |1 = Power status changed. 77 * | | |Note: It is cleared by software writing 1 into this bit. 78 * |[2] |RXSOPIS |Received SOP Message 79 * | | |0 = No SOP message Received. 80 * | | |1 = Received SOP message 81 * | | |UTCPD_RXBCNT being set to 0 does not set this bit. 82 * | | |Note: It is cleared by software writing 1 into this bit. 83 * |[3] |RXHRSTIS |Received Hard Reset 84 * | | |0 = No Hard reset Received. 85 * | | |1 = Received Hard reset. 86 * | | |Note: It is cleared by software writing 1 into this bit. 87 * |[4] |TXFALIS |Transmit SOP Fail 88 * | | |0 = No Transmit SOP fail. 89 * | | |1 = SOP* message transmission not successful, no GoodCRC response received on SOP* message transmission 90 * | | |Transmit SOP* message buffer registers are empty. 91 * | | |Note: It is cleared by software writing 1 into this bit. 92 * |[5] |TXDCUDIS |Transmit SOP* Message Discarded 93 * | | |0 = No TX SOP discarded. 94 * | | |1 = Reset or SOP* message transmission not sent due to incoming receive message 95 * | | |Transmit SOP* message buffer registers are empty. 96 * | | |Note: It is cleared by software writing 1 into this bit. 97 * |[6] |TXOKIS |Transmit SOP* Message Successful 98 * | | |0 = No TX SOP* transmit. 99 * | | |1 = Reset or SOP* message transmission successful 100 * | | |GoodCRC response received on SOP* message transmission 101 * | | |Transmit SOP* message buffer registers are empty. 102 * | | |Note: It is cleared by software writing 1 into this bit. 103 * |[7] |VBAMHIS |VBUS Voltage Alarm High 104 * | | |0 = No high voltage alarm has occurred. 105 * | | |1= A high voltage alarm has occurred. 106 * | | |This bit will be set high when DSVBAM (UTCPD_PWRCTL[5]) is low and VBUS voltage is higher than VBAMH (UTCPD_VBAMH[9:0]). 107 * | | |Note: It is cleared by software writing 1 into this bit. 108 * |[8] |VBAMLIS |VBUS Voltage Alarm Low 109 * | | |0 = No Low voltage alarm has occurred. 110 * | | |1= A Low voltage alarm has occurred. 111 * | | |This bit will be set high when DSVBAM (UTCPD_PWRCTL[5]]) is low and VBUS voltage is lower than VBAML (UTCPD_VBAML[9:0]). 112 * | | |Note: It is cleared by software writing 1 into this bit. 113 * |[9] |FUTIS |Fault Occur 114 * | | |0 = No fault occurs. 115 * | | |1= A Fault has occurred. Read the FUT_STS register. 116 * | | |Note: It is cleared by software writing 1 into this bit. 117 * |[10] |RXOFIS |Rx Buffer Overflow 118 * | | |0 = RX buffer is functioning properly. 119 * | | |1 = RX buffer has overflowed. 120 * | | |Writing 1 to this register acknowledges the overflow 121 * | | |The overflow is cleared by writing 1 to RXSOPIS (UTCPD_IS[2]) 122 * |[11] |SKDCDTIS |VBUS Sink Disconnect Detected 123 * | | |0 = No disconnect detected. 124 * | | |1 = A VBUS Sink disconnect threshold crossing has been detected. 125 * | | |This bit will be set when VBMONI (UTCPD_PWRCTL[6]) is enabled and VBUS voltage drop lower than SKVBDCTH (UTCPD_SKVBDCTH[9:0]). 126 * | | |Note: It is cleared by software writing 1 into this bit. 127 * |[15] |VNDIS |Vendor Define Event Detected 128 * | | |0 = No vendor defined interrupt status has been detected. 129 * | | |1 = A vendor defined interrupt status has been detected 130 * | | |Refer the vender defined interrupt status register. 131 * | | |Note: It is cleared by software writing 1 into this bit. 132 * @var UTCPD_T::IE 133 * Offset: 0x18 UTCPD Interrupt Enable Register 134 * --------------------------------------------------------------------------------------------------- 135 * |Bits |Field |Descriptions 136 * | :----: | :----: | :---- | 137 * |[0] |CCSCHIE |CC Status Changed Interrupt Enable 138 * | | |0 = Disabled. 139 * | | |1 = Enabled. 140 * |[1] |PWRSCHIE |Power Status Changed Interrupt Enable 141 * | | |0 = Disabled. 142 * | | |1 = Enabled. 143 * |[2] |RXSOPIE |Received SOP Message Interrupt Enable 144 * | | |0 = Disabled. 145 * | | |1 = Enabled. 146 * |[3] |RXHRSTIE |Received Hard Reset Interrupt Enable 147 * | | |0 = Disabled. 148 * | | |1 = Enabled. 149 * |[4] |TXFAILIE |Transmit SOP Fail Interrupt Enable 150 * | | |0 = Disabled. 151 * | | |1 = Enabled. 152 * |[5] |TXDCUDIE |Transmit SOP* Message Discarded Interrupt Enable 153 * | | |0 = Disabled. 154 * | | |1 = Enabled. 155 * |[6] |TXOKIE |Transmit SOP* Message Successful Interrupt Enable 156 * | | |0 = Disabled. 157 * | | |1 = Enabled. 158 * |[7] |VBAMHIE |VBUS Voltage Alarm High Interrupt Enable 159 * | | |0 = Disabled. 160 * | | |1 = Enabled. 161 * |[8] |VBAMLIE |VBUS Voltage Alarm Low Interrupt Enable 162 * | | |0 = Disabled. 163 * | | |1 = Enabled. 164 * |[9] |FUTIE |Fault Occur Interrupt Enable 165 * | | |0 = Disabled. 166 * | | |1 = Enabled. 167 * |[10] |RXOFIE |Rx Buffer Overflow Interrupt Enable 168 * | | |0 = Disabled. 169 * | | |1 = Enabled. 170 * |[11] |SKDCDTIE |VBUS Sink Disconnect Detected Interrupt Enable 171 * | | |0 = Disabled. 172 * | | |1 = Enabled. 173 * |[15] |VNDIE |Vendor Define Event Detected Interrupt Enable 174 * | | |0 = Disabled. 175 * | | |1 = Enabled. 176 * @var UTCPD_T::PWRSTSIE 177 * Offset: 0x1C UTCPD Power Status Interrupt Enable Register 178 * --------------------------------------------------------------------------------------------------- 179 * |Bits |Field |Descriptions 180 * | :----: | :----: | :---- | 181 * |[0] |SKVBIE |Sinking VBUS Status Interrupt Enable 182 * | | |0 = Disabled. 183 * | | |1 = Enabled. 184 * |[1] |VCPSIE |VCONN Present Status Interrupt Enable 185 * | | |0 = Disabled. 186 * | | |1 = Enabled. 187 * |[2] |VBPSIE |VBUS Present Status Interrupt Enable 188 * | | |0 = Disabled. 189 * | | |1 = Enabled. 190 * |[3] |VBDTDGIE |VBUS Detection Status Change Interrupt Enable 191 * | | |0 = Disabled. 192 * | | |1 = Enabled. 193 * |[4] |SRVBIE |Sourcing VBUS Status Interrupt Enable 194 * | | |0 = Disabled. 195 * | | |1 = Enabled. 196 * |[5] |SRHVIE |Sourcing High Voltage Status Interrupt Enable 197 * | | |0 = Disabled. 198 * | | |1 = Enabled. 199 * |[7] |DACONIE |Debug Accessory Connected Status Interrupt Enable 200 * | | |0 = Disabled. 201 * | | |1 = Enabled. 202 * @var UTCPD_T::FUTSTSIE 203 * Offset: 0x20 UTCPD Fault Status Interrupt Enable Register 204 * --------------------------------------------------------------------------------------------------- 205 * |Bits |Field |Descriptions 206 * | :----: | :----: | :---- | 207 * |[1] |VCOCIE |VCONN OCP Fault Interrupt Enable 208 * | | |0 = Disabled. 209 * | | |1 = Enabled. 210 * |[2] |VBOVIE |Internal VBUS OVP Fault Interrupt Enable 211 * | | |0 = Disabled. 212 * | | |1 = Enabled. 213 * |[3] |VBOCIE |External VBUS OCP Fault Interrupt Enable 214 * | | |0 = Disabled. 215 * | | |1 = Enabled. 216 * |[4] |FDGFALIE |Force Discharge Failed Interrupt Enable 217 * | | |0 = Disabled. 218 * | | |1 = Enabled. 219 * |[5] |ADGFALIE |Auto Discharge Failed Interrupt Enable 220 * | | |0 = Disabled. 221 * | | |1 = Enabled. 222 * |[6] |FOFFVBIE |Force Off VBUS Interrupt Enable 223 * | | |0 = Disabled. 224 * | | |1 = Enabled. 225 * @var UTCPD_T::CTL 226 * Offset: 0x24 UTCPD Control Register 227 * --------------------------------------------------------------------------------------------------- 228 * |Bits |Field |Descriptions 229 * | :----: | :----: | :---- | 230 * |[0] |ORIENT |Plug Orientation 231 * | | |0 = When VCONN is enabled, apply it to the CC2 pin 232 * | | |Monitor the CC1 pin for BMC communications if PD messaging is enabled. 233 * | | |1 = When VCONN is enabled, apply it to the CC1 pin. Monitor the CC2 pin for BMC 234 * | | |communications if PD messaging is enabled. 235 * |[1] |BISTEN |BIST Test Mode 236 * | | |Setting this bit to 1 is intended to be used only when a USB compliance tester is using USB BIST Test Data to test the PHY layer of the UTCPD 237 * | | |The CPU should clear this bit when a detach is detected. 238 * | | |0 = Normal Operation. 239 * | | |1 = BIST Test Mode. 240 * @var UTCPD_T::PINPL 241 * Offset: 0x28 UTCPD Pin Polarity Control Register 242 * --------------------------------------------------------------------------------------------------- 243 * |Bits |Field |Descriptions 244 * | :----: | :----: | :---- | 245 * |[0] |VBSRENPL |VBUS Source Enable Polarity 246 * | | |0 = Low active. 247 * | | |1 = High active. 248 * |[1] |VBSKENPL |VBUS Sink Enable Polarity 249 * | | |0 = Low active. 250 * | | |1 = High active. 251 * |[2] |VBDGENPL |VBUS Discharge Enable Polarity 252 * | | |It is for Bleed Discharge Enable Polarity. 253 * | | |0 = Low active. 254 * | | |1 = High active. 255 * |[3] |TXFRSPL |Fast Role Swap TX Polarity 256 * | | |0 = Low active. 257 * | | |1 = High active. 258 * |[4] |FOFFVBPL |Force Off VBUS event Polarity 259 * | | |0 = Low active. 260 * | | |1 = High active. 261 * |[5] |VBOCPL |VBUS Overcurrent event Polarity 262 * | | |0 = Low active. 263 * | | |1 = High active. 264 * |[8] |VCENPL |VCONN Enable Polarity 265 * | | |0 = Low active. 266 * | | |1 = High active. 267 * |[9] |VCDGENPL |VCONN Discharge Enable Polarity 268 * | | |0 = Low active. 269 * | | |1 = High active. 270 * |[10] |VCOCPL |VCONN Overcurrent event Polarity 271 * | | |0 = Low active. 272 * | | |1 = High active. 273 * @var UTCPD_T::ROLCTL 274 * Offset: 0x2C UTCPD Role Control Register 275 * --------------------------------------------------------------------------------------------------- 276 * |Bits |Field |Descriptions 277 * | :----: | :----: | :---- | 278 * |[1:0] |CC1 |CC1 279 * | | |00 = Reserved. 280 * | | |01b = Rp (Use Rp definition in RPVALUE). 281 * | | |10 = Rd. 282 * | | |11 = Open (Disconnect or don't care). 283 * |[3:2] |CC2 |CC2 284 * | | |00 = Reserved. 285 * | | |01 = Rp (Use Rp definition in RPVALUE). 286 * | | |10 = Rd. 287 * | | |11 = Open (Disconnect or don't care). 288 * |[5:4] |RPVALUE |Rp Value 289 * | | |00 = Rp default. 290 * | | |01 = Rp 1.5A. 291 * | | |10 = Rp 3.0A. 292 * | | |11 = Reserved. 293 * |[6] |DRP |DRP 294 * | | |0 = No DRP. 295 * | | |1 = DRP. 296 * | | |The UTCPD toggles CC1 & CC2 after receiving LK4CON (UTCPD_CMD[5]) and until a connection is detected 297 * | | |Upon connection, the UTCPD shall resolve to either an Rp or Rd and report the CC1/CC2 State in the CC_STS register 298 * @var UTCPD_T::FUTCTL 299 * Offset: 0x30 UTCPD Fault Control Register 300 * --------------------------------------------------------------------------------------------------- 301 * |Bits |Field |Descriptions 302 * | :----: | :----: | :---- | 303 * |[0] |VCOCDTDS |External VCONN Overcurrent Fault Detect Disable 304 * | | |0 = External VCONN OCP circuit enabled. 305 * | | |1 = External VCONN OCP circuit disabled. 306 * |[1] |VBOVDTDS |Internal VBUS Over Voltage Protection Fault Detect Disable 307 * | | |0 = Internal OVP circuit enabled. 308 * | | |1 = Internal OVP circuit disabled. 309 * | | |Note: Internal VBUS over voltage protection means to use ADC to measure VBUS voltage. 310 * |[2] |VBOCDTDS |External VBUS Overcurrent Protection Fault Detect Disable 311 * | | |0 = External OCP circuit enabled. 312 * | | |1 = External OCP circuit disabled. 313 * |[3] |VBDGTMDS |VBUS Discharge Fault Detection Timer Disable 314 * | | |0 = VBUS Discharge Fault Detection Timer enabled. 315 * | | |1 = VBUS Discharge Fault Detection Timer disabled. 316 * | | |This enables the timer for both force discharge and auto discharge 317 * | | |No timer for bleed discharge 318 * | | |Once time-out, UTCPD will compare VBUS voltage with VSAFE0V or SP_DGTH, depends on setting of ADGDC and FDGEN. 319 * |[4] |FOFFVBDS |Force Off VBUS Disable 320 * | | |0 = Enabled. 321 * | | |1 = Disabled. 322 * @var UTCPD_T::PWRCTL 323 * Offset: 0x34 UTCPD Power Control Register 324 * --------------------------------------------------------------------------------------------------- 325 * |Bits |Field |Descriptions 326 * | :----: | :----: | :---- | 327 * |[0] |VCEN |Enable VCONN 328 * | | |0 = Disable VCONN Source (default). 329 * | | |1 = Enable VCONN Source to CC. 330 * |[1] |VCPWR |VCONN Power Supported 331 * | | |0 = UTCPD delivers at least 1W on VCONN. 332 * | | |1 = UTCPD delivers at least the power indicated in CPVCPWR (UTCPD_DVCAP2[3:1]). 333 * |[2] |FDGEN |Enable Force Discharge 334 * | | |0 = Disable forced discharge (default). 335 * | | |1 = Enable forced discharge of VBUS. 336 * | | |Force discharge is used for source only. 337 * | | |This bit will only be cleared by CPU. 338 * |[3] |BDGEN |Enable Bleed Discharge 339 * | | |0 = Disable bleed discharge (default). 340 * | | |1 = Enable bleed discharge of VBUS. 341 * | | |Bleed Discharge is a low current discharge to provide a minimum load current if needed 342 * | | |10K Ohms or 2mA recommended. Bleed discharge is used for sink only. 343 * | | |This bit will only be cleared by CPU. 344 * |[4] |ADGDC |Auto Discharge Disconnect 345 * | | |0 = The UTCPD shall not automatically discharge VBUS based on VBUS voltage (default). 346 * | | |1 = The UTCPD shall automatically discharge when disconnect detected. 347 * | | |Setting this bit in a Source UTCPD triggers the following actions upon a disconnect detection: 348 * | | |1. Disable sourcing power over VBUS 349 * | | |2. VBUS discharge 350 * | | |Sourcing power over VBUS shall be disabled before or at the same time as starting VBUS discharge. 351 * | | |Setting this bit in a Sink UTCPD triggers the following action upon a disconnect detection: 352 * | | |1. VBUS discharge 353 * | | |The UTCPD shall automatically disable discharge (without clearing this bit) once the voltage on VBUS is below vSafe0V (max) 354 * | | |UTCPD shall not re-apply discharge circuit if VBUS rises above vSafe0V. 355 * | | |This bit will only be cleared by CPU. 356 * |[5] |DSVBAM |Disable VBUS Voltage Alarms 357 * | | |0 = VBUS Voltage Alarms Power status reporting is enabled. 358 * | | |1 = VBUS Voltage Alarms Power status reporting is disabled (default). 359 * |[6] |VBMONI |VBUS Voltage Monitor Enable 360 * | | |0 = VBUS Voltage Monitoring is enabled. 361 * | | |1 = VBUS Voltage Monitoring is disabled (default). 362 * | | |Controls VBUS voltage Monitoring. UTCPD_VBVOL shall report all zeroes if disabled. 363 * @var UTCPD_T::CCSTS 364 * Offset: 0x38 UTCPD CC Status Register 365 * --------------------------------------------------------------------------------------------------- 366 * |Bits |Field |Descriptions 367 * | :----: | :----: | :---- | 368 * |[1:0] |CC1STATE |CC1 State 369 * | | |If (CC1 (UTCPD_ROLCTL[1:0])=Rp) or (CONRLT (UTCPD_CCSTS[4]) = 0). 370 * | | |00 = SRC.Open (Open, Rp). 371 * | | |01 = SRC.Ra (below maximum vRa). 372 * | | |10 = SRC.Rd (within the vRd range). 373 * | | |11 = reserved. 374 * | | |If (CC1 (UTCPD_ROLCTL[1:0])=Rd) or (CONRLT (UTCPD_CCSTS[4]) = 1). 375 * | | |00 = SNK.Open (Below maximum vRa). 376 * | | |01 = SNK.Default (Above minimum vRd-Connect). 377 * | | |10 = SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp 1.5A. 378 * | | |11 = SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp 3.0A. 379 * | | |If CC1 (UTCPD_ROLCTL[1:0])=Reserved, this field is set to 00. 380 * | | |If CC1 (UTCPD_ROLCTL[1:0])=Open, this field is set to 00. 381 * | | |This field always returns 00 if (LK4CONN=1) or (VCEN (UTCPD_PWRCTL[0])]=1 and ORIENT (UTCPD_CTL[0])=1) 382 * | | |Otherwise, the returned value depends upon CC1 (UTCPD_ROLCTL[1:0]) 383 * |[3:2] |CC2STATE |CC2 State 384 * | | |If (CC2 (UTCPD_ROLCTL[3:2]=Rp) or (CONRLT (UTCPD_CCSTS[4]) = 0). 385 * | | |00 = SRC.Open (Open, Rp). 386 * | | |01 = SRC.Ra (below maximum vRa). 387 * | | |10 = SRC.Rd (within the vRd range). 388 * | | |11 = reserved. 389 * | | |If (CC2 (UTCPD_ROLCTL[3:2])=Rd) or (CONRLT (UTCPD_CCSTS[4]) = 1). 390 * | | |00 = SNK.Open (Below maximum vRa). 391 * | | |01 = SNK.Default (Above minimum vRd-Connect). 392 * | | |10 = SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp 1.5A. 393 * | | |11 = SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp 3.0A. 394 * | | |If CC2 (UTCPD_ROLCTL[3:2])=Reserved, this field is set to 00. 395 * | | |If CC2 (UTCPD_ROLCTL[3:2])=Open, this field is set to 00. 396 * | | |This field always returns 00 if (LK4CONN=1) or (VCEN (UTCPD_PWRCTL[0])=1 and ORIENT (UTCPD_CTL[0])=0) 397 * | | |Otherwise, the returned value depends upon CC2 (UTCPD_ROLCTL[3:2]) 398 * |[4] |CONRLT |Connect Result (read only) 399 * | | |0 = the UTCPD is presenting Rp. 400 * | | |1 = the UTCPD is presenting Rd. 401 * |[5] |LK4CONN |Looking for Connection 402 * | | |0 = UTCPD is not actively looking for a connection 403 * | | |A transition from '1' to '0' indicates a potential connection has been found. 404 * | | |1 = UTCPD is looking for a connection (toggling as a DRP or looking for a connection as Sink/Source only condition) 405 * @var UTCPD_T::PWRSTS 406 * Offset: 0x3C UTCPD Power Status Register 407 * --------------------------------------------------------------------------------------------------- 408 * |Bits |Field |Descriptions 409 * | :----: | :----: | :---- | 410 * |[0] |SKVB |Sinking VBUS 411 * | | |0 = Sink is Disconnected (Default). 412 * | | |1 = UTCPD is sinking VBUS to the system load. 413 * |[1] |VCPS |VCONN Present 414 * | | |0 = VCONN is not present. 415 * | | |1 = This bit is asserted when VCONN present CC1 or CC2. Threshold is fixed at 2.4V. 416 * | | |If VCEN (UTCPD_PWRCTL[0])] is disabled VCONN Present should be set to 0. 417 * |[2] |VBPS |VBUS Present 418 * | | |0 = VBUS Disconnected. 419 * | | |1 = VBUS Connected. 420 * | | |The UTCPD shall report VBUS present when UTCPD detects VBUS rises above 4V. 421 * | | |The UTCPD shall report VBUS is not present when UTCPD detects VBUS falls below 3.5V. 422 * |[3] |VBPSDTEN |VBUS Present Detection Enabled 423 * | | |0 = VBUS Present Detection Disabled. 424 * | | |1 = VBUS Present Detection Enabled (default). 425 * |[4] |SRVB |Sourcing VBUS 426 * | | |0 = Sourcing VBUS is disabled. 427 * | | |1 = Sourcing VBUS is enabled. 428 * | | |This bit does not control the path, just provides a monitor of the status. 429 * |[5] |SRHV |Sourcing High Voltage 430 * | | |0 = VSAFE5V. 431 * | | |1 = Higher Voltage. 432 * | | |This bit does not control the power path, it just provides a monitor of the status 433 * | | |This bit is asserted as long as the UTCPD is sourcing nondefault voltage over VBUS (i.e 434 * | | |not VSAFE5V) as a response to CPU writing 0x88 to CMD (Source VBUS High Voltage) 435 * |[7] |DACON |Debug Accessory Connected 436 * | | |0 = No Debug Accessory connected (default). 437 * | | |1 = Debug Accessory connected. 438 * @var UTCPD_T::FUTSTS 439 * Offset: 0x40 UTCPD Fault Status Register 440 * --------------------------------------------------------------------------------------------------- 441 * |Bits |Field |Descriptions 442 * | :----: | :----: | :---- | 443 * |[1] |VCOCFUT |VCONN Overcurrent Protection Fault 444 * | | |0 = Not in an overcurrent protection state. 445 * | | |1 = Overcurrent fault latched. 446 * |[2] |VBOVFUT |VBUS Over Voltage Protection Fault 447 * | | |0 = No Fault detected. 448 * | | |1 = Over-voltage fault latched. 449 * |[3] |VBOCFUT |VBUS Overcurrent Protection Fault 450 * | | |0 = Not in an overcurrent protection state. 451 * | | |1 = Overcurrent fault latched. 452 * |[4] |FDGFAL |Force Discharge Failed 453 * | | |0 = No discharge failure. 454 * | | |1 = Discharge commanded by the TCPM failed. 455 * | | |If FDGEN (UTCPD_PWRCTL[2]) is set, the UTCPD shall report a discharge fails if VBUS is not below vSafe0V within tSafe0V 456 * |[5] |ADGFAL |Auto Discharge Failed 457 * | | |0 = No discharge failure. 458 * | | |1 = Discharge commanded by the TCPM failed. 459 * | | |If ADGDC (UTCPD_PWRCTL[4]) is set, the UTCPD shall report discharge fails if VBUS is not below vSafe0V within tSafe0V 460 * |[6] |FOFFVB |Force Off VBUS 461 * | | |0 = No Fault Detected, no action (default and not supported). 462 * | | |1 = VBUS Source/Sink has been forced off due to external fault. 463 * | | |The UTCPD has disconnected VBUS due to external inputs (EINT0 ~ EINT5) 464 * @var UTCPD_T::CMD 465 * Offset: 0x44 UTCPD Command Register 466 * --------------------------------------------------------------------------------------------------- 467 * |Bits |Field |Descriptions 468 * | :----: | :----: | :---- | 469 * |[7:0] |CMD |Command Set 470 * | | |0x22 = Disable VBUS Detect. 471 * | | |0x33 = Enable VBUS Detect. 472 * | | |0x44 = Disable Sink VBUS. 473 * | | |0x55 = Enable Sink VBUS. 474 * | | |0x66 = Disable Source VBUS. 475 * | | |0x77 = Enable Source VBUS 5V. 476 * | | |0x88 = Source VBUS High Voltage. 477 * | | |0x99 = Look4Connection. 478 * | | |0xAA = RxOneMore. 479 * | | |Others: Reserved. 480 * | | |The Command is issued by the CPU 481 * | | |The Command is cleared by the UTCPD after being acted upon 482 * | | |It always read as 0. 483 * @var UTCPD_T::DVCAP1 484 * Offset: 0x48 UTCPD Device Capabilities 1 Register 485 * --------------------------------------------------------------------------------------------------- 486 * |Bits |Field |Descriptions 487 * | :----: | :----: | :---- | 488 * |[0] |CPSRVB |Source VBUS 489 * | | |0 = TCPC is not capable of controlling the source path to VBUS. 490 * | | |1 = TCPC is capable of controlling the source path to VBUS. 491 * |[1] |CPSRHV |Source High Voltage VBUS 492 * | | |0 = UTCPD is not capable of controlling the source high voltage path to VBUS. 493 * | | |1 = UTCPD is capable of controlling the source high voltage path to VBUS. 494 * |[2] |CPSKVB |Sink VBUS 495 * | | |0 = UTCPD is not capable controlling the sink path to the system load. 496 * | | |1 = UTCPD is capable of controlling the sink path to the system load. 497 * |[3] |CPSRVC |Source VCONN 498 * | | |0 = UTCPD is not capable of switching VCONN. 499 * | | |1 = UTCPD is capable of switching VCONN. 500 * |[4] |CPSDBG |SOP'_DBG/SOP''_DBG Support 501 * | | |0 = All SOP* except SOP'_DBG/SOP''_DBG. 502 * | | |1 = All SOP* messages are supported. 503 * |[7:5] |CPROL |Roles Supported 504 * | | |000 = USB Type-C Port Manager can configure the Port as Source only or Sink only (not DRP). 505 * | | |001 = Source only. 506 * | | |010 = Sink only. 507 * | | |011 = Sink with accessory support. 508 * | | |100 = DRP only. 509 * | | |101 = Source, Sink, DRP, Adapter/Cable all supported. 510 * | | |110 = Source, Sink, DRP. 511 * | | |111 = Not valid. 512 * |[9:8] |CPSRRE |Source Resistor Supported 513 * | | |00 = Rp default only. 514 * | | |01 = Rp 1.5A and default. 515 * | | |10 = Rp 3.0A, 1.5A, and default. 516 * | | |11 = Reserved. 517 * |[10] |CPVBAM |VBUS Measurement and Alarm Capable 518 * | | |0 = No VBUS voltage measurement nor VBUS Alarms. 519 * | | |1 = VBUS voltage measurement and VBUS Alarms. 520 * |[11] |CPFDG |Force Discharge 521 * | | |0 = No Force Discharge implemented. 522 * | | |1 = Force Discharge is implemented. 523 * |[12] |CPBDG |Bleed Discharge 524 * | | |0 = No Bleed Discharge implemented. 525 * | | |1 = Bleed Discharge is implemented. 526 * |[13] |CPVBOVP |VBUS OVP Reporting 527 * | | |0 = VBUS OVP is not reported. 528 * | | |1 = VBUS OVP is reported. 529 * |[14] |CPVBOCP |VBUS OCP Reporting 530 * | | |0 = VBUS OCP is not reported. 531 * | | |1 = VBUS OCP is reported. 532 * @var UTCPD_T::DVCAP2 533 * Offset: 0x4C UTCPD Device Capabilities 2 Register 534 * --------------------------------------------------------------------------------------------------- 535 * |Bits |Field |Descriptions 536 * | :----: | :----: | :---- | 537 * |[0] |CPVCOC |VCONN Overcurrent Fault Capable 538 * | | |0 = UTCPD is not capable of detecting a Vconn fault. 539 * | | |1 = UTCPD is capable of detecting a Vconn fault. 540 * |[3:1] |CPVCPWR |VCONN Power Supported 541 * | | |000 = 1.0W. 542 * | | |001 = 1.5W. 543 * | | |010 = 2.0W. 544 * | | |011 = 3W. 545 * | | |100 = 4W. 546 * | | |101 = 5W. 547 * | | |110 = 6W. 548 * | | |111 = External. 549 * |[5:4] |CPVBAMLS |VBUS Voltage Alarm LSB 550 * | | |00 = UTCPD has 25mV LSB for its voltage alarm and uses all 10 bits in. 551 * | | |VB_AMH and VB_AML. 552 * | | |Others = Reserved. 553 * |[6] |CPSPDGTH |Stop Discharge Threshold 554 * | | |0 = UTCPD_SPDGTH not implemented. 555 * | | |1 = UTCPD_SPDGTH implemented. 556 * |[7] |CPSKDCDT |Sink Disconnect Detection 557 * | | |0 = UTCPD_SKVBDCTH not implemented. 558 * | | |1 = UTCPD_SKVBDCTH implemented. 559 * @var UTCPD_T::MSHEAD 560 * Offset: 0x50 UTCPD Message Header Info Register 561 * --------------------------------------------------------------------------------------------------- 562 * |Bits |Field |Descriptions 563 * | :----: | :----: | :---- | 564 * |[0] |PWRROL |Power Role 565 * | | |0 = Sink. 566 * | | |1 = Source. 567 * |[2:1] |PDREV |USB PD Specification Revision 568 * | | |00 = Revision 1.0. 569 * | | |01 = Revision 2.0. 570 * | | |10 = Revision 3.0. 571 * | | |11 = Revision 3.1. 572 * |[3] |DAROL |Data Role 573 * | | |0 = UFP. 574 * | | |1 = DFP. 575 * |[4] |CABPLG |Cable Plug 576 * | | |0 = Message originated from Source, Sink, or DRP. 577 * | | |1 = Message originated from a Cable Plug. 578 * @var UTCPD_T::DTRXEVNT 579 * Offset: 0x54 UTCPD Enable Detect RX Event Register 580 * --------------------------------------------------------------------------------------------------- 581 * |Bits |Field |Descriptions 582 * | :----: | :----: | :---- | 583 * |[0] |SOPEN |Enable SOP message 584 * | | |0 = UTCPD does not detect SOP message (default). 585 * | | |1 = UTCPD detects SOP message. 586 * |[1] |SOPPEN |Enable SOP' message 587 * | | |0 = UTCPD does not detect SOP' message (default). 588 * | | |1 = UTCPD detects SOP' message. 589 * |[2] |SOPPPEN |Enable SOP'' message 590 * | | |0 = UTCPD does not detect SOP'' message (default). 591 * | | |1 = UTCPD detects SOP'' message. 592 * |[3] |SDBGPEN |Enable SOP_DBG' message 593 * | | |0 = UTCPD does not detect SOP_DBG' message (default). 594 * | | |1 = UTCPD detects SOP_DBG' message. 595 * |[4] |SDBGPPEN |Enable SOP_DBG'' message 596 * | | |0 = UTCPD does not detect SOP_DBG'' message (default). 597 * | | |1 = UTCPD detects SOP_DBG'' message. 598 * |[5] |HRSTEN |Enable Hard Reset 599 * | | |0 = UTCPD does not detect Hard Reset signaling (default). 600 * | | |1 = UTCPD detects Hard Reset signaling. 601 * |[6] |CABRSTEN |Enable Cable Reset 602 * | | |0 = UTCPD does not detect Cable Reset signaling (default). 603 * | | |1 = UTCPD detects Cable Reset signaling. 604 * @var UTCPD_T::RXBCNT 605 * Offset: 0x58 UTCPD RX Byte Count Register 606 * --------------------------------------------------------------------------------------------------- 607 * |Bits |Field |Descriptions 608 * | :----: | :----: | :---- | 609 * |[7:0] |RXBCNT |Receive Byte Count 610 * | | |Indicates number of bytes in this register that are not stale 611 * | | |CPU should read the first RXBCNT bytes in this register 612 * | | |This is the number of bytes in the UTCPD_RXDAx plus three (for the RXFTYPE and RXHEAD). 613 * | | |The UTCPD shall clear the UTCPD_DTRXEVNT and the UTCPD_RXBCNT register to disable the PD message passing when CPU writes the UTCPD_TXCTL register requesting a Hard Reset 614 * @var UTCPD_T::RXFTYPE 615 * Offset: 0x5C UTCPD Received Frame Type Register 616 * --------------------------------------------------------------------------------------------------- 617 * |Bits |Field |Descriptions 618 * | :----: | :----: | :---- | 619 * |[2:0] |RXFTYPE |Received Frame Type 620 * | | |000 = Received SOP. 621 * | | |001 = Received SOP'. 622 * | | |010 = Received SOP''. 623 * | | |011 = Received SOP_DBG'. 624 * | | |100 = Received SOP_DBG''. 625 * | | |110 = Received Cable Reset. 626 * | | |All others are reserved. 627 * @var UTCPD_T::RXHEAD 628 * Offset: 0x60 UTCPD Received Header Data Register 629 * --------------------------------------------------------------------------------------------------- 630 * |Bits |Field |Descriptions 631 * | :----: | :----: | :---- | 632 * |[7:0] |RXHEAD0 |USB PD message header byte 0 633 * |[15:8] |RXHEAD1 |USB PD message header byte 1 634 * @var UTCPD_T::RXDA0 635 * Offset: 0x70 UTCPD Received Data0 Register 636 * --------------------------------------------------------------------------------------------------- 637 * |Bits |Field |Descriptions 638 * | :----: | :----: | :---- | 639 * |[7:0] |RXDAB0 |USB PD Received Datax byte 0 640 * |[15:8] |RXDAB1 |USB PD Received Datax byte 1 641 * |[23:16] |RXDAB2 |USB PD Received Datax byte 2 642 * |[31:24] |RXDAB3 |USB PD Received Datax byte 3 643 * @var UTCPD_T::RXDA1 644 * Offset: 0x74 UTCPD Received Data1 Register 645 * --------------------------------------------------------------------------------------------------- 646 * |Bits |Field |Descriptions 647 * | :----: | :----: | :---- | 648 * |[7:0] |RXDAB0 |USB PD Received Datax byte 0 649 * |[15:8] |RXDAB1 |USB PD Received Datax byte 1 650 * |[23:16] |RXDAB2 |USB PD Received Datax byte 2 651 * |[31:24] |RXDAB3 |USB PD Received Datax byte 3 652 * @var UTCPD_T::RXDA2 653 * Offset: 0x78 UTCPD Received Data2 Register 654 * --------------------------------------------------------------------------------------------------- 655 * |Bits |Field |Descriptions 656 * | :----: | :----: | :---- | 657 * |[7:0] |RXDAB0 |USB PD Received Datax byte 0 658 * |[15:8] |RXDAB1 |USB PD Received Datax byte 1 659 * |[23:16] |RXDAB2 |USB PD Received Datax byte 2 660 * |[31:24] |RXDAB3 |USB PD Received Datax byte 3 661 * @var UTCPD_T::RXDA3 662 * Offset: 0x7C UTCPD Received Data3 Register 663 * --------------------------------------------------------------------------------------------------- 664 * |Bits |Field |Descriptions 665 * | :----: | :----: | :---- | 666 * |[7:0] |RXDAB0 |USB PD Received Datax byte 0 667 * |[15:8] |RXDAB1 |USB PD Received Datax byte 1 668 * |[23:16] |RXDAB2 |USB PD Received Datax byte 2 669 * |[31:24] |RXDAB3 |USB PD Received Datax byte 3 670 * @var UTCPD_T::RXDA4 671 * Offset: 0x80 UTCPD Received Data4 Register 672 * --------------------------------------------------------------------------------------------------- 673 * |Bits |Field |Descriptions 674 * | :----: | :----: | :---- | 675 * |[7:0] |RXDAB0 |USB PD Received Datax byte 0 676 * |[15:8] |RXDAB1 |USB PD Received Datax byte 1 677 * |[23:16] |RXDAB2 |USB PD Received Datax byte 2 678 * |[31:24] |RXDAB3 |USB PD Received Datax byte 3 679 * @var UTCPD_T::RXDA5 680 * Offset: 0x84 UTCPD Received Data5 Register 681 * --------------------------------------------------------------------------------------------------- 682 * |Bits |Field |Descriptions 683 * | :----: | :----: | :---- | 684 * |[7:0] |RXDAB0 |USB PD Received Datax byte 0 685 * |[15:8] |RXDAB1 |USB PD Received Datax byte 1 686 * |[23:16] |RXDAB2 |USB PD Received Datax byte 2 687 * |[31:24] |RXDAB3 |USB PD Received Datax byte 3 688 * @var UTCPD_T::RXDA6 689 * Offset: 0x88 UTCPD Received Data6 Register 690 * --------------------------------------------------------------------------------------------------- 691 * |Bits |Field |Descriptions 692 * | :----: | :----: | :---- | 693 * |[7:0] |RXDAB0 |USB PD Received Datax byte 0 694 * |[15:8] |RXDAB1 |USB PD Received Datax byte 1 695 * |[23:16] |RXDAB2 |USB PD Received Datax byte 2 696 * |[31:24] |RXDAB3 |USB PD Received Datax byte 3 697 * @var UTCPD_T::TXCTL 698 * Offset: 0x90 UTCPD TX Control Register 699 * --------------------------------------------------------------------------------------------------- 700 * |Bits |Field |Descriptions 701 * | :----: | :----: | :---- | 702 * |[2:0] |TXSTYPE |Transmit SOP* message 703 * | | |000 = Transmit SOP. 704 * | | |001 = Transmit SOP'. 705 * | | |010 = Transmit SOP''. 706 * | | |011 = Transmit SOP_DBG'. 707 * | | |100 = Transmit SOP_DBG''. 708 * | | |101 = Transmit Hard Reset. 709 * | | |110 = Transmit Cable Reset. 710 * | | |111 = Transmit BIST Carrier Mode 2. 711 * | | |The UTCPD shall ignore the Retry Counter bits when transmitting a Hard Reset, Cable Reset, or BIST Carrier 712 * |[5:4] |RETRYCNT |Retry Counter 713 * | | |00 = No message retry is required. 714 * | | |01 = Automatically retry message transmission once. 715 * | | |10 = Automatically retry message transmission twice. 716 * | | |11 = Automatically retry message transmission three times. 717 * @var UTCPD_T::TXBCNT 718 * Offset: 0x94 UTCPD TX Byte Count Register 719 * --------------------------------------------------------------------------------------------------- 720 * |Bits |Field |Descriptions 721 * | :----: | :----: | :---- | 722 * |[7:0] |TXBCNT |Transmit Byte Count 723 * | | |This is the number of bytes in the UTCPD_TXDA plus two (for the TXHEAD) 724 * | | |If a previous transmit request has not yet completed when TX_CTL is written requesting a Hard Reset, the UTCPD shall assert the Transmission Discarded bit(TXDCUTIS (UTCPD_IS[5])). 725 * | | |The UTCPD shall assert both TXOKIS (UTCPD_IS[6]) and TXFALIS (UTCPD_IS[4]) after it completes the sending of a Hard Reset 726 * @var UTCPD_T::TXHEAD 727 * Offset: 0x98 UTCPD TX Header Data Register 728 * --------------------------------------------------------------------------------------------------- 729 * |Bits |Field |Descriptions 730 * | :----: | :----: | :---- | 731 * |[7:0] |TXHEAD0 |Transmit Header Byte 0 732 * |[15:8] |TXHEAD1 |Transmit Header Byte 1 733 * @var UTCPD_T::TXDA0 734 * Offset: 0xA0 UTCPD Transmit Data0 Register 735 * --------------------------------------------------------------------------------------------------- 736 * |Bits |Field |Descriptions 737 * | :----: | :----: | :---- | 738 * |[7:0] |TXDAB0 |USB PD Transmit Datax byte 0 739 * |[15:8] |TXDAB1 |USB PD Transmit Datax byte 1 740 * |[23:16] |TXDAB2 |USB PD Transmit Datax byte 2 741 * |[31:24] |TXDAB3 |USB PD Transmit Datax byte 3 742 * @var UTCPD_T::TXDA1 743 * Offset: 0xA4 UTCPD Transmit Data1 Register 744 * --------------------------------------------------------------------------------------------------- 745 * |Bits |Field |Descriptions 746 * | :----: | :----: | :---- | 747 * |[7:0] |TXDAB0 |USB PD Transmit Datax byte 0 748 * |[15:8] |TXDAB1 |USB PD Transmit Datax byte 1 749 * |[23:16] |TXDAB2 |USB PD Transmit Datax byte 2 750 * |[31:24] |TXDAB3 |USB PD Transmit Datax byte 3 751 * @var UTCPD_T::TXDA2 752 * Offset: 0xA8 UTCPD Transmit Data2 Register 753 * --------------------------------------------------------------------------------------------------- 754 * |Bits |Field |Descriptions 755 * | :----: | :----: | :---- | 756 * |[7:0] |TXDAB0 |USB PD Transmit Datax byte 0 757 * |[15:8] |TXDAB1 |USB PD Transmit Datax byte 1 758 * |[23:16] |TXDAB2 |USB PD Transmit Datax byte 2 759 * |[31:24] |TXDAB3 |USB PD Transmit Datax byte 3 760 * @var UTCPD_T::TXDA3 761 * Offset: 0xAC UTCPD Transmit Data3 Register 762 * --------------------------------------------------------------------------------------------------- 763 * |Bits |Field |Descriptions 764 * | :----: | :----: | :---- | 765 * |[7:0] |TXDAB0 |USB PD Transmit Datax byte 0 766 * |[15:8] |TXDAB1 |USB PD Transmit Datax byte 1 767 * |[23:16] |TXDAB2 |USB PD Transmit Datax byte 2 768 * |[31:24] |TXDAB3 |USB PD Transmit Datax byte 3 769 * @var UTCPD_T::TXDA4 770 * Offset: 0xB0 UTCPD Transmit Data4 Register 771 * --------------------------------------------------------------------------------------------------- 772 * |Bits |Field |Descriptions 773 * | :----: | :----: | :---- | 774 * |[7:0] |TXDAB0 |USB PD Transmit Datax byte 0 775 * |[15:8] |TXDAB1 |USB PD Transmit Datax byte 1 776 * |[23:16] |TXDAB2 |USB PD Transmit Datax byte 2 777 * |[31:24] |TXDAB3 |USB PD Transmit Datax byte 3 778 * @var UTCPD_T::TXDA5 779 * Offset: 0xB4 UTCPD Transmit Data5 Register 780 * --------------------------------------------------------------------------------------------------- 781 * |Bits |Field |Descriptions 782 * | :----: | :----: | :---- | 783 * |[7:0] |TXDAB0 |USB PD Transmit Datax byte 0 784 * |[15:8] |TXDAB1 |USB PD Transmit Datax byte 1 785 * |[23:16] |TXDAB2 |USB PD Transmit Datax byte 2 786 * |[31:24] |TXDAB3 |USB PD Transmit Datax byte 3 787 * @var UTCPD_T::TXDA6 788 * Offset: 0xB8 UTCPD Transmit Data6 Register 789 * --------------------------------------------------------------------------------------------------- 790 * |Bits |Field |Descriptions 791 * | :----: | :----: | :---- | 792 * |[7:0] |TXDAB0 |USB PD Transmit Datax byte 0 793 * |[15:8] |TXDAB1 |USB PD Transmit Datax byte 1 794 * |[23:16] |TXDAB2 |USB PD Transmit Datax byte 2 795 * |[31:24] |TXDAB3 |USB PD Transmit Datax byte 3 796 * @var UTCPD_T::VBVOL 797 * Offset: 0xC0 UTCPD VBUS Voltage Register 798 * --------------------------------------------------------------------------------------------------- 799 * |Bits |Field |Descriptions 800 * | :----: | :----: | :---- | 801 * |[9:0] |VBVOL |VBUS voltage measurement 802 * | | |10-bit measurement of (VBUS / Scale Factor) 803 * | | |CPU multiplies this value by the scale factor to obtain the voltage measurement 804 * | | |Voltages greater than or equal to 4V shall meet +/-2% absolute value or +/- 50mV, whichever is greater 805 * | | |The LSB is 25mV 806 * |[11:10] |VBSCALE |VBUS Scale Factor 807 * | | |00 = VBUS measurement not scaled. 808 * | | |01 = VBUS measurement divided by 10. 809 * | | |10 = VBUS measurement divided by 20. 810 * | | |11 = reserved. 811 * @var UTCPD_T::SKVBDCTH 812 * Offset: 0xC4 UTCPD VBUS Sink disconnect threshold Register 813 * --------------------------------------------------------------------------------------------------- 814 * |Bits |Field |Descriptions 815 * | :----: | :----: | :---- | 816 * |[9:0] |SKVBDCTH |Sink VBUS disconnect threshold 817 * | | |10-bit for voltage threshold with 25mV LSB. (Default 3.5V) 818 * | | |A value of zero disables this threshold. 819 * @var UTCPD_T::SPDGTH 820 * Offset: 0xC8 UTCPD VBUS Stop Discharge threshold Register 821 * --------------------------------------------------------------------------------------------------- 822 * |Bits |Field |Descriptions 823 * | :----: | :----: | :---- | 824 * |[9:0] |SPDGTH |VBUS Stop Force Discharge Threshold 825 * | | |This value is used as a threshold hold for force discharge fail. 826 * | | |The default is 0.8V. 827 * | | |The CPU writes to this register to set the threshold at which a Source shall stop the Forced Discharge circuit when FDGEN (UTCPD_PWRCTL[2]) is 1. 828 * @var UTCPD_T::VBAMH 829 * Offset: 0xCC UTCPD VBUS voltage high alarm threshold Register 830 * --------------------------------------------------------------------------------------------------- 831 * |Bits |Field |Descriptions 832 * | :----: | :----: | :---- | 833 * |[9:0] |VBAMH |VBUS voltage high Alarm threshold register 834 * @var UTCPD_T::VBAML 835 * Offset: 0xD0 UTCPD VBUS voltage low alarm threshold Register 836 * --------------------------------------------------------------------------------------------------- 837 * |Bits |Field |Descriptions 838 * | :----: | :----: | :---- | 839 * |[9:0] |VBAML |VBUS voltage low Alarm threshold register 840 * @var UTCPD_T::VNDIS 841 * Offset: 0xD4 UTCPD Vendor defined Interrupt Status Register 842 * --------------------------------------------------------------------------------------------------- 843 * |Bits |Field |Descriptions 844 * | :----: | :----: | :---- | 845 * |[0] |RXFRSIS |Fast Role Swap RX Interrupt Status 846 * | | |0 = Cleared. 847 * | | |1 = The event has been detected. 848 * |[1] |TXFRSIS |Fast Role Swap TX Interrupt Status 849 * | | |0 = Cleared. 850 * | | |1 = The event has been detected. 851 * |[3] |CRCERRIS |CRC Error Interrupt Status 852 * | | |0 = Cleared. 853 * | | |1 = The event has been detected. 854 * |[5] |VCDGIS |VCONN Discharge Interrupt Status 855 * @var UTCPD_T::VNDIE 856 * Offset: 0xD8 UTCPD Vendor defined Interrupt Enable Register 857 * --------------------------------------------------------------------------------------------------- 858 * |Bits |Field |Descriptions 859 * | :----: | :----: | :---- | 860 * |[0] |RXFRSIE |Fast Role Swap RX Interrupt Enable 861 * | | |0 = Disable. 862 * | | |1 = Enable. 863 * |[1] |TXFRSIE |Fast Role Swap TX Interrupt Enable 864 * | | |0 = Disable. 865 * | | |1 = Enable. 866 * |[3] |CRCERRIE |CRC Error Interrupt Enable 867 * | | |0 = Disable. 868 * | | |1 = Enable. 869 * |[5] |VCDGIE |VCONN Discharge Interrupt Enable 870 * | | |0 = Disable. 871 * | | |1 = Enable. 872 * @var UTCPD_T::MUXSEL 873 * Offset: 0xDC UTCPD Mux Select Register 874 * --------------------------------------------------------------------------------------------------- 875 * |Bits |Field |Descriptions 876 * | :----: | :----: | :---- | 877 * |[2:0] |VBOCS |VBUS Overcurrent Source Select 878 * | | |000 = EINT0. 879 * | | |001 = EINT1. 880 * | | |010 = EINT2. 881 * | | |011 = EINT3. 882 * | | |100 = ADC Comparator out. 883 * | | |101 = ACMP0. 884 * | | |110 = ACMP1. 885 * | | |111 = ACMP2. 886 * |[6:4] |VCOCS |VCONN Overcurrent Source Select 887 * | | |000 = EINT0. 888 * | | |001 = EINT1. 889 * | | |010 = EINT2. 890 * | | |011 = EINT3. 891 * | | |100 = ADC Comparator out. 892 * | | |101 = ACMP0. 893 * | | |110 = ACMP1. 894 * | | |111 = ACMP2. 895 * |[10:8] |FVBS |Force off VBUS Select 896 * | | |000 = ENIT0. 897 * | | |001 = EINT1. 898 * | | |010 = EINT2. 899 * | | |011 = ENIT3. 900 * | | |100 = EINT4. 901 * | | |101 = EINT5. 902 * | | |110 = Reserved. 903 * | | |111 = Reserved. 904 * |[16:12] |ADCSELVB |ADC Channel Select for VBUS 905 * | | |ADC result will be latched into VB_VOL_MEA register once ADC_CSEL_VB matches ADC_CHSEL and ADC finishes. 906 * |[21:17] |ADCSELVC |ADC Channel Select for VCONN 907 * | | |ADC result will be latched into VC_VOL_MEA register once ADC_CSEL_VC matches ADC_CHSEL and ADC finishes. 908 * |[24] |CC1VCENS |CC1 VCONN Enable Select 909 * | | |0 = Merged CC1 and CC2 VCONN enable signal. 910 * | | |1 = CC1 VCONN enable signal. 911 * |[25] |CC1FRSS |CC1 VCONN Fast Role Swap Select 912 * | | |0 = Merged CC1 and CC2 VCONN Fast Role Swap signal. 913 * | | |1 = CC1 VCONN Fast Role Swap signal. 914 * |[28] |CC2VCENS |CC2 VCONN Enable Select 915 * | | |0 = Merged CC1 and CC2 VCONN enable signal. 916 * | | |1 = CC2 VCONN enable signal. 917 * |[29] |CC2FRSS |CC2 VCONN Fast Role Swap Select 918 * | | |0 = Merged CC1 and CC2 Fast Role Swap signal. 919 * | | |1 = CC2 VCONN discharge signal. 920 * @var UTCPD_T::VCDGCTL 921 * Offset: 0xE0 UTCPD VCONN Discharge Control Register 922 * --------------------------------------------------------------------------------------------------- 923 * |Bits |Field |Descriptions 924 * | :----: | :----: | :---- | 925 * |[0] |VCUVDTEN |VCONN Under Voltage Detect Enable 926 * | | |0 = Disabled. 927 * | | |1 = Enabled. 928 * |[1] |VCDGEN |VCONN Discharge Enable 929 * | | |0 = Disabled. 930 * | | |1 = Enabled. 931 * @var UTCPD_T::PHYSLEW 932 * Offset: 0xE4 UTCPD PHY Slew Rate Control Register 933 * --------------------------------------------------------------------------------------------------- 934 * |Bits |Field |Descriptions 935 * | :----: | :----: | :---- | 936 * |[2:0] |TXRTRIM |TX Trim Rising slew rate 937 * | | |It is for BMC eye diagram. 938 * | | |Trim PHY TX Rising slew rate (from ROMMAP) 939 * |[6:4] |TXFTRIM |TX Trim Falling slew rate 940 * | | |It is for BMC eye diagram. 941 * | | |Trim PHY TX falling slew rate. (from ROMMAP) 942 * @var UTCPD_T::ADGTM 943 * Offset: 0xE8 UTCPD Auto Discharge Time Register 944 * --------------------------------------------------------------------------------------------------- 945 * |Bits |Field |Descriptions 946 * | :----: | :----: | :---- | 947 * |[7:0] |ADGTM |Auto Discharge time 948 * | | |Default Time = 31.25us x 16 x 100 (0x16) = 49.9ms. 949 * @var UTCPD_T::VSAFE0V 950 * Offset: 0xEC UTCPD Auto Discharge VSAFE0V Register 951 * --------------------------------------------------------------------------------------------------- 952 * |Bits |Field |Descriptions 953 * | :----: | :----: | :---- | 954 * |[9:0] |VSAFE0V |Set the vSafe0V voltage level. 955 * @var UTCPD_T::VSAFE5V 956 * Offset: 0xF0 UTCPD VSAFE5V Register 957 * --------------------------------------------------------------------------------------------------- 958 * |Bits |Field |Descriptions 959 * | :----: | :----: | :---- | 960 * |[9:0] |VSAFE5V |Set the vSafe5V voltage level 961 * | | |For fast role swap voltage comparison. 962 * @var UTCPD_T::RATIO 963 * Offset: 0xF4 UTCPD DRP Toggle Ratio Register 964 * --------------------------------------------------------------------------------------------------- 965 * |Bits |Field |Descriptions 966 * | :----: | :----: | :---- | 967 * |[2:0] |DRPRATIO |The percent of time that a DRP shall advertise source & sink during tDRP 968 * | | |000 = 50:50 (Sink : Source). 969 * | | |010 = 30:70 (Sink : Source). 970 * | | |001 = 40:60 (Sink : Source). 971 * | | |101 = 60:40 (Sink : Source). 972 * | | |110 =70:30 (Sink: Source). 973 * | | |111 = Reserved. 974 * |[3] |VBSEL |VBUS_VOLTAGE_SEL 975 * | | |Select comparing value (vbus_voltage_s) during vbus discharge determines to stop discharging or not. 976 * | | |1: vbus voltage value from adc 977 * | | |0: vbus voltage value from adc only when VBMONI (UTCPD_PWRCT[6]) is 1. 978 * |[6] |ADCAVG |ADC moving average enable 979 * | | |If enable this bit, average the ADC value for 4 times 980 * @var UTCPD_T::INTFRAME 981 * Offset: 0xF8 UTCPD Inter-Frame Time Register 982 * --------------------------------------------------------------------------------------------------- 983 * |Bits |Field |Descriptions 984 * | :----: | :----: | :---- | 985 * |[7:0] |INTFRAME |USB PD Inter frame gap 986 * | | |Each unit time: 83ns (12 MHz RC) 987 * | | |Time = 83ns x 16 x Inter frame gap time. 988 * | | |Example = 83ns x 16 x 25(8'b00011001) = 33.2us. 989 * @var UTCPD_T::VBOVTH 990 * Offset: 0xFC UTCPD VBUS Over Voltage Threshold Register 991 * --------------------------------------------------------------------------------------------------- 992 * |Bits |Field |Descriptions 993 * | :----: | :----: | :---- | 994 * |[9:0] |VBOVTH |VBUS Over Voltage Threshold 995 * | | |This value defines the VBUS over voltage threshold 996 * | | |10-bit for voltage threshold with 25mV LSB. 997 * @var UTCPD_T::VNDINIT 998 * Offset: 0x100 UTCPD Vendor Initial Register 999 * --------------------------------------------------------------------------------------------------- 1000 * |Bits |Field |Descriptions 1001 * | :----: | :----: | :---- | 1002 * |[6:4] |DVCAPDEF |Device Capability Default Setting 1003 * | | |Write the Register will update the value to Device_Cap.RoleSupport, ROLE_CONTROL and MESSAGE_HEADER_INFO register, please refer the following table 1004 * | | |(DevCap_DEF Table) 1005 * @var UTCPD_T::BMCTXBP 1006 * Offset: 0x104 UTCPD BMC TX Bit Period Register 1007 * --------------------------------------------------------------------------------------------------- 1008 * |Bits |Field |Descriptions 1009 * | :----: | :----: | :---- | 1010 * |[7:0] |BMCTXBP |BMC Tx bit period 1011 * | | |It's for BMC eye diagram. 1012 * | | |Example 12 MHz = 83.33ns. 1013 * | | |83.33ns x (39 + 1) = 3.33us. 1014 * @var UTCPD_T::BMCTXDU 1015 * Offset: 0x108 UTCPD BMC TX Duty Register 1016 * --------------------------------------------------------------------------------------------------- 1017 * |Bits |Field |Descriptions 1018 * | :----: | :----: | :---- | 1019 * |[6:0] |DUOFFS2 |BMC Tx duty offset parameter 2 1020 * | | |It's for BMC eye diagram. 1021 * | | |Offset count value. 1022 * | | |Example 12 MHz = 83.33ns. 1023 * |[7] |DUOFFS1 |BMC Tx duty offset parameter 1 1024 * | | |It's for BMC eye diagram. 1025 * | | |0: Increase duty offset? (+) 1026 * | | |1: Decrease duty offset? (-) 1027 * @var UTCPD_T::VCPSVOL 1028 * Offset: 0x10C VCONN Present Voltage Register 1029 * --------------------------------------------------------------------------------------------------- 1030 * |Bits |Field |Descriptions 1031 * | :----: | :----: | :---- | 1032 * |[9:0] |VCPSVOL |VCONN Present voltage 1033 * | | |Detect Voltage = 60h * 0.025V = 2.42V. 1034 * @var UTCPD_T::VCUV 1035 * Offset: 0x110 VCONN Under Voltage Register 1036 * --------------------------------------------------------------------------------------------------- 1037 * |Bits |Field |Descriptions 1038 * | :----: | :----: | :---- | 1039 * |[9:0] |VCUV |VCONN under voltage comparator 1040 * | | |Detect Voltage = 20h * 0.025V = 0.8V. 1041 * @var UTCPD_T::BMCSLICE 1042 * Offset: 0x118 UTCPD BMC SLICE Control Register 1043 * --------------------------------------------------------------------------------------------------- 1044 * |Bits |Field |Descriptions 1045 * | :----: | :----: | :---- | 1046 * |[1:0] |SLICEL |TX Slice Low Level Control 1047 * | | |Low level slice control (The LSB is 2mV.) 1048 * | | |00: 0.18V 1049 * | | |01: 0.2V 1050 * | | |10: 0.22V 1051 * | | |11: 0.24V (Default) 1052 * |[3:2] |SLICEH |TX Slice High Level Control 1053 * | | |High level slice control (The LSB is 2mV.) 1054 * | | |00: 0.84V (Default) 1055 * | | |01: 0.86V 1056 * | | |10: 0.88V 1057 * | | |11: 0.9V 1058 * |[6:4] |SLICEM |TX Slice Middle Level Control 1059 * | | |Middle level slice control (The LSB is 2mV.) 1060 * | | |000: 0.48V 1061 * | | |100: 0.56V (Default) 1062 * | | |111: 0.62V 1063 * |[10:8] |TRIMRD |TRIMRD 1064 * |[15:12] |TRIMRP |TRIMRP 1065 * |[18:16] |TRIMV1P1 |TRIMV1P1 1066 * |[22:20] |TRIMVB10 |Trim VBUS divided 10 1067 * |[26:24] |TRIMVB20 |Trim VBUS divided 20 1068 * |[31:28] |VTRIM |VTRIM 1069 * @var UTCPD_T::PHYCTL 1070 * Offset: 0x11C UTCPD PHY Power Control Register 1071 * --------------------------------------------------------------------------------------------------- 1072 * |Bits |Field |Descriptions 1073 * | :----: | :----: | :---- | 1074 * |[0] |PHYPWR |Analog PHY Power 1075 * | | |0: Power down PHY 1076 * | | |1: Enable PHY 1077 * | | |Analog PHY power default is off before UTCPD clock available 1078 * | | |Once UTCPD clock is on, the analog PHY power will be on as well. 1079 * | | |Turning off PHY power when…… 1080 * | | |1. 1081 * | | |2. 1082 * |[1] |DBCTL |Dead Battery control 1083 * | | |0: Dead Battery circuit control internal Rd/Rp. 1084 * | | |1: Role Control Register control internal Rd/Rp. 1085 * @var UTCPD_T::FRSRXCTL 1086 * Offset: 0x120 UTCPD CC Fast Swap RX Control Register 1087 * --------------------------------------------------------------------------------------------------- 1088 * |Bits |Field |Descriptions 1089 * | :----: | :----: | :---- | 1090 * |[0] |FRSTX |CC transmitter fast swap signal 1091 * | | |Pulse width: 85us 1092 * |[2] |FRSDVVB |CC receive fast swap and auto drive Source VBUS 1093 * | | |0: Disable 1094 * | | |1: Enable 1095 * |[3] |FRSRXEN |CC receive fast swap Rx Enable 1096 * | | |0: Disable 1097 * | | |1: Enable 1098 * @var UTCPD_T::VCVOL 1099 * Offset: 0x124 UTCPD VCONN Voltage Measurement Register 1100 * --------------------------------------------------------------------------------------------------- 1101 * |Bits |Field |Descriptions 1102 * | :----: | :----: | :---- | 1103 * |[9:0] |VCVOL |VCONN Voltage Measurement 1104 * | | |The LSB is 25mV 1105 * @var UTCPD_T::CLKINFO 1106 * Offset: 0x300 UTCPD Clock Information Register 1107 * --------------------------------------------------------------------------------------------------- 1108 * |Bits |Field |Descriptions 1109 * | :----: | :----: | :---- | 1110 * |[0] |ReadyFlag |RC32K domain ready flag Check if the register value is loaded to RC32K domain by reading this flag 1111 * | | |0 : The RC32K signal is not ready 1112 * | | |1 : The RC32K signal is ready 1113 * |[4] |WKEN |Wakeup enable 1114 * | | |0 : UTCPD wakeup function Disabled. 1115 * | | |1 : UTCPD wakeup function Enabled. 1116 */ 1117 __IO uint32_t VID; /*!< [0x0000] UTCPD Vendor ID Register */ 1118 __IO uint32_t PID; /*!< [0x0004] UTCPD Product ID Register */ 1119 __IO uint32_t DID; /*!< [0x0008] UTCPD Device ID Register */ 1120 __IO uint32_t TCREV; /*!< [0x000c] UTCPD USB Type C Revision Register */ 1121 __IO uint32_t PDREV; /*!< [0x0010] UTCPD USB PD Revision Register */ 1122 __IO uint32_t IS; /*!< [0x0014] UTCPD Interrupt Status Register */ 1123 __IO uint32_t IE; /*!< [0x0018] UTCPD Interrupt Enable Register */ 1124 __IO uint32_t PWRSTSIE; /*!< [0x001c] UTCPD Power Status Interrupt Enable Register */ 1125 __IO uint32_t FUTSTSIE; /*!< [0x0020] UTCPD Fault Status Interrupt Enable Register */ 1126 __IO uint32_t CTL; /*!< [0x0024] UTCPD Control Register */ 1127 __IO uint32_t PINPL; /*!< [0x0028] UTCPD Pin Polarity Control Register */ 1128 __IO uint32_t ROLCTL; /*!< [0x002c] UTCPD Role Control Register */ 1129 __IO uint32_t FUTCTL; /*!< [0x0030] UTCPD Fault Control Register */ 1130 __IO uint32_t PWRCTL; /*!< [0x0034] UTCPD Power Control Register */ 1131 __I uint32_t CCSTS; /*!< [0x0038] UTCPD CC Status Register */ 1132 __I uint32_t PWRSTS; /*!< [0x003c] UTCPD Power Status Register */ 1133 __I uint32_t FUTSTS; /*!< [0x0040] UTCPD Fault Status Register */ 1134 __IO uint32_t CMD; /*!< [0x0044] UTCPD Command Register */ 1135 __IO uint32_t DVCAP1; /*!< [0x0048] UTCPD Device Capabilities 1 Register */ 1136 __IO uint32_t DVCAP2; /*!< [0x004c] UTCPD Device Capabilities 2 Register */ 1137 __IO uint32_t MSHEAD; /*!< [0x0050] UTCPD Message Header Info Register */ 1138 __IO uint32_t DTRXEVNT; /*!< [0x0054] UTCPD Enable Detect RX Event Register */ 1139 __I uint32_t RXBCNT; /*!< [0x0058] UTCPD RX Byte Count Register */ 1140 __I uint32_t RXFTYPE; /*!< [0x005c] UTCPD Received Frame Type Register */ 1141 __I uint32_t RXHEAD; /*!< [0x0060] UTCPD Received Header Data Register */ 1142 __I uint32_t RESERVE0[3]; 1143 __I uint32_t RXDA0; /*!< [0x0070] UTCPD Received Data0 Register */ 1144 __I uint32_t RXDA1; /*!< [0x0074] UTCPD Received Data1 Register */ 1145 __I uint32_t RXDA2; /*!< [0x0078] UTCPD Received Data2 Register */ 1146 __I uint32_t RXDA3; /*!< [0x007c] UTCPD Received Data3 Register */ 1147 __I uint32_t RXDA4; /*!< [0x0080] UTCPD Received Data4 Register */ 1148 __I uint32_t RXDA5; /*!< [0x0084] UTCPD Received Data5 Register */ 1149 __I uint32_t RXDA6; /*!< [0x0088] UTCPD Received Data6 Register */ 1150 __I uint32_t RESERVE1[1]; 1151 __IO uint32_t TXCTL; /*!< [0x0090] UTCPD TX Control Register */ 1152 __IO uint32_t TXBCNT; /*!< [0x0094] UTCPD TX Byte Count Register */ 1153 __IO uint32_t TXHEAD; /*!< [0x0098] UTCPD TX Header Data Register */ 1154 __I uint32_t RESERVE2[1]; 1155 __IO uint32_t TXDA0; /*!< [0x00a0] UTCPD Transmit Data0 Register */ 1156 __IO uint32_t TXDA1; /*!< [0x00a4] UTCPD Transmit Data1 Register */ 1157 __IO uint32_t TXDA2; /*!< [0x00a8] UTCPD Transmit Data2 Register */ 1158 __IO uint32_t TXDA3; /*!< [0x00ac] UTCPD Transmit Data3 Register */ 1159 __IO uint32_t TXDA4; /*!< [0x00b0] UTCPD Transmit Data4 Register */ 1160 __IO uint32_t TXDA5; /*!< [0x00b4] UTCPD Transmit Data5 Register */ 1161 __IO uint32_t TXDA6; /*!< [0x00b8] UTCPD Transmit Data6 Register */ 1162 __I uint32_t RESERVE3[1]; 1163 __IO uint32_t VBVOL; /*!< [0x00c0] UTCPD VBUS Voltage Register */ 1164 __IO uint32_t SKVBDCTH; /*!< [0x00c4] UTCPD VBUS Sink disconnect threshold Register */ 1165 __IO uint32_t SPDGTH; /*!< [0x00c8] UTCPD VBUS Stop Discharge threshold Register */ 1166 __IO uint32_t VBAMH; /*!< [0x00cc] UTCPD VBUS voltage high alarm threshold Register */ 1167 __IO uint32_t VBAML; /*!< [0x00d0] UTCPD VBUS voltage low alarm threshold Register */ 1168 __IO uint32_t VNDIS; /*!< [0x00d4] UTCPD Vendor defined Interrupt Status Register */ 1169 __IO uint32_t VNDIE; /*!< [0x00d8] UTCPD Vendor defined Interrupt Enable Register */ 1170 __IO uint32_t MUXSEL; /*!< [0x00dc] UTCPD Mux Select Register */ 1171 __IO uint32_t VCDGCTL; /*!< [0x00e0] UTCPD VCONN Discharge Control Register */ 1172 __IO uint32_t PHYSLEW; /*!< [0x00e4] UTCPD PHY Slew Rate Control Register */ 1173 __IO uint32_t ADGTM; /*!< [0x00e8] UTCPD Auto Discharge Time Register */ 1174 __IO uint32_t VSAFE0V; /*!< [0x00ec] UTCPD Auto Discharge VSAFE0V Register */ 1175 __IO uint32_t VSAFE5V; /*!< [0x00f0] UTCPD VSAFE5V Register */ 1176 __IO uint32_t RATIO; /*!< [0x00f4] UTCPD DRP Toggle Ratio Register */ 1177 __IO uint32_t INTFRAME; /*!< [0x00f8] UTCPD Inter-Frame Time Register */ 1178 __IO uint32_t VBOVTH; /*!< [0x00fc] UTCPD VBUS Over Voltage Threshold Register */ 1179 __IO uint32_t VNDINIT; /*!< [0x0100] UTCPD Vendor Initial Register */ 1180 __IO uint32_t BMCTXBP; /*!< [0x0104] UTCPD BMC TX Bit Period Register */ 1181 __IO uint32_t BMCTXDU; /*!< [0x0108] UTCPD BMC TX Duty Register */ 1182 __IO uint32_t VCPSVOL; /*!< [0x010c] VCONN Present Voltage Register */ 1183 __IO uint32_t VCUV; /*!< [0x0110] VCONN Under Voltage Register */ 1184 __I uint32_t RESERVE4[1]; 1185 __IO uint32_t BMCSLICE; /*!< [0x0118] UTCPD BMC SLICE Control Register */ 1186 __IO uint32_t PHYCTL; /*!< [0x011c] UTCPD PHY Power Control Register */ 1187 __IO uint32_t FRSRXCTL; /*!< [0x0120] UTCPD CC Fast Swap RX Control Register */ 1188 __I uint32_t VCVOL; /*!< [0x0124] UTCPD VCONN Voltage Measurement Register */ 1189 __I uint32_t RESERVE5[118]; 1190 __IO uint32_t CLKINFO; /*!< [0x0300] UTCPD Clock Information Register */ 1191 __I uint32_t RESERVE6[1]; 1192 __IO uint32_t TEST2; /*!< [0x0300] UTCPD Test2 Register */ 1193 1194 } UTCPD_T; 1195 1196 /** 1197 @addtogroup UTCPD_CONST UTCPD Bit Field Definition 1198 Constant Definitions for UTCPD Controller 1199 @{ */ 1200 1201 #define UTCPD_VID_VID_Pos (0) /*!< UTCPD_T::VID: VID Position */ 1202 #define UTCPD_VID_VID_Msk (0xfffful << UTCPD_VID_VID_Pos) /*!< UTCPD_T::VID: VID Mask */ 1203 1204 #define UTCPD_PID_PID_Pos (0) /*!< UTCPD_T::PID: PID Position */ 1205 #define UTCPD_PID_PID_Msk (0xfffful << UTCPD_PID_PID_Pos) /*!< UTCPD_T::PID: PID Mask */ 1206 1207 #define UTCPD_DID_DID_Pos (0) /*!< UTCPD_T::DID: DID Position */ 1208 #define UTCPD_DID_DID_Msk (0xfffful << UTCPD_DID_DID_Pos) /*!< UTCPD_T::DID: DID Mask */ 1209 1210 #define UTCPD_TCREV_TCREV_Pos (0) /*!< UTCPD_T::TCREV: TCREV Position */ 1211 #define UTCPD_TCREV_TCREV_Msk (0xfful << UTCPD_TCREV_TCREV_Pos) /*!< UTCPD_T::TCREV: TCREV Mask */ 1212 1213 #define UTCPD_PDREV_PDVER_Pos (0) /*!< UTCPD_T::PDREV: PDVER Position */ 1214 #define UTCPD_PDREV_PDVER_Msk (0xfful << UTCPD_PDREV_PDVER_Pos) /*!< UTCPD_T::PDREV: PDVER Mask */ 1215 1216 #define UTCPD_PDREV_PDREV_Pos (8) /*!< UTCPD_T::PDREV: PDREV Position */ 1217 #define UTCPD_PDREV_PDREV_Msk (0xfful << UTCPD_PDREV_PDREV_Pos) /*!< UTCPD_T::PDREV: PDREV Mask */ 1218 1219 #define UTCPD_IS_CCSCHIS_Pos (0) /*!< UTCPD_T::IS: CCSCHIS Position */ 1220 #define UTCPD_IS_CCSCHIS_Msk (0x1ul << UTCPD_IS_CCSCHIS_Pos) /*!< UTCPD_T::IS: CCSCHIS Mask */ 1221 1222 #define UTCPD_IS_PWRSCHIS_Pos (1) /*!< UTCPD_T::IS: PWRSCHIS Position */ 1223 #define UTCPD_IS_PWRSCHIS_Msk (0x1ul << UTCPD_IS_PWRSCHIS_Pos) /*!< UTCPD_T::IS: PWRSCHIS Mask */ 1224 1225 #define UTCPD_IS_RXSOPIS_Pos (2) /*!< UTCPD_T::IS: RXSOPIS Position */ 1226 #define UTCPD_IS_RXSOPIS_Msk (0x1ul << UTCPD_IS_RXSOPIS_Pos) /*!< UTCPD_T::IS: RXSOPIS Mask */ 1227 1228 #define UTCPD_IS_RXHRSTIS_Pos (3) /*!< UTCPD_T::IS: RXHRSTIS Position */ 1229 #define UTCPD_IS_RXHRSTIS_Msk (0x1ul << UTCPD_IS_RXHRSTIS_Pos) /*!< UTCPD_T::IS: RXHRSTIS Mask */ 1230 1231 #define UTCPD_IS_TXFALIS_Pos (4) /*!< UTCPD_T::IS: TXFALIS Position */ 1232 #define UTCPD_IS_TXFALIS_Msk (0x1ul << UTCPD_IS_TXFALIS_Pos) /*!< UTCPD_T::IS: TXFALIS Mask */ 1233 1234 #define UTCPD_IS_TXDCUDIS_Pos (5) /*!< UTCPD_T::IS: TXDCUDIS Position */ 1235 #define UTCPD_IS_TXDCUDIS_Msk (0x1ul << UTCPD_IS_TXDCUDIS_Pos) /*!< UTCPD_T::IS: TXDCUDIS Mask */ 1236 1237 #define UTCPD_IS_TXOKIS_Pos (6) /*!< UTCPD_T::IS: TXOKIS Position */ 1238 #define UTCPD_IS_TXOKIS_Msk (0x1ul << UTCPD_IS_TXOKIS_Pos) /*!< UTCPD_T::IS: TXOKIS Mask */ 1239 1240 #define UTCPD_IS_VBAMHIS_Pos (7) /*!< UTCPD_T::IS: VBAMHIS Position */ 1241 #define UTCPD_IS_VBAMHIS_Msk (0x1ul << UTCPD_IS_VBAMHIS_Pos) /*!< UTCPD_T::IS: VBAMHIS Mask */ 1242 1243 #define UTCPD_IS_VBAMLIS_Pos (8) /*!< UTCPD_T::IS: VBAMLIS Position */ 1244 #define UTCPD_IS_VBAMLIS_Msk (0x1ul << UTCPD_IS_VBAMLIS_Pos) /*!< UTCPD_T::IS: VBAMLIS Mask */ 1245 1246 #define UTCPD_IS_FUTIS_Pos (9) /*!< UTCPD_T::IS: FUTIS Position */ 1247 #define UTCPD_IS_FUTIS_Msk (0x1ul << UTCPD_IS_FUTIS_Pos) /*!< UTCPD_T::IS: FUTIS Mask */ 1248 1249 #define UTCPD_IS_RXOFIS_Pos (10) /*!< UTCPD_T::IS: RXOFIS Position */ 1250 #define UTCPD_IS_RXOFIS_Msk (0x1ul << UTCPD_IS_RXOFIS_Pos) /*!< UTCPD_T::IS: RXOFIS Mask */ 1251 1252 #define UTCPD_IS_SKDCDTIS_Pos (11) /*!< UTCPD_T::IS: SKDCDTIS Position */ 1253 #define UTCPD_IS_SKDCDTIS_Msk (0x1ul << UTCPD_IS_SKDCDTIS_Pos) /*!< UTCPD_T::IS: SKDCDTIS Mask */ 1254 1255 #define UTCPD_IS_VNDIS_Pos (15) /*!< UTCPD_T::IS: VNDIS Position */ 1256 #define UTCPD_IS_VNDIS_Msk (0x1ul << UTCPD_IS_VNDIS_Pos) /*!< UTCPD_T::IS: VNDIS Mask */ 1257 1258 #define UTCPD_IE_CCSCHIE_Pos (0) /*!< UTCPD_T::IE: CCSCHIE Position */ 1259 #define UTCPD_IE_CCSCHIE_Msk (0x1ul << UTCPD_IE_CCSCHIE_Pos) /*!< UTCPD_T::IE: CCSCHIE Mask */ 1260 1261 #define UTCPD_IE_PWRSCHIE_Pos (1) /*!< UTCPD_T::IE: PWRSCHIE Position */ 1262 #define UTCPD_IE_PWRSCHIE_Msk (0x1ul << UTCPD_IE_PWRSCHIE_Pos) /*!< UTCPD_T::IE: PWRSCHIE Mask */ 1263 1264 #define UTCPD_IE_RXSOPIE_Pos (2) /*!< UTCPD_T::IE: RXSOPIE Position */ 1265 #define UTCPD_IE_RXSOPIE_Msk (0x1ul << UTCPD_IE_RXSOPIE_Pos) /*!< UTCPD_T::IE: RXSOPIE Mask */ 1266 1267 #define UTCPD_IE_RXHRSTIE_Pos (3) /*!< UTCPD_T::IE: RXHRSTIE Position */ 1268 #define UTCPD_IE_RXHRSTIE_Msk (0x1ul << UTCPD_IE_RXHRSTIE_Pos) /*!< UTCPD_T::IE: RXHRSTIE Mask */ 1269 1270 #define UTCPD_IE_TXFAILIE_Pos (4) /*!< UTCPD_T::IE: TXFAILIE Position */ 1271 #define UTCPD_IE_TXFAILIE_Msk (0x1ul << UTCPD_IE_TXFAILIE_Pos) /*!< UTCPD_T::IE: TXFAILIE Mask */ 1272 1273 #define UTCPD_IE_TXDCUDIE_Pos (5) /*!< UTCPD_T::IE: TXDCUDIE Position */ 1274 #define UTCPD_IE_TXDCUDIE_Msk (0x1ul << UTCPD_IE_TXDCUDIE_Pos) /*!< UTCPD_T::IE: TXDCUDIE Mask */ 1275 1276 #define UTCPD_IE_TXOKIE_Pos (6) /*!< UTCPD_T::IE: TXOKIE Position */ 1277 #define UTCPD_IE_TXOKIE_Msk (0x1ul << UTCPD_IE_TXOKIE_Pos) /*!< UTCPD_T::IE: TXOKIE Mask */ 1278 1279 #define UTCPD_IE_VBAMHIE_Pos (7) /*!< UTCPD_T::IE: VBAMHIE Position */ 1280 #define UTCPD_IE_VBAMHIE_Msk (0x1ul << UTCPD_IE_VBAMHIE_Pos) /*!< UTCPD_T::IE: VBAMHIE Mask */ 1281 1282 #define UTCPD_IE_VBAMLIE_Pos (8) /*!< UTCPD_T::IE: VBAMLIE Position */ 1283 #define UTCPD_IE_VBAMLIE_Msk (0x1ul << UTCPD_IE_VBAMLIE_Pos) /*!< UTCPD_T::IE: VBAMLIE Mask */ 1284 1285 #define UTCPD_IE_FUTIE_Pos (9) /*!< UTCPD_T::IE: FUTIE Position */ 1286 #define UTCPD_IE_FUTIE_Msk (0x1ul << UTCPD_IE_FUTIE_Pos) /*!< UTCPD_T::IE: FUTIE Mask */ 1287 1288 #define UTCPD_IE_RXOFIE_Pos (10) /*!< UTCPD_T::IE: RXOFIE Position */ 1289 #define UTCPD_IE_RXOFIE_Msk (0x1ul << UTCPD_IE_RXOFIE_Pos) /*!< UTCPD_T::IE: RXOFIE Mask */ 1290 1291 #define UTCPD_IE_SKDCDTIE_Pos (11) /*!< UTCPD_T::IE: SKDCDTIE Position */ 1292 #define UTCPD_IE_SKDCDTIE_Msk (0x1ul << UTCPD_IE_SKDCDTIE_Pos) /*!< UTCPD_T::IE: SKDCDTIE Mask */ 1293 1294 #define UTCPD_IE_VNDIE_Pos (15) /*!< UTCPD_T::IE: VNDIE Position */ 1295 #define UTCPD_IE_VNDIE_Msk (0x1ul << UTCPD_IE_VNDIE_Pos) /*!< UTCPD_T::IE: VNDIE Mask */ 1296 1297 #define UTCPD_PWRSTSIE_SKVBIE_Pos (0) /*!< UTCPD_T::PWRSTSIE: SKVBIE Position */ 1298 #define UTCPD_PWRSTSIE_SKVBIE_Msk (0x1ul << UTCPD_PWRSTSIE_SKVBIE_Pos) /*!< UTCPD_T::PWRSTSIE: SKVBIE Mask */ 1299 1300 #define UTCPD_PWRSTSIE_VCPSIE_Pos (1) /*!< UTCPD_T::PWRSTSIE: VCPSIE Position */ 1301 #define UTCPD_PWRSTSIE_VCPSIE_Msk (0x1ul << UTCPD_PWRSTSIE_VCPSIE_Pos) /*!< UTCPD_T::PWRSTSIE: VCPSIE Mask */ 1302 1303 #define UTCPD_PWRSTSIE_VBPSIE_Pos (2) /*!< UTCPD_T::PWRSTSIE: VBPSIE Position */ 1304 #define UTCPD_PWRSTSIE_VBPSIE_Msk (0x1ul << UTCPD_PWRSTSIE_VBPSIE_Pos) /*!< UTCPD_T::PWRSTSIE: VBPSIE Mask */ 1305 1306 #define UTCPD_PWRSTSIE_VBDTDGIE_Pos (3) /*!< UTCPD_T::PWRSTSIE: VBDTDGIE Position */ 1307 #define UTCPD_PWRSTSIE_VBDTDGIE_Msk (0x1ul << UTCPD_PWRSTSIE_VBDTDGIE_Pos) /*!< UTCPD_T::PWRSTSIE: VBDTDGIE Mask */ 1308 1309 #define UTCPD_PWRSTSIE_SRVBIE_Pos (4) /*!< UTCPD_T::PWRSTSIE: SRVBIE Position */ 1310 #define UTCPD_PWRSTSIE_SRVBIE_Msk (0x1ul << UTCPD_PWRSTSIE_SRVBIE_Pos) /*!< UTCPD_T::PWRSTSIE: SRVBIE Mask */ 1311 1312 #define UTCPD_PWRSTSIE_SRHVIE_Pos (5) /*!< UTCPD_T::PWRSTSIE: SRHVIE Position */ 1313 #define UTCPD_PWRSTSIE_SRHVIE_Msk (0x1ul << UTCPD_PWRSTSIE_SRHVIE_Pos) /*!< UTCPD_T::PWRSTSIE: SRHVIE Mask */ 1314 1315 #define UTCPD_PWRSTSIE_DACONIE_Pos (7) /*!< UTCPD_T::PWRSTSIE: DACONIE Position */ 1316 #define UTCPD_PWRSTSIE_DACONIE_Msk (0x1ul << UTCPD_PWRSTSIE_DACONIE_Pos) /*!< UTCPD_T::PWRSTSIE: DACONIE Mask */ 1317 1318 #define UTCPD_FUTSTSIE_VCOCIE_Pos (1) /*!< UTCPD_T::FUTSTSIE: VCOCIE Position */ 1319 #define UTCPD_FUTSTSIE_VCOCIE_Msk (0x1ul << UTCPD_FUTSTSIE_VCOCIE_Pos) /*!< UTCPD_T::FUTSTSIE: VCOCIE Mask */ 1320 1321 #define UTCPD_FUTSTSIE_VBOVIE_Pos (2) /*!< UTCPD_T::FUTSTSIE: VBOVIE Position */ 1322 #define UTCPD_FUTSTSIE_VBOVIE_Msk (0x1ul << UTCPD_FUTSTSIE_VBOVIE_Pos) /*!< UTCPD_T::FUTSTSIE: VBOVIE Mask */ 1323 1324 #define UTCPD_FUTSTSIE_VBOCIE_Pos (3) /*!< UTCPD_T::FUTSTSIE: VBOCIE Position */ 1325 #define UTCPD_FUTSTSIE_VBOCIE_Msk (0x1ul << UTCPD_FUTSTSIE_VBOCIE_Pos) /*!< UTCPD_T::FUTSTSIE: VBOCIE Mask */ 1326 1327 #define UTCPD_FUTSTSIE_FDGFALIE_Pos (4) /*!< UTCPD_T::FUTSTSIE: FDGFALIE Position */ 1328 #define UTCPD_FUTSTSIE_FDGFALIE_Msk (0x1ul << UTCPD_FUTSTSIE_FDGFALIE_Pos) /*!< UTCPD_T::FUTSTSIE: FDGFALIE Mask */ 1329 1330 #define UTCPD_FUTSTSIE_ADGFALIE_Pos (5) /*!< UTCPD_T::FUTSTSIE: ADGFALIE Position */ 1331 #define UTCPD_FUTSTSIE_ADGFALIE_Msk (0x1ul << UTCPD_FUTSTSIE_ADGFALIE_Pos) /*!< UTCPD_T::FUTSTSIE: ADGFALIE Mask */ 1332 1333 #define UTCPD_FUTSTSIE_FOFFVBIE_Pos (6) /*!< UTCPD_T::FUTSTSIE: FOFFVBIE Position */ 1334 #define UTCPD_FUTSTSIE_FOFFVBIE_Msk (0x1ul << UTCPD_FUTSTSIE_FOFFVBIE_Pos) /*!< UTCPD_T::FUTSTSIE: FOFFVBIE Mask */ 1335 1336 #define UTCPD_CTL_ORIENT_Pos (0) /*!< UTCPD_T::CTL: ORIENT Position */ 1337 #define UTCPD_CTL_ORIENT_Msk (0x1ul << UTCPD_CTL_ORIENT_Pos) /*!< UTCPD_T::CTL: ORIENT Mask */ 1338 1339 #define UTCPD_CTL_BISTEN_Pos (1) /*!< UTCPD_T::CTL: BISTEN Position */ 1340 #define UTCPD_CTL_BISTEN_Msk (0x1ul << UTCPD_CTL_BISTEN_Pos) /*!< UTCPD_T::CTL: BISTEN Mask */ 1341 1342 #define UTCPD_PINPL_VBSRENPL_Pos (0) /*!< UTCPD_T::PINPL: VBSRENPL Position */ 1343 #define UTCPD_PINPL_VBSRENPL_Msk (0x1ul << UTCPD_PINPL_VBSRENPL_Pos) /*!< UTCPD_T::PINPL: VBSRENPL Mask */ 1344 1345 #define UTCPD_PINPL_VBSKENPL_Pos (1) /*!< UTCPD_T::PINPL: VBSKENPL Position */ 1346 #define UTCPD_PINPL_VBSKENPL_Msk (0x1ul << UTCPD_PINPL_VBSKENPL_Pos) /*!< UTCPD_T::PINPL: VBSKENPL Mask */ 1347 1348 #define UTCPD_PINPL_VBDGENPL_Pos (2) /*!< UTCPD_T::PINPL: VBDGENPL Position */ 1349 #define UTCPD_PINPL_VBDGENPL_Msk (0x1ul << UTCPD_PINPL_VBDGENPL_Pos) /*!< UTCPD_T::PINPL: VBDGENPL Mask */ 1350 1351 #define UTCPD_PINPL_TXFRSPL_Pos (3) /*!< UTCPD_T::PINPL: TXFRSPL Position */ 1352 #define UTCPD_PINPL_TXFRSPL_Msk (0x1ul << UTCPD_PINPL_TXFRSPL_Pos) /*!< UTCPD_T::PINPL: TXFRSPL Mask */ 1353 1354 #define UTCPD_PINPL_FOFFVBPL_Pos (4) /*!< UTCPD_T::PINPL: FOFFVBPL Position */ 1355 #define UTCPD_PINPL_FOFFVBPL_Msk (0x1ul << UTCPD_PINPL_FOFFVBPL_Pos) /*!< UTCPD_T::PINPL: FOFFVBPL Mask */ 1356 1357 #define UTCPD_PINPL_VBOCPL_Pos (5) /*!< UTCPD_T::PINPL: VBOCPL Position */ 1358 #define UTCPD_PINPL_VBOCPL_Msk (0x1ul << UTCPD_PINPL_VBOCPL_Pos) /*!< UTCPD_T::PINPL: VBOCPL Mask */ 1359 1360 #define UTCPD_PINPL_VCENPL_Pos (8) /*!< UTCPD_T::PINPL: VCENPL Position */ 1361 #define UTCPD_PINPL_VCENPL_Msk (0x1ul << UTCPD_PINPL_VCENPL_Pos) /*!< UTCPD_T::PINPL: VCENPL Mask */ 1362 1363 #define UTCPD_PINPL_VCDGENPL_Pos (9) /*!< UTCPD_T::PINPL: VCDGENPL Position */ 1364 #define UTCPD_PINPL_VCDGENPL_Msk (0x1ul << UTCPD_PINPL_VCDGENPL_Pos) /*!< UTCPD_T::PINPL: VCDGENPL Mask */ 1365 1366 #define UTCPD_PINPL_VCOCPL_Pos (10) /*!< UTCPD_T::PINPL: VCOCPL Position */ 1367 #define UTCPD_PINPL_VCOCPL_Msk (0x1ul << UTCPD_PINPL_VCOCPL_Pos) /*!< UTCPD_T::PINPL: VCOCPL Mask */ 1368 1369 #define UTCPD_ROLCTL_CC1_Pos (0) /*!< UTCPD_T::ROLCTL: CC1 Position */ 1370 #define UTCPD_ROLCTL_CC1_Msk (0x3ul << UTCPD_ROLCTL_CC1_Pos) /*!< UTCPD_T::ROLCTL: CC1 Mask */ 1371 1372 #define UTCPD_ROLCTL_CC2_Pos (2) /*!< UTCPD_T::ROLCTL: CC2 Position */ 1373 #define UTCPD_ROLCTL_CC2_Msk (0x3ul << UTCPD_ROLCTL_CC2_Pos) /*!< UTCPD_T::ROLCTL: CC2 Mask */ 1374 1375 #define UTCPD_ROLCTL_RPVALUE_Pos (4) /*!< UTCPD_T::ROLCTL: RPVALUE Position */ 1376 #define UTCPD_ROLCTL_RPVALUE_Msk (0x3ul << UTCPD_ROLCTL_RPVALUE_Pos) /*!< UTCPD_T::ROLCTL: RPVALUE Mask */ 1377 1378 #define UTCPD_ROLCTL_DRP_Pos (6) /*!< UTCPD_T::ROLCTL: DRP Position */ 1379 #define UTCPD_ROLCTL_DRP_Msk (0x1ul << UTCPD_ROLCTL_DRP_Pos) /*!< UTCPD_T::ROLCTL: DRP Mask */ 1380 1381 #define UTCPD_FUTCTL_VCOCDTDS_Pos (0) /*!< UTCPD_T::FUTCTL: VCOCDTDS Position */ 1382 #define UTCPD_FUTCTL_VCOCDTDS_Msk (0x1ul << UTCPD_FUTCTL_VCOCDTDS_Pos) /*!< UTCPD_T::FUTCTL: VCOCDTDS Mask */ 1383 1384 #define UTCPD_FUTCTL_VBOVDTDS_Pos (1) /*!< UTCPD_T::FUTCTL: VBOVDTDS Position */ 1385 #define UTCPD_FUTCTL_VBOVDTDS_Msk (0x1ul << UTCPD_FUTCTL_VBOVDTDS_Pos) /*!< UTCPD_T::FUTCTL: VBOVDTDS Mask */ 1386 1387 #define UTCPD_FUTCTL_VBOCDTDS_Pos (2) /*!< UTCPD_T::FUTCTL: VBOCDTDS Position */ 1388 #define UTCPD_FUTCTL_VBOCDTDS_Msk (0x1ul << UTCPD_FUTCTL_VBOCDTDS_Pos) /*!< UTCPD_T::FUTCTL: VBOCDTDS Mask */ 1389 1390 #define UTCPD_FUTCTL_VBDGTMDS_Pos (3) /*!< UTCPD_T::FUTCTL: VBDGTMDS Position */ 1391 #define UTCPD_FUTCTL_VBDGTMDS_Msk (0x1ul << UTCPD_FUTCTL_VBDGTMDS_Pos) /*!< UTCPD_T::FUTCTL: VBDGTMDS Mask */ 1392 1393 #define UTCPD_FUTCTL_FOFFVBDS_Pos (4) /*!< UTCPD_T::FUTCTL: FOFFVBDS Position */ 1394 #define UTCPD_FUTCTL_FOFFVBDS_Msk (0x1ul << UTCPD_FUTCTL_FOFFVBDS_Pos) /*!< UTCPD_T::FUTCTL: FOFFVBDS Mask */ 1395 1396 #define UTCPD_PWRCTL_VCEN_Pos (0) /*!< UTCPD_T::PWRCTL: VCEN Position */ 1397 #define UTCPD_PWRCTL_VCEN_Msk (0x1ul << UTCPD_PWRCTL_VCEN_Pos) /*!< UTCPD_T::PWRCTL: VCEN Mask */ 1398 1399 #define UTCPD_PWRCTL_VCPWR_Pos (1) /*!< UTCPD_T::PWRCTL: VCPWR Position */ 1400 #define UTCPD_PWRCTL_VCPWR_Msk (0x1ul << UTCPD_PWRCTL_VCPWR_Pos) /*!< UTCPD_T::PWRCTL: VCPWR Mask */ 1401 1402 #define UTCPD_PWRCTL_FDGEN_Pos (2) /*!< UTCPD_T::PWRCTL: FDGEN Position */ 1403 #define UTCPD_PWRCTL_FDGEN_Msk (0x1ul << UTCPD_PWRCTL_FDGEN_Pos) /*!< UTCPD_T::PWRCTL: FDGEN Mask */ 1404 1405 #define UTCPD_PWRCTL_BDGEN_Pos (3) /*!< UTCPD_T::PWRCTL: BDGEN Position */ 1406 #define UTCPD_PWRCTL_BDGEN_Msk (0x1ul << UTCPD_PWRCTL_BDGEN_Pos) /*!< UTCPD_T::PWRCTL: BDGEN Mask */ 1407 1408 #define UTCPD_PWRCTL_ADGDC_Pos (4) /*!< UTCPD_T::PWRCTL: ADGDC Position */ 1409 #define UTCPD_PWRCTL_ADGDC_Msk (0x1ul << UTCPD_PWRCTL_ADGDC_Pos) /*!< UTCPD_T::PWRCTL: ADGDC Mask */ 1410 1411 #define UTCPD_PWRCTL_DSVBAM_Pos (5) /*!< UTCPD_T::PWRCTL: DSVBAM Position */ 1412 #define UTCPD_PWRCTL_DSVBAM_Msk (0x1ul << UTCPD_PWRCTL_DSVBAM_Pos) /*!< UTCPD_T::PWRCTL: DSVBAM Mask */ 1413 1414 #define UTCPD_PWRCTL_VBMONI_Pos (6) /*!< UTCPD_T::PWRCTL: VBMONI Position */ 1415 #define UTCPD_PWRCTL_VBMONI_Msk (0x1ul << UTCPD_PWRCTL_VBMONI_Pos) /*!< UTCPD_T::PWRCTL: VBMONI Mask */ 1416 1417 #define UTCPD_CCSTS_CC1STATE_Pos (0) /*!< UTCPD_T::CCSTS: CC1STATE Position */ 1418 #define UTCPD_CCSTS_CC1STATE_Msk (0x3ul << UTCPD_CCSTS_CC1STATE_Pos) /*!< UTCPD_T::CCSTS: CC1STATE Mask */ 1419 1420 #define UTCPD_CCSTS_CC2STATE_Pos (2) /*!< UTCPD_T::CCSTS: CC2STATE Position */ 1421 #define UTCPD_CCSTS_CC2STATE_Msk (0x3ul << UTCPD_CCSTS_CC2STATE_Pos) /*!< UTCPD_T::CCSTS: CC2STATE Mask */ 1422 1423 #define UTCPD_CCSTS_CONRLT_Pos (4) /*!< UTCPD_T::CCSTS: CONRLT Position */ 1424 #define UTCPD_CCSTS_CONRLT_Msk (0x1ul << UTCPD_CCSTS_CONRLT_Pos) /*!< UTCPD_T::CCSTS: CONRLT Mask */ 1425 1426 #define UTCPD_CCSTS_LK4CONN_Pos (5) /*!< UTCPD_T::CCSTS: LK4CONN Position */ 1427 #define UTCPD_CCSTS_LK4CONN_Msk (0x1ul << UTCPD_CCSTS_LK4CONN_Pos) /*!< UTCPD_T::CCSTS: LK4CONN Mask */ 1428 1429 #define UTCPD_PWRSTS_SKVB_Pos (0) /*!< UTCPD_T::PWRSTS: SKVB Position */ 1430 #define UTCPD_PWRSTS_SKVB_Msk (0x1ul << UTCPD_PWRSTS_SKVB_Pos) /*!< UTCPD_T::PWRSTS: SKVB Mask */ 1431 1432 #define UTCPD_PWRSTS_VCPS_Pos (1) /*!< UTCPD_T::PWRSTS: VCPS Position */ 1433 #define UTCPD_PWRSTS_VCPS_Msk (0x1ul << UTCPD_PWRSTS_VCPS_Pos) /*!< UTCPD_T::PWRSTS: VCPS Mask */ 1434 1435 #define UTCPD_PWRSTS_VBPS_Pos (2) /*!< UTCPD_T::PWRSTS: VBPS Position */ 1436 #define UTCPD_PWRSTS_VBPS_Msk (0x1ul << UTCPD_PWRSTS_VBPS_Pos) /*!< UTCPD_T::PWRSTS: VBPS Mask */ 1437 1438 #define UTCPD_PWRSTS_VBPSDTEN_Pos (3) /*!< UTCPD_T::PWRSTS: VBPSDTEN Position */ 1439 #define UTCPD_PWRSTS_VBPSDTEN_Msk (0x1ul << UTCPD_PWRSTS_VBPSDTEN_Pos) /*!< UTCPD_T::PWRSTS: VBPSDTEN Mask */ 1440 1441 #define UTCPD_PWRSTS_SRVB_Pos (4) /*!< UTCPD_T::PWRSTS: SRVB Position */ 1442 #define UTCPD_PWRSTS_SRVB_Msk (0x1ul << UTCPD_PWRSTS_SRVB_Pos) /*!< UTCPD_T::PWRSTS: SRVB Mask */ 1443 1444 #define UTCPD_PWRSTS_SRHV_Pos (5) /*!< UTCPD_T::PWRSTS: SRHV Position */ 1445 #define UTCPD_PWRSTS_SRHV_Msk (0x1ul << UTCPD_PWRSTS_SRHV_Pos) /*!< UTCPD_T::PWRSTS: SRHV Mask */ 1446 1447 #define UTCPD_PWRSTS_DACON_Pos (7) /*!< UTCPD_T::PWRSTS: DACON Position */ 1448 #define UTCPD_PWRSTS_DACON_Msk (0x1ul << UTCPD_PWRSTS_DACON_Pos) /*!< UTCPD_T::PWRSTS: DACON Mask */ 1449 1450 #define UTCPD_FUTSTS_VCOCFUT_Pos (1) /*!< UTCPD_T::FUTSTS: VCOCFUT Position */ 1451 #define UTCPD_FUTSTS_VCOCFUT_Msk (0x1ul << UTCPD_FUTSTS_VCOCFUT_Pos) /*!< UTCPD_T::FUTSTS: VCOCFUT Mask */ 1452 1453 #define UTCPD_FUTSTS_VBOVFUT_Pos (2) /*!< UTCPD_T::FUTSTS: VBOVFUT Position */ 1454 #define UTCPD_FUTSTS_VBOVFUT_Msk (0x1ul << UTCPD_FUTSTS_VBOVFUT_Pos) /*!< UTCPD_T::FUTSTS: VBOVFUT Mask */ 1455 1456 #define UTCPD_FUTSTS_VBOCFUT_Pos (3) /*!< UTCPD_T::FUTSTS: VBOCFUT Position */ 1457 #define UTCPD_FUTSTS_VBOCFUT_Msk (0x1ul << UTCPD_FUTSTS_VBOCFUT_Pos) /*!< UTCPD_T::FUTSTS: VBOCFUT Mask */ 1458 1459 #define UTCPD_FUTSTS_FDGFAL_Pos (4) /*!< UTCPD_T::FUTSTS: FDGFAL Position */ 1460 #define UTCPD_FUTSTS_FDGFAL_Msk (0x1ul << UTCPD_FUTSTS_FDGFAL_Pos) /*!< UTCPD_T::FUTSTS: FDGFAL Mask */ 1461 1462 #define UTCPD_FUTSTS_ADGFAL_Pos (5) /*!< UTCPD_T::FUTSTS: ADGFAL Position */ 1463 #define UTCPD_FUTSTS_ADGFAL_Msk (0x1ul << UTCPD_FUTSTS_ADGFAL_Pos) /*!< UTCPD_T::FUTSTS: ADGFAL Mask */ 1464 1465 #define UTCPD_FUTSTS_FOFFVB_Pos (6) /*!< UTCPD_T::FUTSTS: FOFFVB Position */ 1466 #define UTCPD_FUTSTS_FOFFVB_Msk (0x1ul << UTCPD_FUTSTS_FOFFVB_Pos) /*!< UTCPD_T::FUTSTS: FOFFVB Mask */ 1467 1468 #define UTCPD_CMD_CMD_Pos (0) /*!< UTCPD_T::CMD: CMD Position */ 1469 #define UTCPD_CMD_CMD_Msk (0xfful << UTCPD_CMD_CMD_Pos) /*!< UTCPD_T::CMD: CMD Mask */ 1470 1471 #define UTCPD_DVCAP1_CPSRVB_Pos (0) /*!< UTCPD_T::DVCAP1: CPSRVB Position */ 1472 #define UTCPD_DVCAP1_CPSRVB_Msk (0x1ul << UTCPD_DVCAP1_CPSRVB_Pos) /*!< UTCPD_T::DVCAP1: CPSRVB Mask */ 1473 1474 #define UTCPD_DVCAP1_CPSRHV_Pos (1) /*!< UTCPD_T::DVCAP1: CPSRHV Position */ 1475 #define UTCPD_DVCAP1_CPSRHV_Msk (0x1ul << UTCPD_DVCAP1_CPSRHV_Pos) /*!< UTCPD_T::DVCAP1: CPSRHV Mask */ 1476 1477 #define UTCPD_DVCAP1_CPSKVB_Pos (2) /*!< UTCPD_T::DVCAP1: CPSKVB Position */ 1478 #define UTCPD_DVCAP1_CPSKVB_Msk (0x1ul << UTCPD_DVCAP1_CPSKVB_Pos) /*!< UTCPD_T::DVCAP1: CPSKVB Mask */ 1479 1480 #define UTCPD_DVCAP1_CPSRVC_Pos (3) /*!< UTCPD_T::DVCAP1: CPSRVC Position */ 1481 #define UTCPD_DVCAP1_CPSRVC_Msk (0x1ul << UTCPD_DVCAP1_CPSRVC_Pos) /*!< UTCPD_T::DVCAP1: CPSRVC Mask */ 1482 1483 #define UTCPD_DVCAP1_CPSDBG_Pos (4) /*!< UTCPD_T::DVCAP1: CPSDBG Position */ 1484 #define UTCPD_DVCAP1_CPSDBG_Msk (0x1ul << UTCPD_DVCAP1_CPSDBG_Pos) /*!< UTCPD_T::DVCAP1: CPSDBG Mask */ 1485 1486 #define UTCPD_DVCAP1_CPROL_Pos (5) /*!< UTCPD_T::DVCAP1: CPROL Position */ 1487 #define UTCPD_DVCAP1_CPROL_Msk (0x7ul << UTCPD_DVCAP1_CPROL_Pos) /*!< UTCPD_T::DVCAP1: CPROL Mask */ 1488 1489 #define UTCPD_DVCAP1_CPSRRE_Pos (8) /*!< UTCPD_T::DVCAP1: CPSRRE Position */ 1490 #define UTCPD_DVCAP1_CPSRRE_Msk (0x3ul << UTCPD_DVCAP1_CPSRRE_Pos) /*!< UTCPD_T::DVCAP1: CPSRRE Mask */ 1491 1492 #define UTCPD_DVCAP1_CPVBAM_Pos (10) /*!< UTCPD_T::DVCAP1: CPVBAM Position */ 1493 #define UTCPD_DVCAP1_CPVBAM_Msk (0x1ul << UTCPD_DVCAP1_CPVBAM_Pos) /*!< UTCPD_T::DVCAP1: CPVBAM Mask */ 1494 1495 #define UTCPD_DVCAP1_CPFDG_Pos (11) /*!< UTCPD_T::DVCAP1: CPFDG Position */ 1496 #define UTCPD_DVCAP1_CPFDG_Msk (0x1ul << UTCPD_DVCAP1_CPFDG_Pos) /*!< UTCPD_T::DVCAP1: CPFDG Mask */ 1497 1498 #define UTCPD_DVCAP1_CPBDG_Pos (12) /*!< UTCPD_T::DVCAP1: CPBDG Position */ 1499 #define UTCPD_DVCAP1_CPBDG_Msk (0x1ul << UTCPD_DVCAP1_CPBDG_Pos) /*!< UTCPD_T::DVCAP1: CPBDG Mask */ 1500 1501 #define UTCPD_DVCAP1_CPVBOVP_Pos (13) /*!< UTCPD_T::DVCAP1: CPVBOVP Position */ 1502 #define UTCPD_DVCAP1_CPVBOVP_Msk (0x1ul << UTCPD_DVCAP1_CPVBOVP_Pos) /*!< UTCPD_T::DVCAP1: CPVBOVP Mask */ 1503 1504 #define UTCPD_DVCAP1_CPVBOCP_Pos (14) /*!< UTCPD_T::DVCAP1: CPVBOCP Position */ 1505 #define UTCPD_DVCAP1_CPVBOCP_Msk (0x1ul << UTCPD_DVCAP1_CPVBOCP_Pos) /*!< UTCPD_T::DVCAP1: CPVBOCP Mask */ 1506 1507 #define UTCPD_DVCAP2_CPVCOC_Pos (0) /*!< UTCPD_T::DVCAP2: CPVCOC Position */ 1508 #define UTCPD_DVCAP2_CPVCOC_Msk (0x1ul << UTCPD_DVCAP2_CPVCOC_Pos) /*!< UTCPD_T::DVCAP2: CPVCOC Mask */ 1509 1510 #define UTCPD_DVCAP2_CPVCPWR_Pos (1) /*!< UTCPD_T::DVCAP2: CPVCPWR Position */ 1511 #define UTCPD_DVCAP2_CPVCPWR_Msk (0x7ul << UTCPD_DVCAP2_CPVCPWR_Pos) /*!< UTCPD_T::DVCAP2: CPVCPWR Mask */ 1512 1513 #define UTCPD_DVCAP2_CPVBAMLS_Pos (4) /*!< UTCPD_T::DVCAP2: CPVBAMLS Position */ 1514 #define UTCPD_DVCAP2_CPVBAMLS_Msk (0x3ul << UTCPD_DVCAP2_CPVBAMLS_Pos) /*!< UTCPD_T::DVCAP2: CPVBAMLS Mask */ 1515 1516 #define UTCPD_DVCAP2_CPSPDGTH_Pos (6) /*!< UTCPD_T::DVCAP2: CPSPDGTH Position */ 1517 #define UTCPD_DVCAP2_CPSPDGTH_Msk (0x1ul << UTCPD_DVCAP2_CPSPDGTH_Pos) /*!< UTCPD_T::DVCAP2: CPSPDGTH Mask */ 1518 1519 #define UTCPD_DVCAP2_CPSKDCDT_Pos (7) /*!< UTCPD_T::DVCAP2: CPSKDCDT Position */ 1520 #define UTCPD_DVCAP2_CPSKDCDT_Msk (0x1ul << UTCPD_DVCAP2_CPSKDCDT_Pos) /*!< UTCPD_T::DVCAP2: CPSKDCDT Mask */ 1521 1522 #define UTCPD_MSHEAD_PWRROL_Pos (0) /*!< UTCPD_T::MSHEAD: PWRROL Position */ 1523 #define UTCPD_MSHEAD_PWRROL_Msk (0x1ul << UTCPD_MSHEAD_PWRROL_Pos) /*!< UTCPD_T::MSHEAD: PWRROL Mask */ 1524 1525 #define UTCPD_MSHEAD_PDREV_Pos (1) /*!< UTCPD_T::MSHEAD: PDREV Position */ 1526 #define UTCPD_MSHEAD_PDREV_Msk (0x3ul << UTCPD_MSHEAD_PDREV_Pos) /*!< UTCPD_T::MSHEAD: PDREV Mask */ 1527 1528 #define UTCPD_MSHEAD_DAROL_Pos (3) /*!< UTCPD_T::MSHEAD: DAROL Position */ 1529 #define UTCPD_MSHEAD_DAROL_Msk (0x1ul << UTCPD_MSHEAD_DAROL_Pos) /*!< UTCPD_T::MSHEAD: DAROL Mask */ 1530 1531 #define UTCPD_MSHEAD_CABPLG_Pos (4) /*!< UTCPD_T::MSHEAD: CABPLG Position */ 1532 #define UTCPD_MSHEAD_CABPLG_Msk (0x1ul << UTCPD_MSHEAD_CABPLG_Pos) /*!< UTCPD_T::MSHEAD: CABPLG Mask */ 1533 1534 #define UTCPD_DTRXEVNT_SOPEN_Pos (0) /*!< UTCPD_T::DTRXEVNT: SOPEN Position */ 1535 #define UTCPD_DTRXEVNT_SOPEN_Msk (0x1ul << UTCPD_DTRXEVNT_SOPEN_Pos) /*!< UTCPD_T::DTRXEVNT: SOPEN Mask */ 1536 1537 #define UTCPD_DTRXEVNT_SOPPEN_Pos (1) /*!< UTCPD_T::DTRXEVNT: SOPPEN Position */ 1538 #define UTCPD_DTRXEVNT_SOPPEN_Msk (0x1ul << UTCPD_DTRXEVNT_SOPPEN_Pos) /*!< UTCPD_T::DTRXEVNT: SOPPEN Mask */ 1539 1540 #define UTCPD_DTRXEVNT_SOPPPEN_Pos (2) /*!< UTCPD_T::DTRXEVNT: SOPPPEN Position */ 1541 #define UTCPD_DTRXEVNT_SOPPPEN_Msk (0x1ul << UTCPD_DTRXEVNT_SOPPPEN_Pos) /*!< UTCPD_T::DTRXEVNT: SOPPPEN Mask */ 1542 1543 #define UTCPD_DTRXEVNT_SDBGPEN_Pos (3) /*!< UTCPD_T::DTRXEVNT: SDBGPEN Position */ 1544 #define UTCPD_DTRXEVNT_SDBGPEN_Msk (0x1ul << UTCPD_DTRXEVNT_SDBGPEN_Pos) /*!< UTCPD_T::DTRXEVNT: SDBGPEN Mask */ 1545 1546 #define UTCPD_DTRXEVNT_SDBGPPEN_Pos (4) /*!< UTCPD_T::DTRXEVNT: SDBGPPEN Position */ 1547 #define UTCPD_DTRXEVNT_SDBGPPEN_Msk (0x1ul << UTCPD_DTRXEVNT_SDBGPPEN_Pos) /*!< UTCPD_T::DTRXEVNT: SDBGPPEN Mask */ 1548 1549 #define UTCPD_DTRXEVNT_HRSTEN_Pos (5) /*!< UTCPD_T::DTRXEVNT: HRSTEN Position */ 1550 #define UTCPD_DTRXEVNT_HRSTEN_Msk (0x1ul << UTCPD_DTRXEVNT_HRSTEN_Pos) /*!< UTCPD_T::DTRXEVNT: HRSTEN Mask */ 1551 1552 #define UTCPD_DTRXEVNT_CABRSTEN_Pos (6) /*!< UTCPD_T::DTRXEVNT: CABRSTEN Position */ 1553 #define UTCPD_DTRXEVNT_CABRSTEN_Msk (0x1ul << UTCPD_DTRXEVNT_CABRSTEN_Pos) /*!< UTCPD_T::DTRXEVNT: CABRSTEN Mask */ 1554 1555 #define UTCPD_RXBCNT_RXBCNT_Pos (0) /*!< UTCPD_T::RXBCNT: RXBCNT Position */ 1556 #define UTCPD_RXBCNT_RXBCNT_Msk (0xfful << UTCPD_RXBCNT_RXBCNT_Pos) /*!< UTCPD_T::RXBCNT: RXBCNT Mask */ 1557 1558 #define UTCPD_RXFTYPE_RXFTYPE_Pos (0) /*!< UTCPD_T::RXFTYPE: RXFTYPE Position */ 1559 #define UTCPD_RXFTYPE_RXFTYPE_Msk (0x7ul << UTCPD_RXFTYPE_RXFTYPE_Pos) /*!< UTCPD_T::RXFTYPE: RXFTYPE Mask */ 1560 1561 #define UTCPD_RXHEAD_RXHEAD0_Pos (0) /*!< UTCPD_T::RXHEAD: RXHEAD0 Position */ 1562 #define UTCPD_RXHEAD_RXHEAD0_Msk (0xfful << UTCPD_RXHEAD_RXHEAD0_Pos) /*!< UTCPD_T::RXHEAD: RXHEAD0 Mask */ 1563 1564 #define UTCPD_RXHEAD_RXHEAD1_Pos (8) /*!< UTCPD_T::RXHEAD: RXHEAD1 Position */ 1565 #define UTCPD_RXHEAD_RXHEAD1_Msk (0xfful << UTCPD_RXHEAD_RXHEAD1_Pos) /*!< UTCPD_T::RXHEAD: RXHEAD1 Mask */ 1566 1567 #define UTCPD_RXDA0_RXDAB0_Pos (0) /*!< UTCPD_T::RXDA0: RXDAB0 Position */ 1568 #define UTCPD_RXDA0_RXDAB0_Msk (0xfful << UTCPD_RXDA0_RXDAB0_Pos) /*!< UTCPD_T::RXDA0: RXDAB0 Mask */ 1569 1570 #define UTCPD_RXDA0_RXDAB1_Pos (8) /*!< UTCPD_T::RXDA0: RXDAB1 Position */ 1571 #define UTCPD_RXDA0_RXDAB1_Msk (0xfful << UTCPD_RXDA0_RXDAB1_Pos) /*!< UTCPD_T::RXDA0: RXDAB1 Mask */ 1572 1573 #define UTCPD_RXDA0_RXDAB2_Pos (16) /*!< UTCPD_T::RXDA0: RXDAB2 Position */ 1574 #define UTCPD_RXDA0_RXDAB2_Msk (0xfful << UTCPD_RXDA0_RXDAB2_Pos) /*!< UTCPD_T::RXDA0: RXDAB2 Mask */ 1575 1576 #define UTCPD_RXDA0_RXDAB3_Pos (24) /*!< UTCPD_T::RXDA0: RXDAB3 Position */ 1577 #define UTCPD_RXDA0_RXDAB3_Msk (0xfful << UTCPD_RXDA0_RXDAB3_Pos) /*!< UTCPD_T::RXDA0: RXDAB3 Mask */ 1578 1579 #define UTCPD_RXDA1_RXDAB0_Pos (0) /*!< UTCPD_T::RXDA1: RXDAB0 Position */ 1580 #define UTCPD_RXDA1_RXDAB0_Msk (0xfful << UTCPD_RXDA1_RXDAB0_Pos) /*!< UTCPD_T::RXDA1: RXDAB0 Mask */ 1581 1582 #define UTCPD_RXDA1_RXDAB1_Pos (8) /*!< UTCPD_T::RXDA1: RXDAB1 Position */ 1583 #define UTCPD_RXDA1_RXDAB1_Msk (0xfful << UTCPD_RXDA1_RXDAB1_Pos) /*!< UTCPD_T::RXDA1: RXDAB1 Mask */ 1584 1585 #define UTCPD_RXDA1_RXDAB2_Pos (16) /*!< UTCPD_T::RXDA1: RXDAB2 Position */ 1586 #define UTCPD_RXDA1_RXDAB2_Msk (0xfful << UTCPD_RXDA1_RXDAB2_Pos) /*!< UTCPD_T::RXDA1: RXDAB2 Mask */ 1587 1588 #define UTCPD_RXDA1_RXDAB3_Pos (24) /*!< UTCPD_T::RXDA1: RXDAB3 Position */ 1589 #define UTCPD_RXDA1_RXDAB3_Msk (0xfful << UTCPD_RXDA1_RXDAB3_Pos) /*!< UTCPD_T::RXDA1: RXDAB3 Mask */ 1590 1591 #define UTCPD_RXDA2_RXDAB0_Pos (0) /*!< UTCPD_T::RXDA2: RXDAB0 Position */ 1592 #define UTCPD_RXDA2_RXDAB0_Msk (0xfful << UTCPD_RXDA2_RXDAB0_Pos) /*!< UTCPD_T::RXDA2: RXDAB0 Mask */ 1593 1594 #define UTCPD_RXDA2_RXDAB1_Pos (8) /*!< UTCPD_T::RXDA2: RXDAB1 Position */ 1595 #define UTCPD_RXDA2_RXDAB1_Msk (0xfful << UTCPD_RXDA2_RXDAB1_Pos) /*!< UTCPD_T::RXDA2: RXDAB1 Mask */ 1596 1597 #define UTCPD_RXDA2_RXDAB2_Pos (16) /*!< UTCPD_T::RXDA2: RXDAB2 Position */ 1598 #define UTCPD_RXDA2_RXDAB2_Msk (0xfful << UTCPD_RXDA2_RXDAB2_Pos) /*!< UTCPD_T::RXDA2: RXDAB2 Mask */ 1599 1600 #define UTCPD_RXDA2_RXDAB3_Pos (24) /*!< UTCPD_T::RXDA2: RXDAB3 Position */ 1601 #define UTCPD_RXDA2_RXDAB3_Msk (0xfful << UTCPD_RXDA2_RXDAB3_Pos) /*!< UTCPD_T::RXDA2: RXDAB3 Mask */ 1602 1603 #define UTCPD_RXDA3_RXDAB0_Pos (0) /*!< UTCPD_T::RXDA3: RXDAB0 Position */ 1604 #define UTCPD_RXDA3_RXDAB0_Msk (0xfful << UTCPD_RXDA3_RXDAB0_Pos) /*!< UTCPD_T::RXDA3: RXDAB0 Mask */ 1605 1606 #define UTCPD_RXDA3_RXDAB1_Pos (8) /*!< UTCPD_T::RXDA3: RXDAB1 Position */ 1607 #define UTCPD_RXDA3_RXDAB1_Msk (0xfful << UTCPD_RXDA3_RXDAB1_Pos) /*!< UTCPD_T::RXDA3: RXDAB1 Mask */ 1608 1609 #define UTCPD_RXDA3_RXDAB2_Pos (16) /*!< UTCPD_T::RXDA3: RXDAB2 Position */ 1610 #define UTCPD_RXDA3_RXDAB2_Msk (0xfful << UTCPD_RXDA3_RXDAB2_Pos) /*!< UTCPD_T::RXDA3: RXDAB2 Mask */ 1611 1612 #define UTCPD_RXDA3_RXDAB3_Pos (24) /*!< UTCPD_T::RXDA3: RXDAB3 Position */ 1613 #define UTCPD_RXDA3_RXDAB3_Msk (0xfful << UTCPD_RXDA3_RXDAB3_Pos) /*!< UTCPD_T::RXDA3: RXDAB3 Mask */ 1614 1615 #define UTCPD_RXDA4_RXDAB0_Pos (0) /*!< UTCPD_T::RXDA4: RXDAB0 Position */ 1616 #define UTCPD_RXDA4_RXDAB0_Msk (0xfful << UTCPD_RXDA4_RXDAB0_Pos) /*!< UTCPD_T::RXDA4: RXDAB0 Mask */ 1617 1618 #define UTCPD_RXDA4_RXDAB1_Pos (8) /*!< UTCPD_T::RXDA4: RXDAB1 Position */ 1619 #define UTCPD_RXDA4_RXDAB1_Msk (0xfful << UTCPD_RXDA4_RXDAB1_Pos) /*!< UTCPD_T::RXDA4: RXDAB1 Mask */ 1620 1621 #define UTCPD_RXDA4_RXDAB2_Pos (16) /*!< UTCPD_T::RXDA4: RXDAB2 Position */ 1622 #define UTCPD_RXDA4_RXDAB2_Msk (0xfful << UTCPD_RXDA4_RXDAB2_Pos) /*!< UTCPD_T::RXDA4: RXDAB2 Mask */ 1623 1624 #define UTCPD_RXDA4_RXDAB3_Pos (24) /*!< UTCPD_T::RXDA4: RXDAB3 Position */ 1625 #define UTCPD_RXDA4_RXDAB3_Msk (0xfful << UTCPD_RXDA4_RXDAB3_Pos) /*!< UTCPD_T::RXDA4: RXDAB3 Mask */ 1626 1627 #define UTCPD_RXDA5_RXDAB0_Pos (0) /*!< UTCPD_T::RXDA5: RXDAB0 Position */ 1628 #define UTCPD_RXDA5_RXDAB0_Msk (0xfful << UTCPD_RXDA5_RXDAB0_Pos) /*!< UTCPD_T::RXDA5: RXDAB0 Mask */ 1629 1630 #define UTCPD_RXDA5_RXDAB1_Pos (8) /*!< UTCPD_T::RXDA5: RXDAB1 Position */ 1631 #define UTCPD_RXDA5_RXDAB1_Msk (0xfful << UTCPD_RXDA5_RXDAB1_Pos) /*!< UTCPD_T::RXDA5: RXDAB1 Mask */ 1632 1633 #define UTCPD_RXDA5_RXDAB2_Pos (16) /*!< UTCPD_T::RXDA5: RXDAB2 Position */ 1634 #define UTCPD_RXDA5_RXDAB2_Msk (0xfful << UTCPD_RXDA5_RXDAB2_Pos) /*!< UTCPD_T::RXDA5: RXDAB2 Mask */ 1635 1636 #define UTCPD_RXDA5_RXDAB3_Pos (24) /*!< UTCPD_T::RXDA5: RXDAB3 Position */ 1637 #define UTCPD_RXDA5_RXDAB3_Msk (0xfful << UTCPD_RXDA5_RXDAB3_Pos) /*!< UTCPD_T::RXDA5: RXDAB3 Mask */ 1638 1639 #define UTCPD_RXDA6_RXDAB0_Pos (0) /*!< UTCPD_T::RXDA6: RXDAB0 Position */ 1640 #define UTCPD_RXDA6_RXDAB0_Msk (0xfful << UTCPD_RXDA6_RXDAB0_Pos) /*!< UTCPD_T::RXDA6: RXDAB0 Mask */ 1641 1642 #define UTCPD_RXDA6_RXDAB1_Pos (8) /*!< UTCPD_T::RXDA6: RXDAB1 Position */ 1643 #define UTCPD_RXDA6_RXDAB1_Msk (0xfful << UTCPD_RXDA6_RXDAB1_Pos) /*!< UTCPD_T::RXDA6: RXDAB1 Mask */ 1644 1645 #define UTCPD_RXDA6_RXDAB2_Pos (16) /*!< UTCPD_T::RXDA6: RXDAB2 Position */ 1646 #define UTCPD_RXDA6_RXDAB2_Msk (0xfful << UTCPD_RXDA6_RXDAB2_Pos) /*!< UTCPD_T::RXDA6: RXDAB2 Mask */ 1647 1648 #define UTCPD_RXDA6_RXDAB3_Pos (24) /*!< UTCPD_T::RXDA6: RXDAB3 Position */ 1649 #define UTCPD_RXDA6_RXDAB3_Msk (0xfful << UTCPD_RXDA6_RXDAB3_Pos) /*!< UTCPD_T::RXDA6: RXDAB3 Mask */ 1650 1651 #define UTCPD_TXCTL_TXSTYPE_Pos (0) /*!< UTCPD_T::TXCTL: TXSTYPE Position */ 1652 #define UTCPD_TXCTL_TXSTYPE_Msk (0x7ul << UTCPD_TXCTL_TXSTYPE_Pos) /*!< UTCPD_T::TXCTL: TXSTYPE Mask */ 1653 1654 #define UTCPD_TXCTL_RETRYCNT_Pos (4) /*!< UTCPD_T::TXCTL: RETRYCNT Position */ 1655 #define UTCPD_TXCTL_RETRYCNT_Msk (0x3ul << UTCPD_TXCTL_RETRYCNT_Pos) /*!< UTCPD_T::TXCTL: RETRYCNT Mask */ 1656 1657 #define UTCPD_TXBCNT_TXBCNT_Pos (0) /*!< UTCPD_T::TXBCNT: TXBCNT Position */ 1658 #define UTCPD_TXBCNT_TXBCNT_Msk (0xfful << UTCPD_TXBCNT_TXBCNT_Pos) /*!< UTCPD_T::TXBCNT: TXBCNT Mask */ 1659 1660 #define UTCPD_TXHEAD_TXHEAD0_Pos (0) /*!< UTCPD_T::TXHEAD: TXHEAD0 Position */ 1661 #define UTCPD_TXHEAD_TXHEAD0_Msk (0xfful << UTCPD_TXHEAD_TXHEAD0_Pos) /*!< UTCPD_T::TXHEAD: TXHEAD0 Mask */ 1662 1663 #define UTCPD_TXHEAD_TXHEAD1_Pos (8) /*!< UTCPD_T::TXHEAD: TXHEAD1 Position */ 1664 #define UTCPD_TXHEAD_TXHEAD1_Msk (0xfful << UTCPD_TXHEAD_TXHEAD1_Pos) /*!< UTCPD_T::TXHEAD: TXHEAD1 Mask */ 1665 1666 #define UTCPD_TXDA0_TXDAB0_Pos (0) /*!< UTCPD_T::TXDA0: TXDAB0 Position */ 1667 #define UTCPD_TXDA0_TXDAB0_Msk (0xfful << UTCPD_TXDA0_TXDAB0_Pos) /*!< UTCPD_T::TXDA0: TXDAB0 Mask */ 1668 1669 #define UTCPD_TXDA0_TXDAB1_Pos (8) /*!< UTCPD_T::TXDA0: TXDAB1 Position */ 1670 #define UTCPD_TXDA0_TXDAB1_Msk (0xfful << UTCPD_TXDA0_TXDAB1_Pos) /*!< UTCPD_T::TXDA0: TXDAB1 Mask */ 1671 1672 #define UTCPD_TXDA0_TXDAB2_Pos (16) /*!< UTCPD_T::TXDA0: TXDAB2 Position */ 1673 #define UTCPD_TXDA0_TXDAB2_Msk (0xfful << UTCPD_TXDA0_TXDAB2_Pos) /*!< UTCPD_T::TXDA0: TXDAB2 Mask */ 1674 1675 #define UTCPD_TXDA0_TXDAB3_Pos (24) /*!< UTCPD_T::TXDA0: TXDAB3 Position */ 1676 #define UTCPD_TXDA0_TXDAB3_Msk (0xfful << UTCPD_TXDA0_TXDAB3_Pos) /*!< UTCPD_T::TXDA0: TXDAB3 Mask */ 1677 1678 #define UTCPD_TXDA1_TXDAB0_Pos (0) /*!< UTCPD_T::TXDA1: TXDAB0 Position */ 1679 #define UTCPD_TXDA1_TXDAB0_Msk (0xfful << UTCPD_TXDA1_TXDAB0_Pos) /*!< UTCPD_T::TXDA1: TXDAB0 Mask */ 1680 1681 #define UTCPD_TXDA1_TXDAB1_Pos (8) /*!< UTCPD_T::TXDA1: TXDAB1 Position */ 1682 #define UTCPD_TXDA1_TXDAB1_Msk (0xfful << UTCPD_TXDA1_TXDAB1_Pos) /*!< UTCPD_T::TXDA1: TXDAB1 Mask */ 1683 1684 #define UTCPD_TXDA1_TXDAB2_Pos (16) /*!< UTCPD_T::TXDA1: TXDAB2 Position */ 1685 #define UTCPD_TXDA1_TXDAB2_Msk (0xfful << UTCPD_TXDA1_TXDAB2_Pos) /*!< UTCPD_T::TXDA1: TXDAB2 Mask */ 1686 1687 #define UTCPD_TXDA1_TXDAB3_Pos (24) /*!< UTCPD_T::TXDA1: TXDAB3 Position */ 1688 #define UTCPD_TXDA1_TXDAB3_Msk (0xfful << UTCPD_TXDA1_TXDAB3_Pos) /*!< UTCPD_T::TXDA1: TXDAB3 Mask */ 1689 1690 #define UTCPD_TXDA2_TXDAB0_Pos (0) /*!< UTCPD_T::TXDA2: TXDAB0 Position */ 1691 #define UTCPD_TXDA2_TXDAB0_Msk (0xfful << UTCPD_TXDA2_TXDAB0_Pos) /*!< UTCPD_T::TXDA2: TXDAB0 Mask */ 1692 1693 #define UTCPD_TXDA2_TXDAB1_Pos (8) /*!< UTCPD_T::TXDA2: TXDAB1 Position */ 1694 #define UTCPD_TXDA2_TXDAB1_Msk (0xfful << UTCPD_TXDA2_TXDAB1_Pos) /*!< UTCPD_T::TXDA2: TXDAB1 Mask */ 1695 1696 #define UTCPD_TXDA2_TXDAB2_Pos (16) /*!< UTCPD_T::TXDA2: TXDAB2 Position */ 1697 #define UTCPD_TXDA2_TXDAB2_Msk (0xfful << UTCPD_TXDA2_TXDAB2_Pos) /*!< UTCPD_T::TXDA2: TXDAB2 Mask */ 1698 1699 #define UTCPD_TXDA2_TXDAB3_Pos (24) /*!< UTCPD_T::TXDA2: TXDAB3 Position */ 1700 #define UTCPD_TXDA2_TXDAB3_Msk (0xfful << UTCPD_TXDA2_TXDAB3_Pos) /*!< UTCPD_T::TXDA2: TXDAB3 Mask */ 1701 1702 #define UTCPD_TXDA3_TXDAB0_Pos (0) /*!< UTCPD_T::TXDA3: TXDAB0 Position */ 1703 #define UTCPD_TXDA3_TXDAB0_Msk (0xfful << UTCPD_TXDA3_TXDAB0_Pos) /*!< UTCPD_T::TXDA3: TXDAB0 Mask */ 1704 1705 #define UTCPD_TXDA3_TXDAB1_Pos (8) /*!< UTCPD_T::TXDA3: TXDAB1 Position */ 1706 #define UTCPD_TXDA3_TXDAB1_Msk (0xfful << UTCPD_TXDA3_TXDAB1_Pos) /*!< UTCPD_T::TXDA3: TXDAB1 Mask */ 1707 1708 #define UTCPD_TXDA3_TXDAB2_Pos (16) /*!< UTCPD_T::TXDA3: TXDAB2 Position */ 1709 #define UTCPD_TXDA3_TXDAB2_Msk (0xfful << UTCPD_TXDA3_TXDAB2_Pos) /*!< UTCPD_T::TXDA3: TXDAB2 Mask */ 1710 1711 #define UTCPD_TXDA3_TXDAB3_Pos (24) /*!< UTCPD_T::TXDA3: TXDAB3 Position */ 1712 #define UTCPD_TXDA3_TXDAB3_Msk (0xfful << UTCPD_TXDA3_TXDAB3_Pos) /*!< UTCPD_T::TXDA3: TXDAB3 Mask */ 1713 1714 #define UTCPD_TXDA4_TXDAB0_Pos (0) /*!< UTCPD_T::TXDA4: TXDAB0 Position */ 1715 #define UTCPD_TXDA4_TXDAB0_Msk (0xfful << UTCPD_TXDA4_TXDAB0_Pos) /*!< UTCPD_T::TXDA4: TXDAB0 Mask */ 1716 1717 #define UTCPD_TXDA4_TXDAB1_Pos (8) /*!< UTCPD_T::TXDA4: TXDAB1 Position */ 1718 #define UTCPD_TXDA4_TXDAB1_Msk (0xfful << UTCPD_TXDA4_TXDAB1_Pos) /*!< UTCPD_T::TXDA4: TXDAB1 Mask */ 1719 1720 #define UTCPD_TXDA4_TXDAB2_Pos (16) /*!< UTCPD_T::TXDA4: TXDAB2 Position */ 1721 #define UTCPD_TXDA4_TXDAB2_Msk (0xfful << UTCPD_TXDA4_TXDAB2_Pos) /*!< UTCPD_T::TXDA4: TXDAB2 Mask */ 1722 1723 #define UTCPD_TXDA4_TXDAB3_Pos (24) /*!< UTCPD_T::TXDA4: TXDAB3 Position */ 1724 #define UTCPD_TXDA4_TXDAB3_Msk (0xfful << UTCPD_TXDA4_TXDAB3_Pos) /*!< UTCPD_T::TXDA4: TXDAB3 Mask */ 1725 1726 #define UTCPD_TXDA5_TXDAB0_Pos (0) /*!< UTCPD_T::TXDA5: TXDAB0 Position */ 1727 #define UTCPD_TXDA5_TXDAB0_Msk (0xfful << UTCPD_TXDA5_TXDAB0_Pos) /*!< UTCPD_T::TXDA5: TXDAB0 Mask */ 1728 1729 #define UTCPD_TXDA5_TXDAB1_Pos (8) /*!< UTCPD_T::TXDA5: TXDAB1 Position */ 1730 #define UTCPD_TXDA5_TXDAB1_Msk (0xfful << UTCPD_TXDA5_TXDAB1_Pos) /*!< UTCPD_T::TXDA5: TXDAB1 Mask */ 1731 1732 #define UTCPD_TXDA5_TXDAB2_Pos (16) /*!< UTCPD_T::TXDA5: TXDAB2 Position */ 1733 #define UTCPD_TXDA5_TXDAB2_Msk (0xfful << UTCPD_TXDA5_TXDAB2_Pos) /*!< UTCPD_T::TXDA5: TXDAB2 Mask */ 1734 1735 #define UTCPD_TXDA5_TXDAB3_Pos (24) /*!< UTCPD_T::TXDA5: TXDAB3 Position */ 1736 #define UTCPD_TXDA5_TXDAB3_Msk (0xfful << UTCPD_TXDA5_TXDAB3_Pos) /*!< UTCPD_T::TXDA5: TXDAB3 Mask */ 1737 1738 #define UTCPD_TXDA6_TXDAB0_Pos (0) /*!< UTCPD_T::TXDA6: TXDAB0 Position */ 1739 #define UTCPD_TXDA6_TXDAB0_Msk (0xfful << UTCPD_TXDA6_TXDAB0_Pos) /*!< UTCPD_T::TXDA6: TXDAB0 Mask */ 1740 1741 #define UTCPD_TXDA6_TXDAB1_Pos (8) /*!< UTCPD_T::TXDA6: TXDAB1 Position */ 1742 #define UTCPD_TXDA6_TXDAB1_Msk (0xfful << UTCPD_TXDA6_TXDAB1_Pos) /*!< UTCPD_T::TXDA6: TXDAB1 Mask */ 1743 1744 #define UTCPD_TXDA6_TXDAB2_Pos (16) /*!< UTCPD_T::TXDA6: TXDAB2 Position */ 1745 #define UTCPD_TXDA6_TXDAB2_Msk (0xfful << UTCPD_TXDA6_TXDAB2_Pos) /*!< UTCPD_T::TXDA6: TXDAB2 Mask */ 1746 1747 #define UTCPD_TXDA6_TXDAB3_Pos (24) /*!< UTCPD_T::TXDA6: TXDAB3 Position */ 1748 #define UTCPD_TXDA6_TXDAB3_Msk (0xfful << UTCPD_TXDA6_TXDAB3_Pos) /*!< UTCPD_T::TXDA6: TXDAB3 Mask */ 1749 1750 #define UTCPD_VBVOL_VBVOL_Pos (0) /*!< UTCPD_T::VBVOL: VBVOL Position */ 1751 #define UTCPD_VBVOL_VBVOL_Msk (0x3fful << UTCPD_VBVOL_VBVOL_Pos) /*!< UTCPD_T::VBVOL: VBVOL Mask */ 1752 1753 #define UTCPD_VBVOL_VBSCALE_Pos (10) /*!< UTCPD_T::VBVOL: VBSCALE Position */ 1754 #define UTCPD_VBVOL_VBSCALE_Msk (0x3ul << UTCPD_VBVOL_VBSCALE_Pos) /*!< UTCPD_T::VBVOL: VBSCALE Mask */ 1755 1756 #define UTCPD_SKVBDCTH_SKVBDCTH_Pos (0) /*!< UTCPD_T::SKVBDCTH: SKVBDCTH Position */ 1757 #define UTCPD_SKVBDCTH_SKVBDCTH_Msk (0x3fful << UTCPD_SKVBDCTH_SKVBDCTH_Pos) /*!< UTCPD_T::SKVBDCTH: SKVBDCTH Mask */ 1758 1759 #define UTCPD_SPDGTH_SPDGTH_Pos (0) /*!< UTCPD_T::SPDGTH: SPDGTH Position */ 1760 #define UTCPD_SPDGTH_SPDGTH_Msk (0x3fful << UTCPD_SPDGTH_SPDGTH_Pos) /*!< UTCPD_T::SPDGTH: SPDGTH Mask */ 1761 1762 #define UTCPD_VBAMH_VBAMH_Pos (0) /*!< UTCPD_T::VBAMH: VBAMH Position */ 1763 #define UTCPD_VBAMH_VBAMH_Msk (0x3fful << UTCPD_VBAMH_VBAMH_Pos) /*!< UTCPD_T::VBAMH: VBAMH Mask */ 1764 1765 #define UTCPD_VBAML_VBAML_Pos (0) /*!< UTCPD_T::VBAML: VBAML Position */ 1766 #define UTCPD_VBAML_VBAML_Msk (0x3fful << UTCPD_VBAML_VBAML_Pos) /*!< UTCPD_T::VBAML: VBAML Mask */ 1767 1768 #define UTCPD_VNDIS_RXFRSIS_Pos (0) /*!< UTCPD_T::VNDIS: RXFRSIS Position */ 1769 #define UTCPD_VNDIS_RXFRSIS_Msk (0x1ul << UTCPD_VNDIS_RXFRSIS_Pos) /*!< UTCPD_T::VNDIS: RXFRSIS Mask */ 1770 1771 #define UTCPD_VNDIS_TXFRSIS_Pos (1) /*!< UTCPD_T::VNDIS: TXFRSIS Position */ 1772 #define UTCPD_VNDIS_TXFRSIS_Msk (0x1ul << UTCPD_VNDIS_TXFRSIS_Pos) /*!< UTCPD_T::VNDIS: TXFRSIS Mask */ 1773 1774 #define UTCPD_VNDIS_CRCERRIS_Pos (3) /*!< UTCPD_T::VNDIS: CRCERRIS Position */ 1775 #define UTCPD_VNDIS_CRCERRIS_Msk (0x1ul << UTCPD_VNDIS_CRCERRIS_Pos) /*!< UTCPD_T::VNDIS: CRCERRIS Mask */ 1776 1777 #define UTCPD_VNDIS_VCDGIS_Pos (5) /*!< UTCPD_T::VNDIS: VCDGIS Position */ 1778 #define UTCPD_VNDIS_VCDGIS_Msk (0x1ul << UTCPD_VNDIS_VCDGIS_Pos) /*!< UTCPD_T::VNDIS: VCDGIS Mask */ 1779 1780 #define UTCPD_VNDIE_RXFRSIE_Pos (0) /*!< UTCPD_T::VNDIE: RXFRSIE Position */ 1781 #define UTCPD_VNDIE_RXFRSIE_Msk (0x1ul << UTCPD_VNDIE_RXFRSIE_Pos) /*!< UTCPD_T::VNDIE: RXFRSIE Mask */ 1782 1783 #define UTCPD_VNDIE_TXFRSIE_Pos (1) /*!< UTCPD_T::VNDIE: TXFRSIE Position */ 1784 #define UTCPD_VNDIE_TXFRSIE_Msk (0x1ul << UTCPD_VNDIE_TXFRSIE_Pos) /*!< UTCPD_T::VNDIE: TXFRSIE Mask */ 1785 1786 #define UTCPD_VNDIE_CRCERRIE_Pos (3) /*!< UTCPD_T::VNDIE: CRCERRIE Position */ 1787 #define UTCPD_VNDIE_CRCERRIE_Msk (0x1ul << UTCPD_VNDIE_CRCERRIE_Pos) /*!< UTCPD_T::VNDIE: CRCERRIE Mask */ 1788 1789 #define UTCPD_VNDIE_VCDGIE_Pos (5) /*!< UTCPD_T::VNDIE: VCDGIE Position */ 1790 #define UTCPD_VNDIE_VCDGIE_Msk (0x1ul << UTCPD_VNDIE_VCDGIE_Pos) /*!< UTCPD_T::VNDIE: VCDGIE Mask */ 1791 1792 #define UTCPD_MUXSEL_VBOCS_Pos (0) /*!< UTCPD_T::MUXSEL: VBOCS Position */ 1793 #define UTCPD_MUXSEL_VBOCS_Msk (0x7ul << UTCPD_MUXSEL_VBOCS_Pos) /*!< UTCPD_T::MUXSEL: VBOCS Mask */ 1794 1795 #define UTCPD_MUXSEL_VCOCS_Pos (4) /*!< UTCPD_T::MUXSEL: VCOCS Position */ 1796 #define UTCPD_MUXSEL_VCOCS_Msk (0x7ul << UTCPD_MUXSEL_VCOCS_Pos) /*!< UTCPD_T::MUXSEL: VCOCS Mask */ 1797 1798 #define UTCPD_MUXSEL_FVBS_Pos (8) /*!< UTCPD_T::MUXSEL: FVBS Position */ 1799 #define UTCPD_MUXSEL_FVBS_Msk (0x7ul << UTCPD_MUXSEL_FVBS_Pos) /*!< UTCPD_T::MUXSEL: FVBS Mask */ 1800 1801 #define UTCPD_MUXSEL_ADCSELVB_Pos (12) /*!< UTCPD_T::MUXSEL: ADCSELVB Position */ 1802 #define UTCPD_MUXSEL_ADCSELVB_Msk (0x1ful << UTCPD_MUXSEL_ADCSELVB_Pos) /*!< UTCPD_T::MUXSEL: ADCSELVB Mask */ 1803 1804 #define UTCPD_MUXSEL_ADCSELVC_Pos (17) /*!< UTCPD_T::MUXSEL: ADCSELVC Position */ 1805 #define UTCPD_MUXSEL_ADCSELVC_Msk (0x1ful << UTCPD_MUXSEL_ADCSELVC_Pos) /*!< UTCPD_T::MUXSEL: ADCSELVC Mask */ 1806 1807 #define UTCPD_MUXSEL_CC1VCENS_Pos (24) /*!< UTCPD_T::MUXSEL: CC1VCENS Position */ 1808 #define UTCPD_MUXSEL_CC1VCENS_Msk (0x1ul << UTCPD_MUXSEL_CC1VCENS_Pos) /*!< UTCPD_T::MUXSEL: CC1VCENS Mask */ 1809 1810 #define UTCPD_MUXSEL_CC1FRSS_Pos (25) /*!< UTCPD_T::MUXSEL: CC1FRSS Position */ 1811 #define UTCPD_MUXSEL_CC1FRSS_Msk (0x1ul << UTCPD_MUXSEL_CC1FRSS_Pos) /*!< UTCPD_T::MUXSEL: CC1FRSS Mask */ 1812 1813 #define UTCPD_MUXSEL_CC2VCENS_Pos (28) /*!< UTCPD_T::MUXSEL: CC2VCENS Position */ 1814 #define UTCPD_MUXSEL_CC2VCENS_Msk (0x1ul << UTCPD_MUXSEL_CC2VCENS_Pos) /*!< UTCPD_T::MUXSEL: CC2VCENS Mask */ 1815 1816 #define UTCPD_MUXSEL_CC2FRSS_Pos (29) /*!< UTCPD_T::MUXSEL: CC2FRSS Position */ 1817 #define UTCPD_MUXSEL_CC2FRSS_Msk (0x1ul << UTCPD_MUXSEL_CC2FRSS_Pos) /*!< UTCPD_T::MUXSEL: CC2FRSS Mask */ 1818 1819 #define UTCPD_VCDGCTL_VCUVDTEN_Pos (0) /*!< UTCPD_T::VCDGCTL: VCUVDTEN Position */ 1820 #define UTCPD_VCDGCTL_VCUVDTEN_Msk (0x1ul << UTCPD_VCDGCTL_VCUVDTEN_Pos) /*!< UTCPD_T::VCDGCTL: VCUVDTEN Mask */ 1821 1822 #define UTCPD_VCDGCTL_VCDGEN_Pos (1) /*!< UTCPD_T::VCDGCTL: VCDGEN Position */ 1823 #define UTCPD_VCDGCTL_VCDGEN_Msk (0x1ul << UTCPD_VCDGCTL_VCDGEN_Pos) /*!< UTCPD_T::VCDGCTL: VCDGEN Mask */ 1824 1825 #define UTCPD_PHYSLEW_TXRTRIM_Pos (0) /*!< UTCPD_T::PHYSLEW: TXRTRIM Position */ 1826 #define UTCPD_PHYSLEW_TXRTRIM_Msk (0x7ul << UTCPD_PHYSLEW_TXRTRIM_Pos) /*!< UTCPD_T::PHYSLEW: TXRTRIM Mask */ 1827 1828 #define UTCPD_PHYSLEW_TXFTRIM_Pos (4) /*!< UTCPD_T::PHYSLEW: TXFTRIM Position */ 1829 #define UTCPD_PHYSLEW_TXFTRIM_Msk (0x7ul << UTCPD_PHYSLEW_TXFTRIM_Pos) /*!< UTCPD_T::PHYSLEW: TXFTRIM Mask */ 1830 1831 #define UTCPD_ADGTM_ADGTM_Pos (0) /*!< UTCPD_T::ADGTM: ADGTM Position */ 1832 #define UTCPD_ADGTM_ADGTM_Msk (0xfful << UTCPD_ADGTM_ADGTM_Pos) /*!< UTCPD_T::ADGTM: ADGTM Mask */ 1833 1834 #define UTCPD_VSAFE0V_VSAFE0V_Pos (0) /*!< UTCPD_T::VSAFE0V: VSAFE0V Position */ 1835 #define UTCPD_VSAFE0V_VSAFE0V_Msk (0x3fful << UTCPD_VSAFE0V_VSAFE0V_Pos) /*!< UTCPD_T::VSAFE0V: VSAFE0V Mask */ 1836 1837 #define UTCPD_VSAFE5V_VSAFE5V_Pos (0) /*!< UTCPD_T::VSAFE5V: VSAFE5V Position */ 1838 #define UTCPD_VSAFE5V_VSAFE5V_Msk (0x3fful << UTCPD_VSAFE5V_VSAFE5V_Pos) /*!< UTCPD_T::VSAFE5V: VSAFE5V Mask */ 1839 1840 #define UTCPD_RATIO_DRPRATIO_Pos (0) /*!< UTCPD_T::RATIO: DRPRATIO Position */ 1841 #define UTCPD_RATIO_DRPRATIO_Msk (0x7ul << UTCPD_RATIO_DRPRATIO_Pos) /*!< UTCPD_T::RATIO: DRPRATIO Mask */ 1842 1843 #define UTCPD_RATIO_VBSEL_Pos (3) /*!< UTCPD_T::RATIO: VBSEL Position */ 1844 #define UTCPD_RATIO_VBSEL_Msk (0x1ul << UTCPD_RATIO_VBSEL_Pos) /*!< UTCPD_T::RATIO: VBSEL Mask */ 1845 1846 #define UTCPD_RATIO_ADCAVG_Pos (6) /*!< UTCPD_T::RATIO: ADCAVG Position */ 1847 #define UTCPD_RATIO_ADCAVG_Msk (0x1ul << UTCPD_RATIO_ADCAVG_Pos) /*!< UTCPD_T::RATIO: ADCAVG Mask */ 1848 1849 #define UTCPD_INTFRAME_INTFRAME_Pos (0) /*!< UTCPD_T::INTFRAME: INTFRAME Position */ 1850 #define UTCPD_INTFRAME_INTFRAME_Msk (0xfful << UTCPD_INTFRAME_INTFRAME_Pos) /*!< UTCPD_T::INTFRAME: INTFRAME Mask */ 1851 1852 #define UTCPD_VBOVTH_VBOVTH_Pos (0) /*!< UTCPD_T::VBOVTH: VBOVTH Position */ 1853 #define UTCPD_VBOVTH_VBOVTH_Msk (0x3fful << UTCPD_VBOVTH_VBOVTH_Pos) /*!< UTCPD_T::VBOVTH: VBOVTH Mask */ 1854 1855 #define UTCPD_VNDINIT_DVCAPDEF_Pos (4) /*!< UTCPD_T::VNDINIT: DVCAPDEF Position */ 1856 #define UTCPD_VNDINIT_DVCAPDEF_Msk (0x7ul << UTCPD_VNDINIT_DVCAPDEF_Pos) /*!< UTCPD_T::VNDINIT: DVCAPDEF Mask */ 1857 1858 #define UTCPD_BMCTXBP_BMCTXBP_Pos (0) /*!< UTCPD_T::BMCTXBP: BMCTXBP Position */ 1859 #define UTCPD_BMCTXBP_BMCTXBP_Msk (0xfful << UTCPD_BMCTXBP_BMCTXBP_Pos) /*!< UTCPD_T::BMCTXBP: BMCTXBP Mask */ 1860 1861 #define UTCPD_BMCTXDU_DUOFFS2_Pos (0) /*!< UTCPD_T::BMCTXDU: DUOFFS2 Position */ 1862 #define UTCPD_BMCTXDU_DUOFFS2_Msk (0x7ful << UTCPD_BMCTXDU_DUOFFS2_Pos) /*!< UTCPD_T::BMCTXDU: DUOFFS2 Mask */ 1863 1864 #define UTCPD_BMCTXDU_DUOFFS1_Pos (7) /*!< UTCPD_T::BMCTXDU: DUOFFS1 Position */ 1865 #define UTCPD_BMCTXDU_DUOFFS1_Msk (0x1ul << UTCPD_BMCTXDU_DUOFFS1_Pos) /*!< UTCPD_T::BMCTXDU: DUOFFS1 Mask */ 1866 1867 #define UTCPD_VCPSVOL_VCPSVOL_Pos (0) /*!< UTCPD_T::VCPSVOL: VCPSVOL Position */ 1868 #define UTCPD_VCPSVOL_VCPSVOL_Msk (0x3fful << UTCPD_VCPSVOL_VCPSVOL_Pos) /*!< UTCPD_T::VCPSVOL: VCPSVOL Mask */ 1869 1870 #define UTCPD_VCUV_VCUV_Pos (0) /*!< UTCPD_T::VCUV: VCUV Position */ 1871 #define UTCPD_VCUV_VCUV_Msk (0x3fful << UTCPD_VCUV_VCUV_Pos) /*!< UTCPD_T::VCUV: VCUV Mask */ 1872 1873 #define UTCPD_BMCSLICE_SLICEL_Pos (0) /*!< UTCPD_T::BMCSLICE: SLICEL Position */ 1874 #define UTCPD_BMCSLICE_SLICEL_Msk (0x3ul << UTCPD_BMCSLICE_SLICEL_Pos) /*!< UTCPD_T::BMCSLICE: SLICEL Mask */ 1875 1876 #define UTCPD_BMCSLICE_SLICEH_Pos (2) /*!< UTCPD_T::BMCSLICE: SLICEH Position */ 1877 #define UTCPD_BMCSLICE_SLICEH_Msk (0x3ul << UTCPD_BMCSLICE_SLICEH_Pos) /*!< UTCPD_T::BMCSLICE: SLICEH Mask */ 1878 1879 #define UTCPD_BMCSLICE_SLICEM_Pos (4) /*!< UTCPD_T::BMCSLICE: SLICEM Position */ 1880 #define UTCPD_BMCSLICE_SLICEM_Msk (0x7ul << UTCPD_BMCSLICE_SLICEM_Pos) /*!< UTCPD_T::BMCSLICE: SLICEM Mask */ 1881 1882 #define UTCPD_BMCSLICE_TRIMRD_Pos (8) /*!< UTCPD_T::BMCSLICE: TRIMRD Position */ 1883 #define UTCPD_BMCSLICE_TRIMRD_Msk (0x7ul << UTCPD_BMCSLICE_TRIMRD_Pos) /*!< UTCPD_T::BMCSLICE: TRIMRD Mask */ 1884 1885 #define UTCPD_BMCSLICE_TRIMRP_Pos (12) /*!< UTCPD_T::BMCSLICE: TRIMRP Position */ 1886 #define UTCPD_BMCSLICE_TRIMRP_Msk (0xful << UTCPD_BMCSLICE_TRIMRP_Pos) /*!< UTCPD_T::BMCSLICE: TRIMRP Mask */ 1887 1888 #define UTCPD_BMCSLICE_TRIMV1P1_Pos (16) /*!< UTCPD_T::BMCSLICE: TRIMV1P1 Position */ 1889 #define UTCPD_BMCSLICE_TRIMV1P1_Msk (0x7ul << UTCPD_BMCSLICE_TRIMV1P1_Pos) /*!< UTCPD_T::BMCSLICE: TRIMV1P1 Mask */ 1890 1891 #define UTCPD_BMCSLICE_TRIMVB10_Pos (20) /*!< UTCPD_T::BMCSLICE: TRIMVB10 Position */ 1892 #define UTCPD_BMCSLICE_TRIMVB10_Msk (0x7ul << UTCPD_BMCSLICE_TRIMVB10_Pos) /*!< UTCPD_T::BMCSLICE: TRIMVB10 Mask */ 1893 1894 #define UTCPD_BMCSLICE_TRIMVB20_Pos (24) /*!< UTCPD_T::BMCSLICE: TRIMVB20 Position */ 1895 #define UTCPD_BMCSLICE_TRIMVB20_Msk (0x7ul << UTCPD_BMCSLICE_TRIMVB20_Pos) /*!< UTCPD_T::BMCSLICE: TRIMVB20 Mask */ 1896 1897 #define UTCPD_BMCSLICE_VTRIM_Pos (28) /*!< UTCPD_T::BMCSLICE: VTRIM Position */ 1898 #define UTCPD_BMCSLICE_VTRIM_Msk (0xful << UTCPD_BMCSLICE_VTRIM_Pos) /*!< UTCPD_T::BMCSLICE: VTRIM Mask */ 1899 1900 #define UTCPD_PHYCTL_PHYPWR_Pos (0) /*!< UTCPD_T::PHYCTL: PHYPWR Position */ 1901 #define UTCPD_PHYCTL_PHYPWR_Msk (0x1ul << UTCPD_PHYCTL_PHYPWR_Pos) /*!< UTCPD_T::PHYCTL: PHYPWR Mask */ 1902 1903 #define UTCPD_PHYCTL_DBCTL_Pos (1) /*!< UTCPD_T::PHYCTL: DBCTL Position */ 1904 #define UTCPD_PHYCTL_DBCTL_Msk (0x1ul << UTCPD_PHYCTL_DBCTL_Pos) /*!< UTCPD_T::PHYCTL: DBCTL Mask */ 1905 1906 #define UTCPD_FRSRXCTL_FRSTX_Pos (0) /*!< UTCPD_T::FRSRXCTL: FRSTX Position */ 1907 #define UTCPD_FRSRXCTL_FRSTX_Msk (0x1ul << UTCPD_FRSRXCTL_FRSTX_Pos) /*!< UTCPD_T::FRSRXCTL: FRSTX Mask */ 1908 1909 #define UTCPD_FRSRXCTL_FRSDVVB_Pos (2) /*!< UTCPD_T::FRSRXCTL: FRSDVVB Position */ 1910 #define UTCPD_FRSRXCTL_FRSDVVB_Msk (0x1ul << UTCPD_FRSRXCTL_FRSDVVB_Pos) /*!< UTCPD_T::FRSRXCTL: FRSDVVB Mask */ 1911 1912 #define UTCPD_FRSRXCTL_FRSRXEN_Pos (3) /*!< UTCPD_T::FRSRXCTL: FRSRXEN Position */ 1913 #define UTCPD_FRSRXCTL_FRSRXEN_Msk (0x1ul << UTCPD_FRSRXCTL_FRSRXEN_Pos) /*!< UTCPD_T::FRSRXCTL: FRSRXEN Mask */ 1914 1915 #define UTCPD_VCVOL_VCVOL_Pos (0) /*!< UTCPD_T::VCVOL: VCVOL Position */ 1916 #define UTCPD_VCVOL_VCVOL_Msk (0x3fful << UTCPD_VCVOL_VCVOL_Pos) /*!< UTCPD_T::VCVOL: VCVOL Mask */ 1917 1918 #define UTCPD_CLKINFO_ReadyFlag_Pos (0) /*!< UTCPD_T::CLKINFO: ReadyFlag Position */ 1919 #define UTCPD_CLKINFO_ReadyFlag_Msk (0x1ul << UTCPD_CLKINFO_ReadyFlag_Pos) /*!< UTCPD_T::CLKINFO: ReadyFlag Mask */ 1920 1921 #define UTCPD_CLKINFO_WKEN_Pos (4) /*!< UTCPD_T::CLKINFO: WKEN Position */ 1922 #define UTCPD_CLKINFO_WKEN_Msk (0x1ul << UTCPD_CLKINFO_WKEN_Pos) /*!< UTCPD_T::CLKINFO: WKEN Mask */ 1923 1924 /**@}*/ /* UTCPD_CONST */ 1925 /**@}*/ /* end of UTCPD register group */ 1926 1927 1928 /**@}*/ /* end of REGISTER group */ 1929
