1 /* USER CODE BEGIN Header */ 2 /** 3 ****************************************************************************** 4 * @file debug_config.h 5 * @author MCD Application Team 6 * @brief Real Time Debug module general configuration file 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 /* USER CODE END Header */ 20 #ifndef DEBUG_CONFIG_H 21 #define DEBUG_CONFIG_H 22 23 #include "app_conf.h" 24 25 #if(CFG_RT_DEBUG_GPIO_MODULE == 1) 26 27 /***********************************/ 28 /** Debug configuration selection **/ 29 /***********************************/ 30 /* Debug configuration for System purpose */ 31 #define USE_RT_DEBUG_CONFIGURATION_SYSTEM (0) 32 33 /* Debug configuration for BLE purpose */ 34 #define USE_RT_DEBUG_CONFIGURATION_BLE (0) 35 36 /* Debug configuration for MAC purpose */ 37 #define USE_RT_DEBUG_CONFIGURATION_MAC (0) 38 39 /* Debug configuration for COEX purpose */ 40 #define USE_RT_DEBUG_CONFIGURATION_COEX (0) 41 42 /*********************************/ 43 /** GPIO debug signal selection **/ 44 /*********************************/ 45 46 /* System clock manager - System clock config */ 47 #define USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG (0) 48 #define GPIO_DEBUG_SCM_SYSTEM_CLOCK_CONFIG {GPIOA, GPIO_PIN_12} 49 50 /* System clock manager - Setup */ 51 #define USE_RT_DEBUG_SCM_SETUP (0) 52 #define GPIO_DEBUG_SCM_SETUP {GPIOA, GPIO_PIN_5} 53 54 /* System clock manager - HSE RDY interrupt handling */ 55 #define USE_RT_DEBUG_SCM_HSERDY_ISR (0) 56 #define GPIO_DEBUG_SCM_HSERDY_ISR {GPIOA, GPIO_PIN_15} 57 58 #define USE_RT_DEBUG_ADC_ACTIVATION (0) 59 #define GPIO_DEBUG_ADC_ACTIVATION {GPIOB, GPIO_PIN_4} 60 61 #define USE_RT_DEBUG_ADC_DEACTIVATION (0) 62 #define GPIO_DEBUG_ADC_DEACTIVATION {GPIOA, GPIO_PIN_0} 63 64 #define USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION (0) 65 #define GPIO_DEBUG_ADC_TEMPERATURE_ACQUISITION {GPIOB, GPIO_PIN_8} 66 67 #define USE_RT_DEBUG_RNG_ENABLE (0) 68 #define GPIO_DEBUG_RNG_ENABLE {GPIOA, GPIO_PIN_0} 69 70 #define USE_RT_DEBUG_RNG_DISABLE (0) 71 #define GPIO_DEBUG_RNG_DISABLE {GPIOA, GPIO_PIN_0} 72 73 #define USE_RT_DEBUG_RNG_GEN_RAND_NUM (0) 74 #define GPIO_DEBUG_RNG_GEN_RAND_NUM {GPIOB, GPIO_PIN_12} 75 76 #define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ENTER (0) 77 #define GPIO_DEBUG_LOW_POWER_STOP_MODE_ENTER {GPIOA, GPIO_PIN_0} 78 79 #define USE_RT_DEBUG_LOW_POWER_STOP_MODE_EXIT (0) 80 #define GPIO_DEBUG_LOW_POWER_STOP_MODE_EXIT {GPIOA, GPIO_PIN_0} 81 82 #define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE (0) 83 #define GPIO_DEBUG_LOW_POWER_STOP_MODE_ACTIVE {GPIOB, GPIO_PIN_3} 84 85 #define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ENTER (0) 86 #define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ENTER {GPIOA, GPIO_PIN_0} 87 88 #define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_EXIT (0) 89 #define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_EXIT {GPIOA, GPIO_PIN_0} 90 91 #define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE (0) 92 #define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE {GPIOB, GPIO_PIN_15} 93 94 #define USE_RT_DEBUG_HCI_READ_DONE (0) 95 #define GPIO_DEBUG_HCI_READ_DONE {GPIOA, GPIO_PIN_0} 96 97 #define USE_RT_DEBUG_HCI_RCVD_CMD (0) 98 #define GPIO_DEBUG_HCI_RCVD_CMD {GPIOA, GPIO_PIN_0} 99 100 #define USE_RT_DEBUG_HCI_WRITE_DONE (0) 101 #define GPIO_DEBUG_HCI_WRITE_DONE {GPIOA, GPIO_PIN_0} 102 103 #define USE_RT_DEBUG_SCHDLR_EVNT_UPDATE (0) 104 #define GPIO_DEBUG_SCHDLR_EVNT_UPDATE {GPIOA, GPIO_PIN_0} 105 106 #define USE_RT_DEBUG_SCHDLR_TIMER_SET (0) 107 #define GPIO_DEBUG_SCHDLR_TIMER_SET {GPIOA, GPIO_PIN_0} 108 109 #define USE_RT_DEBUG_SCHDLR_PHY_CLBR_TIMER (0) 110 #define GPIO_DEBUG_SCHDLR_PHY_CLBR_TIMER {GPIOA, GPIO_PIN_0} 111 112 #define USE_RT_DEBUG_SCHDLR_EVNT_SKIPPED (0) 113 #define GPIO_DEBUG_SCHDLR_EVNT_SKIPPED {GPIOA, GPIO_PIN_0} 114 115 #define USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE (0) 116 #define GPIO_DEBUG_SCHDLR_HNDL_NXT_TRACE {GPIOA, GPIO_PIN_12} 117 118 #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED (0) 119 #define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED {GPIOA, GPIO_PIN_0} 120 121 #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK (0) 122 #define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK {GPIOA, GPIO_PIN_0} 123 124 #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK (0) 125 #define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK {GPIOA, GPIO_PIN_0} 126 127 #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE (0) 128 #define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE {GPIOA, GPIO_PIN_0} 129 130 #define USE_RT_DEBUG_SCHDLR_EVNT_RGSTR (0) 131 #define GPIO_DEBUG_SCHDLR_EVNT_RGSTR {GPIOB, GPIO_PIN_8} 132 133 #define USE_RT_DEBUG_SCHDLR_ADD_CONFLICT_Q (0) 134 #define GPIO_DEBUG_SCHDLR_ADD_CONFLICT_Q {GPIOA, GPIO_PIN_0} 135 136 #define USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT (0) 137 #define GPIO_DEBUG_SCHDLR_HNDL_MISSED_EVNT {GPIOA, GPIO_PIN_5} 138 139 #define USE_RT_DEBUG_SCHDLR_UNRGSTR_EVNT (0) 140 #define GPIO_DEBUG_SCHDLR_UNRGSTR_EVNT {GPIOA, GPIO_PIN_0} 141 142 #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE (0) 143 #define GPIO_DEBUG_SCHDLR_EXEC_EVNT_TRACE {GPIOA, GPIO_PIN_15} 144 145 #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_PROFILE (0) 146 #define GPIO_DEBUG_SCHDLR_EXEC_EVNT_PROFILE {GPIOA, GPIO_PIN_0} 147 148 #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_ERROR (0) 149 #define GPIO_DEBUG_SCHDLR_EXEC_EVNT_ERROR {GPIOA, GPIO_PIN_0} 150 151 #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING (0) 152 #define GPIO_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING {GPIOA, GPIO_PIN_0} 153 154 #define USE_RT_DEBUG_LLHWC_CMN_CLR_ISR (0) 155 #define GPIO_DEBUG_LLHWC_CMN_CLR_ISR {GPIOA, GPIO_PIN_0} 156 157 #define USE_RT_DEBUG_LLWCC_CMN_HG_ISR (0) 158 #define GPIO_DEBUG_LLWCC_CMN_HG_ISR {GPIOA, GPIO_PIN_15} 159 160 #define USE_RT_DEBUG_LLHWC_CMN_LW_ISR (0) 161 #define GPIO_DEBUG_LLHWC_CMN_LW_ISR {GPIOA, GPIO_PIN_12} 162 163 #define USE_RT_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR (0) 164 #define GPIO_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR {GPIOA, GPIO_PIN_0} 165 166 #define USE_RT_DEBUG_LLHWC_LL_ISR (0) 167 #define GPIO_DEBUG_LLHWC_LL_ISR {GPIOA, GPIO_PIN_0} 168 169 #define USE_RT_DEBUG_LLHWC_SPLTMR_SET (0) 170 #define GPIO_DEBUG_LLHWC_SPLTMR_SET {GPIOA, GPIO_PIN_0} 171 172 #define USE_RT_DEBUG_LLHWC_SPLTMR_GET (0) 173 #define GPIO_DEBUG_LLHWC_SPLTMR_GET {GPIOA, GPIO_PIN_0} 174 175 #define USE_RT_DEBUG_LLHWC_LOW_ISR (0) 176 #define GPIO_DEBUG_LLHWC_LOW_ISR {GPIOA, GPIO_PIN_0} 177 178 #define USE_RT_DEBUG_LLHWC_STOP_SCN (0) 179 #define GPIO_DEBUG_LLHWC_STOP_SCN {GPIOA, GPIO_PIN_0} 180 181 #define USE_RT_DEBUG_LLHWC_WAIT_ENVT_ON_AIR (0) 182 #define GPIO_DEBUG_LLHWC_WAIT_ENVT_ON_AIR {GPIOA, GPIO_PIN_0} 183 184 #define USE_RT_DEBUG_LLHWC_SET_CONN_EVNT_PARAM (0) 185 #define GPIO_DEBUG_LLHWC_SET_CONN_EVNT_PARAM {GPIOA, GPIO_PIN_0} 186 187 #define USE_RT_DEBUG_POST_EVNT (0) 188 #define GPIO_DEBUG_POST_EVNT {GPIOA, GPIO_PIN_0} 189 190 #define USE_RT_DEBUG_HNDL_ALL_EVNTS (0) 191 #define GPIO_DEBUG_HNDL_ALL_EVNTS {GPIOA, GPIO_PIN_0} 192 193 #define USE_RT_DEBUG_PROCESS_EVNT (0) 194 #define GPIO_DEBUG_PROCESS_EVNT {GPIOA, GPIO_PIN_0} 195 196 #define USE_RT_DEBUG_PROCESS_ISO_DATA (0) 197 #define GPIO_DEBUG_PROCESS_ISO_DATA {GPIOA, GPIO_PIN_0} 198 199 #define USE_RT_DEBUG_ALLOC_TX_ISO_EMPTY_PKT (0) 200 #define GPIO_DEBUG_ALLOC_TX_ISO_EMPTY_PKT {GPIOA, GPIO_PIN_0} 201 202 #define USE_RT_DEBUG_BIG_FREE_EMPTY_PKTS (0) 203 #define GPIO_DEBUG_BIG_FREE_EMPTY_PKTS {GPIOA, GPIO_PIN_0} 204 205 #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_OK (0) 206 #define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_OK {GPIOA, GPIO_PIN_0} 207 208 #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_CRC (0) 209 #define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_CRC {GPIOA, GPIO_PIN_0} 210 211 #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX (0) 212 #define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX {GPIOA, GPIO_PIN_0} 213 214 #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE (0) 215 #define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE {GPIOA, GPIO_PIN_0} 216 217 #define USE_RT_DEBUG_ISO_HNDL_SDU (0) 218 #define GPIO_DEBUG_ISO_HNDL_SDU {GPIOA, GPIO_PIN_0} 219 220 #define USE_RT_DEBUG_LL_INTF_INIT (0) 221 #define GPIO_DEBUG_LL_INTF_INIT {GPIOA, GPIO_PIN_0} 222 223 #define USE_RT_DEBUG_DATA_TO_CNTRLR (0) 224 #define GPIO_DEBUG_DATA_TO_CNTRLR {GPIOA, GPIO_PIN_0} 225 226 #define USE_RT_DEBUG_FREE_LL_PKT_HNDLR (0) 227 #define GPIO_DEBUG_FREE_LL_PKT_HNDLR {GPIOA, GPIO_PIN_0} 228 229 #define USE_RT_DEBUG_PHY_INIT_CLBR_TRACE (0) 230 #define GPIO_DEBUG_PHY_INIT_CLBR_TRACE {GPIOA, GPIO_PIN_0} 231 232 #define USE_RT_DEBUG_PHY_RUNTIME_CLBR_TRACE (0) 233 #define GPIO_DEBUG_PHY_RUNTIME_CLBR_TRACE {GPIOA, GPIO_PIN_0} 234 235 #define USE_RT_DEBUG_PHY_CLBR_ISR (0) 236 #define GPIO_DEBUG_PHY_CLBR_ISR {GPIOB, GPIO_PIN_3} 237 238 #define USE_RT_DEBUG_PHY_INIT_CLBR_SINGLE_CH (0) 239 #define GPIO_DEBUG_PHY_INIT_CLBR_SINGLE_CH {GPIOA, GPIO_PIN_0} 240 241 #define USE_RT_DEBUG_PHY_CLBR_STRTD (0) 242 #define GPIO_DEBUG_PHY_CLBR_STRTD {GPIOA, GPIO_PIN_0} 243 244 #define USE_RT_DEBUG_PHY_CLBR_EXEC (0) 245 #define GPIO_DEBUG_PHY_CLBR_EXEC {GPIOB, GPIO_PIN_4} 246 247 #define USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV (0) 248 #define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV {GPIOA, GPIO_PIN_0} 249 250 #define USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR (0) 251 #define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR {GPIOA, GPIO_PIN_0} 252 253 #define USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT (0) 254 #define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT {GPIOA, GPIO_PIN_0} 255 256 #define USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE (0) 257 #define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE {GPIOA, GPIO_PIN_0} 258 259 #define USE_RT_DEBUG_RCO_ISR_TRACE (0) 260 #define GPIO_DEBUG_RCO_ISR_TRACE {GPIOA, GPIO_PIN_0} 261 262 #define USE_RT_DEBUG_RCO_ISR_COMPENDATE (0) 263 #define GPIO_DEBUG_RCO_ISR_COMPENDATE {GPIOA, GPIO_PIN_0} 264 265 #define USE_RT_DEBUG_RAL_STRT_TX (0) 266 #define GPIO_DEBUG_RAL_STRT_TX {GPIOA, GPIO_PIN_5} 267 268 #define USE_RT_DEBUG_RAL_ISR_TIMER_ERROR (0) 269 #define GPIO_DEBUG_RAL_ISR_TIMER_ERROR {GPIOA, GPIO_PIN_0} 270 271 #define USE_RT_DEBUG_RAL_ISR_TRACE (0) 272 #define GPIO_DEBUG_RAL_ISR_TRACE {GPIOB, GPIO_PIN_3} 273 274 #define USE_RT_DEBUG_RAL_STOP_OPRTN (0) 275 #define GPIO_DEBUG_RAL_STOP_OPRTN {GPIOB, GPIO_PIN_8} 276 277 #define USE_RT_DEBUG_RAL_STRT_RX (0) 278 #define GPIO_DEBUG_RAL_STRT_RX {GPIOB, GPIO_PIN_12} 279 280 #define USE_RT_DEBUG_RAL_DONE_CLBK_TX (0) 281 #define GPIO_DEBUG_RAL_DONE_CLBK_TX {GPIOA, GPIO_PIN_0} 282 283 #define USE_RT_DEBUG_RAL_DONE_CLBK_RX (0) 284 #define GPIO_DEBUG_RAL_DONE_CLBK_RX {GPIOA, GPIO_PIN_0} 285 286 #define USE_RT_DEBUG_RAL_DONE_CLBK_ED (0) 287 #define GPIO_DEBUG_RAL_DONE_CLBK_ED {GPIOA, GPIO_PIN_0} 288 289 #define USE_RT_DEBUG_RAL_ED_SCAN (0) 290 #define GPIO_DEBUG_RAL_ED_SCAN {GPIOA, GPIO_PIN_0} 291 292 #define USE_RT_DEBUG_ERROR_MEM_CAP_EXCED (0) 293 #define GPIO_DEBUG_ERROR_MEM_CAP_EXCED {GPIOA, GPIO_PIN_0} 294 295 #define USE_RT_DEBUG_ERROR_COMMAND_DISALLOWED (0) 296 #define GPIO_DEBUG_ERROR_COMMAND_DISALLOWED {GPIOA, GPIO_PIN_0} 297 298 #define USE_RT_DEBUG_PTA_INIT (0) 299 #define GPIO_DEBUG_PTA_INIT {GPIOA, GPIO_PIN_0} 300 301 #define USE_RT_DEBUG_PTA_EN (0) 302 #define GPIO_DEBUG_PTA_EN {GPIOA, GPIO_PIN_0} 303 304 #define USE_RT_DEBUG_LLHWC_PTA_SET_EN (0) 305 #define GPIO_DEBUG_LLHWC_PTA_SET_EN {GPIOA, GPIO_PIN_0} 306 307 #define USE_RT_DEBUG_LLHWC_PTA_SET_PARAMS (0) 308 #define GPIO_DEBUG_LLHWC_PTA_SET_PARAMS {GPIOA, GPIO_PIN_0} 309 310 #define USE_RT_DEBUG_COEX_STRT_ON_IDLE (0) 311 #define GPIO_DEBUG_COEX_STRT_ON_IDLE {GPIOB, GPIO_PIN_15} 312 313 #define USE_RT_DEBUG_COEX_ASK_FOR_AIR (0) 314 #define GPIO_DEBUG_COEX_ASK_FOR_AIR {GPIOB, GPIO_PIN_3} 315 316 #define USE_RT_DEBUG_COEX_TIMER_EVNT_CLBK (0) 317 #define GPIO_DEBUG_COEX_TIMER_EVNT_CLBK {GPIOA, GPIO_PIN_0} 318 319 #define USE_RT_DEBUG_COEX_STRT_ONE_SHOT (0) 320 #define GPIO_DEBUG_COEX_STRT_ONE_SHOT {GPIOA, GPIO_PIN_5} 321 322 #define USE_RT_DEBUG_COEX_FORCE_STOP_RX (0) 323 #define GPIO_DEBUG_COEX_FORCE_STOP_RX {GPIOB, GPIO_PIN_12} 324 325 #define USE_RT_DEBUG_LLHWC_ADV_DONE (0) 326 #define GPIO_DEBUG_LLHWC_ADV_DONE {GPIOA, GPIO_PIN_0} 327 328 #define USE_RT_DEBUG_LLHWC_SCN_DONE (0) 329 #define GPIO_DEBUG_LLHWC_SCN_DONE {GPIOA, GPIO_PIN_0} 330 331 #define USE_RT_DEBUG_LLHWC_INIT_DONE (0) 332 #define GPIO_DEBUG_LLHWC_INIT_DONE {GPIOA, GPIO_PIN_0} 333 334 #define USE_RT_DEBUG_LLHWC_CONN_DONE (0) 335 #define GPIO_DEBUG_LLHWC_CONN_DONE {GPIOA, GPIO_PIN_0} 336 337 #define USE_RT_DEBUG_LLHWC_CIG_DONE (0) 338 #define GPIO_DEBUG_LLHWC_CIG_DONE {GPIOA, GPIO_PIN_0} 339 340 #define USE_RT_DEBUG_LLHWC_BIG_DONE (0) 341 #define GPIO_DEBUG_LLHWC_BIG_DONE {GPIOA, GPIO_PIN_0} 342 343 #define USE_RT_DEBUG_OS_TMR_CREATE (0) 344 #define GPIO_DEBUG_OS_TMR_CREATE {GPIOA, GPIO_PIN_0} 345 346 #define USE_RT_DEBUG_ADV_EXT_TIMEOUT_CBK (0) 347 #define GPIO_DEBUG_ADV_EXT_TIMEOUT_CBK {GPIOA, GPIO_PIN_0} 348 349 #define USE_RT_DEBUG_ADV_EXT_SCN_DUR_CBK (0) 350 #define GPIO_DEBUG_ADV_EXT_SCN_DUR_CBK {GPIOA, GPIO_PIN_0} 351 352 #define USE_RT_DEBUG_ADV_EXT_SCN_PERIOD_CBK (0) 353 #define GPIO_DEBUG_ADV_EXT_SCN_PERIOD_CBK {GPIOA, GPIO_PIN_0} 354 355 #define USE_RT_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK (0) 356 #define GPIO_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK {GPIOA, GPIO_PIN_0} 357 358 #define USE_RT_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK (0) 359 #define GPIO_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK {GPIOA, GPIO_PIN_0} 360 361 #define USE_RT_DEBUG_BIS_TERM_TMR_CBK (0) 362 #define GPIO_DEBUG_BIS_TERM_TMR_CBK {GPIOA, GPIO_PIN_0} 363 364 #define USE_RT_DEBUG_BIS_TST_MODE_CBK (0) 365 #define GPIO_DEBUG_BIS_TST_MODE_CBK {GPIOA, GPIO_PIN_0} 366 367 #define USE_RT_DEBUG_BIS_TST_MODE_TMR_CBK (0) 368 #define GPIO_DEBUG_BIS_TST_MODE_TMR_CBK {GPIOA, GPIO_PIN_0} 369 370 #define USE_RT_DEBUG_ISO_POST_TMR_CBK (0) 371 #define GPIO_DEBUG_ISO_POST_TMR_CBK {GPIOA, GPIO_PIN_0} 372 373 #define USE_RT_DEBUG_ISO_TST_MODE_TMR_CBK (0) 374 #define GPIO_DEBUG_ISO_TST_MODE_TMR_CBK {GPIOA, GPIO_PIN_0} 375 376 #define USE_RT_DEBUG_CONN_POST_TMR_CBK (0) 377 #define GPIO_DEBUG_CONN_POST_TMR_CBK {GPIOA, GPIO_PIN_0} 378 379 #define USE_RT_DEBUG_EVNT_SCHDLR_TMR_CBK (0) 380 #define GPIO_DEBUG_EVNT_SCHDLR_TMR_CBK {GPIOA, GPIO_PIN_0} 381 382 #define USE_RT_DEBUG_HCI_POST_TMR_CBK (0) 383 #define GPIO_DEBUG_HCI_POST_TMR_CBK {GPIOA, GPIO_PIN_0} 384 385 #define USE_RT_DEBUG_LLCP_POST_TMR_CBK (0) 386 #define GPIO_DEBUG_LLCP_POST_TMR_CBK {GPIOA, GPIO_PIN_0} 387 388 #define USE_RT_DEBUG_LLHWC_ENRGY_DETECT_CBK (0) 389 #define GPIO_DEBUG_LLHWC_ENRGY_DETECT_CBK {GPIOA, GPIO_PIN_0} 390 391 #define USE_RT_DEBUG_PRVCY_POST_TMR_CBK (0) 392 #define GPIO_DEBUG_PRVCY_POST_TMR_CBK {GPIOA, GPIO_PIN_0} 393 394 #define USE_RT_DEBUG_ANT_PRPR_TMR_CBK (0) 395 #define GPIO_DEBUG_ANT_PRPR_TMR_CBK {GPIOA, GPIO_PIN_0} 396 397 #define USE_RT_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK (0) 398 #define GPIO_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK {GPIOA, GPIO_PIN_0} 399 400 #define USE_RT_DEBUG_MLME_RX_EN_TMR_CBK (0) 401 #define GPIO_DEBUG_MLME_RX_EN_TMR_CBK {GPIOA, GPIO_PIN_0} 402 403 #define USE_RT_DEBUG_MLME_GNRC_TMR_CBK (0) 404 #define GPIO_DEBUG_MLME_GNRC_TMR_CBK {GPIOA, GPIO_PIN_0} 405 406 #define USE_RT_DEBUG_MIB_JOIN_LST_TMR_CBK (0) 407 #define GPIO_DEBUG_MIB_JOIN_LST_TMR_CBK {GPIOA, GPIO_PIN_0} 408 409 #define USE_RT_DEBUG_MLME_PWR_PRES_TMR_CBK (0) 410 #define GPIO_DEBUG_MLME_PWR_PRES_TMR_CBK {GPIOA, GPIO_PIN_0} 411 412 #define USE_RT_DEBUG_PRESISTENCE_TMR_CBK (0) 413 #define GPIO_DEBUG_PRESISTENCE_TMR_CBK {GPIOA, GPIO_PIN_0} 414 415 #define USE_RT_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK (0) 416 #define GPIO_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK {GPIOA, GPIO_PIN_0} 417 418 #define USE_RT_DEBUG_RADIO_CSMA_TMR_CBK (0) 419 #define GPIO_DEBUG_RADIO_CSMA_TMR_CBK {GPIOA, GPIO_PIN_0} 420 421 #define USE_RT_DEBUG_RADIO_CSL_RCV_TMR_CBK (0) 422 #define GPIO_DEBUG_RADIO_CSL_RCV_TMR_CBK {GPIOA, GPIO_PIN_0} 423 424 #define USE_RT_DEBUG_ED_TMR_CBK (0) 425 #define GPIO_DEBUG_ED_TMR_CBK {GPIOA, GPIO_PIN_0} 426 427 #define USE_RT_DEBUG_DIO_EXT_TMR_CBK (0) 428 #define GPIO_DEBUG_DIO_EXT_TMR_CBK {GPIOA, GPIO_PIN_0} 429 430 #define USE_RT_DEBUG_RCO_CLBR_TMR_CBK (0) 431 #define GPIO_DEBUG_RCO_CLBR_TMR_CBK {GPIOA, GPIO_PIN_0} 432 433 #define USE_RT_DEBUG_ADV_EXT_MNGR_ADV_CBK (0) 434 #define GPIO_DEBUG_ADV_EXT_MNGR_ADV_CBK {GPIOA, GPIO_PIN_0} 435 436 #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_CBK (0) 437 #define GPIO_DEBUG_ADV_EXT_MNGR_SCN_CBK {GPIOA, GPIO_PIN_0} 438 439 #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK (0) 440 #define GPIO_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK {GPIOA, GPIO_PIN_0} 441 442 #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK (0) 443 #define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK {GPIOA, GPIO_PIN_0} 444 445 #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK (0) 446 #define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK {GPIOA, GPIO_PIN_0} 447 448 #define USE_RT_DEBUG_BIG_ADV_CBK (0) 449 #define GPIO_DEBUG_BIG_ADV_CBK {GPIOA, GPIO_PIN_0} 450 451 #define USE_RT_DEBUG_BIG_ADV_ERR_CBK (0) 452 #define GPIO_DEBUG_BIG_ADV_ERR_CBK {GPIOA, GPIO_PIN_0} 453 454 #define USE_RT_DEBUG_BIG_SYNC_CBK (0) 455 #define GPIO_DEBUG_BIG_SYNC_CBK {GPIOA, GPIO_PIN_0} 456 457 #define USE_RT_DEBUG_BIG_SYNC_ERR_CBK (0) 458 #define GPIO_DEBUG_BIG_SYNC_ERR_CBK {GPIOA, GPIO_PIN_0} 459 460 #define USE_RT_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK (0) 461 #define GPIO_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK {GPIOA, GPIO_PIN_0} 462 463 #define USE_RT_DEBUG_ISO_CIG_ERR_CBK (0) 464 #define GPIO_DEBUG_ISO_CIG_ERR_CBK {GPIOA, GPIO_PIN_0} 465 466 #define USE_RT_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK (0) 467 #define GPIO_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK {GPIOA, GPIO_PIN_0} 468 469 #define USE_RT_DEBUG_PRDC_CLBR_EXTRL_CBK (0) 470 #define GPIO_DEBUG_PRDC_CLBR_EXTRL_CBK {GPIOA, GPIO_PIN_0} 471 472 #define USE_RT_DEBUG_PTR_PRDC_ADV_SYNC_CBK (0) 473 #define GPIO_DEBUG_PTR_PRDC_ADV_SYNC_CBK {GPIOA, GPIO_PIN_0} 474 475 #define USE_RT_DEBUG_NCONN_SCN_CBK (0) 476 #define GPIO_DEBUG_NCONN_SCN_CBK {GPIOA, GPIO_PIN_0} 477 478 #define USE_RT_DEBUG_NCONN_ADV_CBK (0) 479 #define GPIO_DEBUG_NCONN_ADV_CBK {GPIOA, GPIO_PIN_0} 480 481 #define USE_RT_DEBUG_NCONN_INIT_CBK (0) 482 #define GPIO_DEBUG_NCONN_INIT_CBK {GPIOA, GPIO_PIN_0} 483 484 #define USE_RT_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK (0) 485 #define GPIO_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK {GPIOA, GPIO_PIN_0} 486 487 #define USE_RT_DEBUG_ANT_STACK_EVNT_CBK (0) 488 #define GPIO_DEBUG_ANT_STACK_EVNT_CBK {GPIOA, GPIO_PIN_0} 489 490 #define USE_RT_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK (0) 491 #define GPIO_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK {GPIOA, GPIO_PIN_0} 492 493 #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT (0) 494 #define GPIO_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT {GPIOA, GPIO_PIN_0} 495 496 #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT (0) 497 #define GPIO_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT {GPIOA, GPIO_PIN_0} 498 499 #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT (0) 500 #define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT {GPIOA, GPIO_PIN_0} 501 502 #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT (0) 503 #define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT {GPIOA, GPIO_PIN_0} 504 505 #define USE_RT_DEBUG_BIS_MNGR_BIG_TERM_CBK (0) 506 #define GPIO_DEBUG_BIS_MNGR_BIG_TERM_CBK {GPIOA, GPIO_PIN_0} 507 508 #define USE_RT_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK (0) 509 #define GPIO_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK {GPIOA, GPIO_PIN_0} 510 511 #define USE_RT_DEBUG_ISOAL_MNGR_SDU_GEN (0) 512 #define GPIO_DEBUG_ISOAL_MNGR_SDU_GEN {GPIOA, GPIO_PIN_0} 513 514 #define USE_RT_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK (0) 515 #define GPIO_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK {GPIOA, GPIO_PIN_0} 516 517 #define USE_RT_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK (0) 518 #define GPIO_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK {GPIOA, GPIO_PIN_0} 519 520 #define USE_RT_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK (0) 521 #define GPIO_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK {GPIOA, GPIO_PIN_0} 522 523 #define USE_RT_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT (0) 524 #define GPIO_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT {GPIOA, GPIO_PIN_0} 525 526 #define USE_RT_DEBUG_HCI_EVENT_HNDLR (0) 527 #define GPIO_DEBUG_HCI_EVENT_HNDLR {GPIOA, GPIO_PIN_0} 528 529 #define USE_RT_DEBUG_MLME_TMRS_CBK (0) 530 #define GPIO_DEBUG_MLME_TMRS_CBK {GPIOA, GPIO_PIN_0} 531 532 #define USE_RT_DEBUG_DIRECT_TX_EVNT_CBK (0) 533 #define GPIO_DEBUG_DIRECT_TX_EVNT_CBK {GPIOA, GPIO_PIN_0} 534 535 #define USE_RT_DEBUG_INDIRECT_PKT_TOUR_CBK (0) 536 #define GPIO_DEBUG_INDIRECT_PKT_TOUR_CBK {GPIOA, GPIO_PIN_0} 537 538 #define USE_RT_DEBUG_RADIO_CSMA_TMR (0) 539 #define GPIO_DEBUG_RADIO_CSMA_TMR {GPIOA, GPIO_PIN_0} 540 541 #define USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK (0) 542 #define GPIO_DEBUG_RAL_SM_DONE_EVNT_CBK {GPIOB, GPIO_PIN_4} 543 544 #define USE_RT_DEBUG_ED_TMR_HNDL (0) 545 #define GPIO_DEBUG_ED_TMR_HNDL {GPIOA, GPIO_PIN_0} 546 547 #define USE_RT_DEBUG_OS_TMR_EVNT_CBK (0) 548 #define GPIO_DEBUG_OS_TMR_EVNT_CBK {GPIOA, GPIO_PIN_0} 549 550 #define USE_RT_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME (0) 551 #define GPIO_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME {GPIOA, GPIO_PIN_0} 552 553 #define USE_RT_DEBUG_PROFILE_END_DRIFT_TIME (0) 554 #define GPIO_DEBUG_PROFILE_END_DRIFT_TIME {GPIOA, GPIO_PIN_0} 555 556 #define USE_RT_DEBUG_PROC_RADIO_RCV (0) 557 #define GPIO_DEBUG_PROC_RADIO_RCV {GPIOA, GPIO_PIN_0} 558 559 #define USE_RT_DEBUG_EVNT_TIME_UPDT (0) 560 #define GPIO_DEBUG_EVNT_TIME_UPDT {GPIOA, GPIO_PIN_0} 561 562 #define USE_RT_DEBUG_MAC_RECEIVE_DONE (0) 563 #define GPIO_DEBUG_MAC_RECEIVE_DONE {GPIOA, GPIO_PIN_0} 564 565 #define USE_RT_DEBUG_MAC_TX_DONE (0) 566 #define GPIO_DEBUG_MAC_TX_DONE {GPIOA, GPIO_PIN_0} 567 568 #define USE_RT_DEBUG_RADIO_APPLY_CSMA (0) 569 #define GPIO_DEBUG_RADIO_APPLY_CSMA {GPIOA, GPIO_PIN_0} 570 571 #define USE_RT_DEBUG_RADIO_TRANSMIT (0) 572 #define GPIO_DEBUG_RADIO_TRANSMIT {GPIOA, GPIO_PIN_0} 573 574 #define USE_RT_DEBUG_PROC_RADIO_TX (0) 575 #define GPIO_DEBUG_PROC_RADIO_TX {GPIOA, GPIO_PIN_0} 576 577 #define USE_RT_DEBUG_RAL_TX_DONE (0) 578 #define GPIO_DEBUG_RAL_TX_DONE {GPIOA, GPIO_PIN_0} 579 580 #define USE_RT_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT (0) 581 #define GPIO_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT {GPIOA, GPIO_PIN_0} 582 583 #define USE_RT_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT (0) 584 #define GPIO_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT {GPIOA, GPIO_PIN_0} 585 586 #define USE_RT_DEBUG_RAL_CONTINUE_RX (0) 587 #define GPIO_DEBUG_RAL_CONTINUE_RX {GPIOA, GPIO_PIN_0} 588 589 #define USE_RT_DEBUG_RAL_PERFORM_CCA (0) 590 #define GPIO_DEBUG_RAL_PERFORM_CCA {GPIOA, GPIO_PIN_0} 591 592 #define USE_RT_DEBUG_RAL_ENABLE_TRANSMITTER (0) 593 #define GPIO_DEBUG_RAL_ENABLE_TRANSMITTER {GPIOA, GPIO_PIN_0} 594 595 #define USE_RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 (0) 596 #define GPIO_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 {GPIOA, GPIO_PIN_0} 597 598 /* Application signal selection and GPIO assignment. 599 CAN BE MODIFIED BY USER */ 600 601 #define USE_RT_DEBUG_APP_APPE_INIT (1) 602 #define GPIO_DEBUG_APP_APPE_INIT {GPIOA, GPIO_PIN_0} 603 604 /********************************/ 605 /** Debug configuration setup **/ 606 /*******************************/ 607 608 /* 609 * 610 * Debug configuration for System purpose 611 * 612 */ 613 #if (USE_RT_DEBUG_CONFIGURATION_SYSTEM == 1U) 614 /* SCM_SETUP activation */ 615 #undef USE_RT_DEBUG_SCM_SETUP 616 #define USE_RT_DEBUG_SCM_SETUP (1U) 617 618 /* SCM_SYSTEM_CLOCK_CONFIG activation */ 619 #undef USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG 620 #define USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG (1U) 621 622 /* SCM_HSERDY_ISR activation */ 623 #undef USE_RT_DEBUG_SCM_HSERDY_ISR 624 #define USE_RT_DEBUG_SCM_HSERDY_ISR (1U) 625 626 /* LOW_POWER_STOP_MODE_ACTIVE activation */ 627 #undef USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE 628 #define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE (1U) 629 630 /* ADC_ACTIVATION activation */ 631 #undef USE_RT_DEBUG_ADC_ACTIVATION 632 #define USE_RT_DEBUG_ADC_ACTIVATION (1U) 633 634 /* ADC_TEMPERATURE_ACQUISITION activation */ 635 #undef USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION 636 #define USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION (1U) 637 638 /* RNG_GEN_RAND_NUM activation */ 639 #undef USE_RT_DEBUG_RNG_GEN_RAND_NUM 640 #define USE_RT_DEBUG_RNG_GEN_RAND_NUM (1U) 641 642 /* LOW_POWER_STANDBY_MODE_ACTIVE activation */ 643 #undef USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE 644 #define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE (1U) 645 646 /* 647 * 648 * Debug configuration for BLE purpose 649 * 650 */ 651 #elif (USE_RT_DEBUG_CONFIGURATION_BLE == 1U) 652 653 /* LLHWC_CMN_LW_ISR activation */ 654 #undef USE_RT_DEBUG_LLHWC_CMN_LW_ISR 655 #define USE_RT_DEBUG_LLHWC_CMN_LW_ISR (1U) 656 657 /* LLHWC_CMN_HG_ISR activation */ 658 #undef USE_RT_DEBUG_LLWCC_CMN_HG_ISR 659 #define USE_RT_DEBUG_LLWCC_CMN_HG_ISR (1U) 660 661 /* PHY_CLBR_EXEC activation */ 662 #undef USE_RT_DEBUG_PHY_CLBR_EXEC 663 #define USE_RT_DEBUG_PHY_CLBR_EXEC (1U) 664 665 /* SCHDLR_EVNT_RGSTR activation */ 666 #undef USE_RT_DEBUG_SCHDLR_EVNT_RGSTR 667 #define USE_RT_DEBUG_SCHDLR_EVNT_RGSTR (1U) 668 669 /* SCHDLR_HNDL_MISSED_EVNT activation */ 670 #undef USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT 671 #define USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT (1U) 672 673 /* SCHDLR_HNDL_NXT_TRACE activation */ 674 #undef USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE 675 #define USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE (1U) 676 677 /* SCHDLR_EXEC_EVNT_TRACE activation */ 678 #undef USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE 679 #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE (1U) 680 681 /* PHY_CLBR_ISR activation */ 682 #undef USE_RT_DEBUG_PHY_CLBR_ISR 683 #define USE_RT_DEBUG_PHY_CLBR_ISR (1U) 684 685 /* 686 * 687 * Debug configuration for MAC purpose 688 * 689 */ 690 #elif (USE_RT_DEBUG_CONFIGURATION_MAC == 1U) 691 692 /* LLHWC_CMN_LW_ISR activation */ 693 #undef USE_RT_DEBUG_LLHWC_CMN_LW_ISR 694 #define USE_RT_DEBUG_LLHWC_CMN_LW_ISR (1U) 695 696 /* LLHWC_CMN_HG_ISR activation */ 697 #undef USE_RT_DEBUG_LLWCC_CMN_HG_ISR 698 #define USE_RT_DEBUG_LLWCC_CMN_HG_ISR (1U) 699 700 /* RAL_ISR_TRACE activation */ 701 #undef USE_RT_DEBUG_RAL_ISR_TRACE 702 #define USE_RT_DEBUG_RAL_ISR_TRACE (1U) 703 704 /* RAL_SM_DONE_EVNT_CBK activation */ 705 #undef USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK 706 #define USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK (1U) 707 708 /* RAL_STOP_OPRTN activation */ 709 #undef USE_RT_DEBUG_RAL_STOP_OPRTN 710 #define USE_RT_DEBUG_RAL_STOP_OPRTN (1U) 711 712 /* RAL_STRT_RX activation */ 713 #undef USE_RT_DEBUG_RAL_STRT_RX 714 #define USE_RT_DEBUG_RAL_STRT_RX (1U) 715 716 /* RAL_STRT_TX activation */ 717 #undef USE_RT_DEBUG_RAL_STRT_TX 718 #define USE_RT_DEBUG_RAL_STRT_TX (1U) 719 720 /* 721 * 722 * Debug configuration for COEX purpose 723 * 724 */ 725 #elif (USE_RT_DEBUG_CONFIGURATION_COEX == 1U) 726 727 /* COEX_ASK_FOR_AIR activation */ 728 #undef USE_RT_DEBUG_COEX_ASK_FOR_AIR 729 #define USE_RT_DEBUG_COEX_ASK_FOR_AIR (1U) 730 731 /* COEX_FORCE_STOP_RX activation */ 732 #undef USE_RT_DEBUG_COEX_FORCE_STOP_RX 733 #define USE_RT_DEBUG_COEX_FORCE_STOP_RX (1U) 734 735 /* COEX_STRT_ON_IDLE activation */ 736 #undef USE_RT_DEBUG_COEX_STRT_ON_IDLE 737 #define USE_RT_DEBUG_COEX_STRT_ON_IDLE (1U) 738 739 /* COEX_STRT_ONE_SHOT activation */ 740 #undef USE_RT_DEBUG_COEX_STRT_ONE_SHOT 741 #define USE_RT_DEBUG_COEX_STRT_ONE_SHOT (1U) 742 743 /* SCHDLR_HNDL_NXT_TRACE activation */ 744 #undef USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE 745 #define USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE (1U) 746 747 /* SCHDLR_EXEC_EVNT_TRACE activation */ 748 #undef USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE 749 #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE (1U) 750 751 /* RAL_SM_DONE_EVNT_CBK activation */ 752 #undef USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK 753 #define USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK (1U) 754 755 /* RAL_STOP_OPRTN activation */ 756 #undef USE_RT_DEBUG_RAL_STOP_OPRTN 757 #define USE_RT_DEBUG_RAL_STOP_OPRTN (1U) 758 759 #else 760 /* Nothing to do */ 761 #endif /* (USE_RT_DEBUG_CONFIGURATION_COEX == 1U) */ 762 763 #endif /* CFG_RT_DEBUG_GPIO_MODULE */ 764 765 /******************************************************************/ 766 /** Association table between general debug signal and used gpio **/ 767 /******************************************************************/ 768 769 #include "debug_signals.h" 770 771 #if(CFG_RT_DEBUG_GPIO_MODULE == 1) 772 773 #include "stm32wbaxx_hal.h" 774 775 typedef struct { 776 GPIO_TypeDef* GPIO_port; 777 uint16_t GPIO_pin; 778 } st_gpio_debug_t; 779 780 static const st_gpio_debug_t general_debug_table[] = { 781 #if (USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG == 1) 782 [RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG] = GPIO_DEBUG_SCM_SYSTEM_CLOCK_CONFIG, 783 #endif /* USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG */ 784 785 #if (USE_RT_DEBUG_SCM_SETUP == 1) 786 [RT_DEBUG_SCM_SETUP] = GPIO_DEBUG_SCM_SETUP, 787 #endif /* USE_RT_DEBUG_SCM_SETUP */ 788 789 #if (USE_RT_DEBUG_SCM_HSERDY_ISR == 1) 790 [RT_DEBUG_SCM_HSERDY_ISR] = GPIO_DEBUG_SCM_HSERDY_ISR, 791 #endif /* USE_RT_DEBUG_SCM_HSERDY_ISR */ 792 793 #if (USE_RT_DEBUG_ADC_ACTIVATION == 1) 794 [RT_DEBUG_ADC_ACTIVATION] = GPIO_DEBUG_ADC_ACTIVATION, 795 #endif /* USE_RT_DEBUG_ADC_ACTIVATION */ 796 797 #if (USE_RT_DEBUG_ADC_DEACTIVATION == 1) 798 [RT_DEBUG_ADC_DEACTIVATION] = GPIO_DEBUG_ADC_DEACTIVATION, 799 #endif /* USE_RT_DEBUG_ADC_DEACTIVATION */ 800 801 #if (USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION == 1) 802 [RT_DEBUG_ADC_TEMPERATURE_ACQUISITION] = GPIO_DEBUG_ADC_TEMPERATURE_ACQUISITION, 803 #endif /* USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION */ 804 805 #if (USE_RT_DEBUG_RNG_ENABLE == 1) 806 [RT_DEBUG_RNG_ENABLE] = GPIO_DEBUG_RNG_ENABLE, 807 #endif /* USE_RT_DEBUG_RNG_ENABLE */ 808 809 #if (USE_RT_DEBUG_RNG_DISABLE == 1) 810 [RT_DEBUG_RNG_DISABLE] = GPIO_DEBUG_RNG_DISABLE, 811 #endif /* USE_RT_DEBUG_RNG_DISABLE */ 812 813 #if (USE_RT_DEBUG_RNG_GEN_RAND_NUM == 1) 814 [RT_DEBUG_RNG_GEN_RAND_NUM] = GPIO_DEBUG_RNG_GEN_RAND_NUM, 815 #endif /* USE_RT_DEBUG_RNG_GEN_RAND_NUM */ 816 817 #if (USE_RT_DEBUG_LOW_POWER_STOP_MODE_ENTER == 1) 818 [RT_DEBUG_LOW_POWER_STOP_MODE_ENTER] = GPIO_DEBUG_LOW_POWER_STOP_MODE_ENTER, 819 #endif /* USE_RT_DEBUG_LOW_POWER_STOP_MODE_ENTER */ 820 821 #if (USE_RT_DEBUG_LOW_POWER_STOP_MODE_EXIT == 1) 822 [RT_DEBUG_LOW_POWER_STOP_MODE_EXIT] = GPIO_DEBUG_LOW_POWER_STOP_MODE_EXIT, 823 #endif /* USE_RT_DEBUG_LOW_POWER_STOP_MODE_EXIT */ 824 825 #if (USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE == 1) 826 [RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE] = GPIO_DEBUG_LOW_POWER_STOP_MODE_ACTIVE, 827 #endif /* USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE */ 828 829 #if (USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ENTER == 1) 830 [RT_DEBUG_LOW_POWER_STANDBY_MODE_ENTER] = GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ENTER, 831 #endif /* USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ENTER */ 832 833 #if (USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_EXIT == 1) 834 [RT_DEBUG_LOW_POWER_STANDBY_MODE_EXIT] = GPIO_DEBUG_LOW_POWER_STANDBY_MODE_EXIT, 835 #endif /* USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_EXIT */ 836 837 #if (USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE == 1) 838 [RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE] = GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE, 839 #endif /* USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE */ 840 841 #if (USE_RT_DEBUG_HCI_READ_DONE == 1) 842 [RT_DEBUG_HCI_READ_DONE] = GPIO_DEBUG_HCI_READ_DONE, 843 #endif /* USE_RT_DEBUG_HCI_READ_DONE */ 844 845 #if (USE_RT_DEBUG_HCI_RCVD_CMD == 1) 846 [RT_DEBUG_HCI_RCVD_CMD] = GPIO_DEBUG_HCI_RCVD_CMD, 847 #endif /* USE_RT_DEBUG_HCI_RCVD_CMD */ 848 849 #if (USE_RT_DEBUG_HCI_WRITE_DONE == 1) 850 [RT_DEBUG_HCI_WRITE_DONE] = GPIO_DEBUG_HCI_WRITE_DONE, 851 #endif /* USE_RT_DEBUG_HCI_WRITE_DONE */ 852 853 #if (USE_RT_DEBUG_SCHDLR_EVNT_UPDATE == 1) 854 [RT_DEBUG_SCHDLR_EVNT_UPDATE] = GPIO_DEBUG_SCHDLR_EVNT_UPDATE, 855 #endif /* USE_RT_DEBUG_SCHDLR_EVNT_UPDATE */ 856 857 #if (USE_RT_DEBUG_SCHDLR_TIMER_SET == 1) 858 [RT_DEBUG_SCHDLR_TIMER_SET] = GPIO_DEBUG_SCHDLR_TIMER_SET, 859 #endif /* USE_RT_DEBUG_SCHDLR_TIMER_SET */ 860 861 #if (USE_RT_DEBUG_SCHDLR_PHY_CLBR_TIMER == 1) 862 [RT_DEBUG_SCHDLR_PHY_CLBR_TIMER] = GPIO_DEBUG_SCHDLR_PHY_CLBR_TIMER, 863 #endif /* USE_RT_DEBUG_SCHDLR_PHY_CLBR_TIMER */ 864 865 #if (USE_RT_DEBUG_SCHDLR_EVNT_SKIPPED == 1) 866 [RT_DEBUG_SCHDLR_EVNT_SKIPPED] = GPIO_DEBUG_SCHDLR_EVNT_SKIPPED, 867 #endif /* USE_RT_DEBUG_SCHDLR_EVNT_SKIPPED */ 868 869 #if (USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE == 1) 870 [RT_DEBUG_SCHDLR_HNDL_NXT_TRACE] = GPIO_DEBUG_SCHDLR_HNDL_NXT_TRACE, 871 #endif /* USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE */ 872 873 #if (USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED == 1) 874 [RT_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED] = GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED, 875 #endif /* USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED */ 876 877 #if (USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK == 1) 878 [RT_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK] = GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK, 879 #endif /* USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK */ 880 881 #if (USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK == 1) 882 [RT_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK] = GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK, 883 #endif /* USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK */ 884 885 #if (USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE == 1) 886 [RT_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE] = GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE, 887 #endif /* USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE */ 888 889 #if (USE_RT_DEBUG_SCHDLR_EVNT_RGSTR == 1) 890 [RT_DEBUG_SCHDLR_EVNT_RGSTR] = GPIO_DEBUG_SCHDLR_EVNT_RGSTR, 891 #endif /* USE_RT_DEBUG_SCHDLR_EVNT_RGSTR */ 892 893 #if (USE_RT_DEBUG_SCHDLR_ADD_CONFLICT_Q == 1) 894 [RT_DEBUG_SCHDLR_ADD_CONFLICT_Q] = GPIO_DEBUG_SCHDLR_ADD_CONFLICT_Q, 895 #endif /* USE_RT_DEBUG_SCHDLR_ADD_CONFLICT_Q */ 896 897 #if (USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT == 1) 898 [RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT] = GPIO_DEBUG_SCHDLR_HNDL_MISSED_EVNT, 899 #endif /* USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT */ 900 901 #if (USE_RT_DEBUG_SCHDLR_UNRGSTR_EVNT == 1) 902 [RT_DEBUG_SCHDLR_UNRGSTR_EVNT] = GPIO_DEBUG_SCHDLR_UNRGSTR_EVNT, 903 #endif /* USE_RT_DEBUG_SCHDLR_UNRGSTR_EVNT */ 904 905 #if (USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE == 1) 906 [RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE] = GPIO_DEBUG_SCHDLR_EXEC_EVNT_TRACE, 907 #endif /* USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE */ 908 909 #if (USE_RT_DEBUG_SCHDLR_EXEC_EVNT_PROFILE == 1) 910 [RT_DEBUG_SCHDLR_EXEC_EVNT_PROFILE] = GPIO_DEBUG_SCHDLR_EXEC_EVNT_PROFILE, 911 #endif /* USE_RT_DEBUG_SCHDLR_EXEC_EVNT_PROFILE */ 912 913 #if (USE_RT_DEBUG_SCHDLR_EXEC_EVNT_ERROR == 1) 914 [RT_DEBUG_SCHDLR_EXEC_EVNT_ERROR] = GPIO_DEBUG_SCHDLR_EXEC_EVNT_ERROR, 915 #endif /* USE_RT_DEBUG_SCHDLR_EXEC_EVNT_ERROR */ 916 917 #if (USE_RT_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING == 1) 918 [RT_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING] = GPIO_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING, 919 #endif /* USE_RT_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING */ 920 921 #if (USE_RT_DEBUG_LLHWC_CMN_CLR_ISR == 1) 922 [RT_DEBUG_LLHWC_CMN_CLR_ISR] = GPIO_DEBUG_LLHWC_CMN_CLR_ISR, 923 #endif /* USE_RT_DEBUG_LLHWC_CMN_CLR_ISR */ 924 925 #if (USE_RT_DEBUG_LLWCC_CMN_HG_ISR == 1) 926 [RT_DEBUG_LLWCC_CMN_HG_ISR] = GPIO_DEBUG_LLWCC_CMN_HG_ISR, 927 #endif /* USE_RT_DEBUG_LLWCC_CMN_HG_ISR */ 928 929 #if (USE_RT_DEBUG_LLHWC_CMN_LW_ISR == 1) 930 [RT_DEBUG_LLHWC_CMN_LW_ISR] = GPIO_DEBUG_LLHWC_CMN_LW_ISR, 931 #endif /* USE_RT_DEBUG_LLHWC_CMN_LW_ISR */ 932 933 #if (USE_RT_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR == 1) 934 [RT_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR] = GPIO_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR, 935 #endif /* USE_RT_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR */ 936 937 #if (USE_RT_DEBUG_LLHWC_LL_ISR == 1) 938 [RT_DEBUG_LLHWC_LL_ISR] = GPIO_DEBUG_LLHWC_LL_ISR, 939 #endif /* USE_RT_DEBUG_LLHWC_LL_ISR */ 940 941 #if (USE_RT_DEBUG_LLHWC_SPLTMR_SET == 1) 942 [RT_DEBUG_LLHWC_SPLTMR_SET] = GPIO_DEBUG_LLHWC_SPLTMR_SET, 943 #endif /* USE_RT_DEBUG_LLHWC_SPLTMR_SET */ 944 945 #if (USE_RT_DEBUG_LLHWC_SPLTMR_GET == 1) 946 [RT_DEBUG_LLHWC_SPLTMR_GET] = GPIO_DEBUG_LLHWC_SPLTMR_GET, 947 #endif /* USE_RT_DEBUG_LLHWC_SPLTMR_GET */ 948 949 #if (USE_RT_DEBUG_LLHWC_LOW_ISR == 1) 950 [RT_DEBUG_LLHWC_LOW_ISR] = GPIO_DEBUG_LLHWC_LOW_ISR, 951 #endif /* USE_RT_DEBUG_LLHWC_LOW_ISR */ 952 953 #if (USE_RT_DEBUG_LLHWC_STOP_SCN == 1) 954 [RT_DEBUG_LLHWC_STOP_SCN] = GPIO_DEBUG_LLHWC_STOP_SCN, 955 #endif /* USE_RT_DEBUG_LLHWC_STOP_SCN */ 956 957 #if (USE_RT_DEBUG_LLHWC_WAIT_ENVT_ON_AIR == 1) 958 [RT_DEBUG_LLHWC_WAIT_ENVT_ON_AIR] = GPIO_DEBUG_LLHWC_WAIT_ENVT_ON_AIR, 959 #endif /* USE_RT_DEBUG_LLHWC_WAIT_ENVT_ON_AIR */ 960 961 #if (USE_RT_DEBUG_LLHWC_SET_CONN_EVNT_PARAM == 1) 962 [RT_DEBUG_LLHWC_SET_CONN_EVNT_PARAM] = GPIO_DEBUG_LLHWC_SET_CONN_EVNT_PARAM, 963 #endif /* USE_RT_DEBUG_LLHWC_SET_CONN_EVNT_PARAM */ 964 965 #if (USE_RT_DEBUG_POST_EVNT == 1) 966 [RT_DEBUG_POST_EVNT] = GPIO_DEBUG_POST_EVNT, 967 #endif /* USE_RT_DEBUG_POST_EVNT */ 968 969 #if (USE_RT_DEBUG_HNDL_ALL_EVNTS == 1) 970 [RT_DEBUG_HNDL_ALL_EVNTS] = GPIO_DEBUG_HNDL_ALL_EVNTS, 971 #endif /* USE_RT_DEBUG_HNDL_ALL_EVNTS */ 972 973 #if (USE_RT_DEBUG_PROCESS_EVNT == 1) 974 [RT_DEBUG_PROCESS_EVNT] = GPIO_DEBUG_PROCESS_EVNT, 975 #endif /* USE_RT_DEBUG_PROCESS_EVNT */ 976 977 #if (USE_RT_DEBUG_PROCESS_ISO_DATA == 1) 978 [RT_DEBUG_PROCESS_ISO_DATA] = GPIO_DEBUG_PROCESS_ISO_DATA, 979 #endif /* USE_RT_DEBUG_PROCESS_ISO_DATA */ 980 981 #if (USE_RT_DEBUG_ALLOC_TX_ISO_EMPTY_PKT == 1) 982 [RT_DEBUG_ALLOC_TX_ISO_EMPTY_PKT] = GPIO_DEBUG_ALLOC_TX_ISO_EMPTY_PKT, 983 #endif /* USE_RT_DEBUG_ALLOC_TX_ISO_EMPTY_PKT */ 984 985 #if (USE_RT_DEBUG_BIG_FREE_EMPTY_PKTS == 1) 986 [RT_DEBUG_BIG_FREE_EMPTY_PKTS] = GPIO_DEBUG_BIG_FREE_EMPTY_PKTS, 987 #endif /* USE_RT_DEBUG_BIG_FREE_EMPTY_PKTS */ 988 989 #if (USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_OK == 1) 990 [RT_DEBUG_RECOMBINE_UNFRMD_DATA_OK] = GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_OK, 991 #endif /* USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_OK */ 992 993 #if (USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_CRC == 1) 994 [RT_DEBUG_RECOMBINE_UNFRMD_DATA_CRC] = GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_CRC, 995 #endif /* USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_CRC */ 996 997 #if (USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX == 1) 998 [RT_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX] = GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX, 999 #endif /* USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX */ 1000 1001 #if (USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE == 1) 1002 [RT_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE] = GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE, 1003 #endif /* USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE */ 1004 1005 #if (USE_RT_DEBUG_ISO_HNDL_SDU == 1) 1006 [RT_DEBUG_ISO_HNDL_SDU] = GPIO_DEBUG_ISO_HNDL_SDU, 1007 #endif /* USE_RT_DEBUG_ISO_HNDL_SDU */ 1008 1009 #if (USE_RT_DEBUG_LL_INTF_INIT == 1) 1010 [RT_DEBUG_LL_INTF_INIT] = GPIO_DEBUG_LL_INTF_INIT, 1011 #endif /* USE_RT_DEBUG_LL_INTF_INIT */ 1012 1013 #if (USE_RT_DEBUG_DATA_TO_CNTRLR == 1) 1014 [RT_DEBUG_DATA_TO_CNTRLR] = GPIO_DEBUG_DATA_TO_CNTRLR, 1015 #endif /* USE_RT_DEBUG_DATA_TO_CNTRLR */ 1016 1017 #if (USE_RT_DEBUG_FREE_LL_PKT_HNDLR == 1) 1018 [RT_DEBUG_FREE_LL_PKT_HNDLR] = GPIO_DEBUG_FREE_LL_PKT_HNDLR, 1019 #endif /* USE_RT_DEBUG_FREE_LL_PKT_HNDLR */ 1020 1021 #if (USE_RT_DEBUG_PHY_INIT_CLBR_TRACE == 1) 1022 [RT_DEBUG_PHY_INIT_CLBR_TRACE] = GPIO_DEBUG_PHY_INIT_CLBR_TRACE, 1023 #endif /* USE_RT_DEBUG_PHY_INIT_CLBR_TRACE */ 1024 1025 #if (USE_RT_DEBUG_PHY_RUNTIME_CLBR_TRACE == 1) 1026 [RT_DEBUG_PHY_RUNTIME_CLBR_TRACE] = GPIO_DEBUG_PHY_RUNTIME_CLBR_TRACE, 1027 #endif /* USE_RT_DEBUG_PHY_RUNTIME_CLBR_TRACE */ 1028 1029 #if (USE_RT_DEBUG_PHY_CLBR_ISR == 1) 1030 [RT_DEBUG_PHY_CLBR_ISR] = GPIO_DEBUG_PHY_CLBR_ISR, 1031 #endif /* USE_RT_DEBUG_PHY_CLBR_ISR */ 1032 1033 #if (USE_RT_DEBUG_PHY_INIT_CLBR_SINGLE_CH == 1) 1034 [RT_DEBUG_PHY_INIT_CLBR_SINGLE_CH] = GPIO_DEBUG_PHY_INIT_CLBR_SINGLE_CH, 1035 #endif /* USE_RT_DEBUG_PHY_INIT_CLBR_SINGLE_CH */ 1036 1037 #if (USE_RT_DEBUG_PHY_CLBR_STRTD == 1) 1038 [RT_DEBUG_PHY_CLBR_STRTD] = GPIO_DEBUG_PHY_CLBR_STRTD, 1039 #endif /* USE_RT_DEBUG_PHY_CLBR_STRTD */ 1040 1041 #if (USE_RT_DEBUG_PHY_CLBR_EXEC == 1) 1042 [RT_DEBUG_PHY_CLBR_EXEC] = GPIO_DEBUG_PHY_CLBR_EXEC, 1043 #endif /* USE_RT_DEBUG_PHY_CLBR_EXEC */ 1044 1045 #if (USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV == 1) 1046 [RT_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV] = GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV, 1047 #endif /* USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV */ 1048 1049 #if (USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR == 1) 1050 [RT_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR] = GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR, 1051 #endif /* USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR */ 1052 1053 #if (USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT == 1) 1054 [RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT] = GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT, 1055 #endif /* USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT */ 1056 1057 #if (USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE == 1) 1058 [RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE] = GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE, 1059 #endif /* USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE */ 1060 1061 #if (USE_RT_DEBUG_RCO_ISR_TRACE == 1) 1062 [RT_DEBUG_RCO_ISR_TRACE] = GPIO_DEBUG_RCO_ISR_TRACE, 1063 #endif /* USE_RT_DEBUG_RCO_ISR_TRACE */ 1064 1065 #if (USE_RT_DEBUG_RCO_ISR_COMPENDATE == 1) 1066 [RT_DEBUG_RCO_ISR_COMPENDATE] = GPIO_DEBUG_RCO_ISR_COMPENDATE, 1067 #endif /* USE_RT_DEBUG_RCO_ISR_COMPENDATE */ 1068 1069 #if (USE_RT_DEBUG_RAL_STRT_TX == 1) 1070 [RT_DEBUG_RAL_STRT_TX] = GPIO_DEBUG_RAL_STRT_TX, 1071 #endif /* USE_RT_DEBUG_RAL_STRT_TX */ 1072 1073 #if (USE_RT_DEBUG_RAL_ISR_TIMER_ERROR == 1) 1074 [RT_DEBUG_RAL_ISR_TIMER_ERROR] = GPIO_DEBUG_RAL_ISR_TIMER_ERROR, 1075 #endif /* USE_RT_DEBUG_RAL_ISR_TIMER_ERROR */ 1076 1077 #if (USE_RT_DEBUG_RAL_ISR_TRACE == 1) 1078 [RT_DEBUG_RAL_ISR_TRACE] = GPIO_DEBUG_RAL_ISR_TRACE, 1079 #endif /* USE_RT_DEBUG_RAL_ISR_TRACE */ 1080 1081 #if (USE_RT_DEBUG_RAL_STOP_OPRTN == 1) 1082 [RT_DEBUG_RAL_STOP_OPRTN] = GPIO_DEBUG_RAL_STOP_OPRTN, 1083 #endif /* USE_RT_DEBUG_RAL_STOP_OPRTN */ 1084 1085 #if (USE_RT_DEBUG_RAL_STRT_RX == 1) 1086 [RT_DEBUG_RAL_STRT_RX] = GPIO_DEBUG_RAL_STRT_RX, 1087 #endif /* USE_RT_DEBUG_RAL_STRT_RX */ 1088 1089 #if (USE_RT_DEBUG_RAL_DONE_CLBK_TX == 1) 1090 [RT_DEBUG_RAL_DONE_CLBK_TX] = GPIO_DEBUG_RAL_DONE_CLBK_TX, 1091 #endif /* USE_RT_DEBUG_RAL_DONE_CLBK_TX */ 1092 1093 #if (USE_RT_DEBUG_RAL_DONE_CLBK_RX == 1) 1094 [RT_DEBUG_RAL_DONE_CLBK_RX] = GPIO_DEBUG_RAL_DONE_CLBK_RX, 1095 #endif /* USE_RT_DEBUG_RAL_DONE_CLBK_RX */ 1096 1097 #if (USE_RT_DEBUG_RAL_DONE_CLBK_ED == 1) 1098 [RT_DEBUG_RAL_DONE_CLBK_ED] = GPIO_DEBUG_RAL_DONE_CLBK_ED, 1099 #endif /* USE_RT_DEBUG_RAL_DONE_CLBK_ED */ 1100 1101 #if (USE_RT_DEBUG_RAL_ED_SCAN == 1) 1102 [RT_DEBUG_RAL_ED_SCAN] = GPIO_DEBUG_RAL_ED_SCAN, 1103 #endif /* USE_RT_DEBUG_RAL_ED_SCAN */ 1104 1105 #if (USE_RT_DEBUG_ERROR_MEM_CAP_EXCED == 1) 1106 [RT_DEBUG_ERROR_MEM_CAP_EXCED] = GPIO_DEBUG_ERROR_MEM_CAP_EXCED, 1107 #endif /* USE_RT_DEBUG_ERROR_MEM_CAP_EXCED */ 1108 1109 #if (USE_RT_DEBUG_ERROR_COMMAND_DISALLOWED == 1) 1110 [RT_DEBUG_ERROR_COMMAND_DISALLOWED] = GPIO_DEBUG_ERROR_COMMAND_DISALLOWED, 1111 #endif /* USE_RT_DEBUG_ERROR_COMMAND_DISALLOWED */ 1112 1113 #if (USE_RT_DEBUG_PTA_INIT == 1) 1114 [RT_DEBUG_PTA_INIT] = GPIO_DEBUG_PTA_INIT, 1115 #endif /* USE_RT_DEBUG_PTA_INIT */ 1116 1117 #if (USE_RT_DEBUG_PTA_EN == 1) 1118 [RT_DEBUG_PTA_EN] = GPIO_DEBUG_PTA_EN, 1119 #endif /* USE_RT_DEBUG_PTA_EN */ 1120 1121 #if (USE_RT_DEBUG_LLHWC_PTA_SET_EN == 1) 1122 [RT_DEBUG_LLHWC_PTA_SET_EN] = GPIO_DEBUG_LLHWC_PTA_SET_EN, 1123 #endif /* USE_RT_DEBUG_LLHWC_PTA_SET_EN */ 1124 1125 #if (USE_RT_DEBUG_LLHWC_PTA_SET_PARAMS == 1) 1126 [RT_DEBUG_LLHWC_PTA_SET_PARAMS] = GPIO_DEBUG_LLHWC_PTA_SET_PARAMS, 1127 #endif /* USE_RT_DEBUG_LLHWC_PTA_SET_PARAMS */ 1128 1129 #if (USE_RT_DEBUG_COEX_STRT_ON_IDLE == 1) 1130 [RT_DEBUG_COEX_STRT_ON_IDLE] = GPIO_DEBUG_COEX_STRT_ON_IDLE, 1131 #endif /* USE_RT_DEBUG_COEX_STRT_ON_IDLE */ 1132 1133 #if (USE_RT_DEBUG_COEX_ASK_FOR_AIR == 1) 1134 [RT_DEBUG_COEX_ASK_FOR_AIR] = GPIO_DEBUG_COEX_ASK_FOR_AIR, 1135 #endif /* USE_RT_DEBUG_COEX_ASK_FOR_AIR */ 1136 1137 #if (USE_RT_DEBUG_COEX_TIMER_EVNT_CLBK == 1) 1138 [RT_DEBUG_COEX_TIMER_EVNT_CLBK] = GPIO_DEBUG_COEX_TIMER_EVNT_CLBK, 1139 #endif /* USE_RT_DEBUG_COEX_TIMER_EVNT_CLBK */ 1140 1141 #if (USE_RT_DEBUG_COEX_STRT_ONE_SHOT == 1) 1142 [RT_DEBUG_COEX_STRT_ONE_SHOT] = GPIO_DEBUG_COEX_STRT_ONE_SHOT, 1143 #endif /* USE_RT_DEBUG_COEX_STRT_ONE_SHOT */ 1144 1145 #if (USE_RT_DEBUG_COEX_FORCE_STOP_RX == 1) 1146 [RT_DEBUG_COEX_FORCE_STOP_RX] = GPIO_DEBUG_COEX_FORCE_STOP_RX, 1147 #endif /* USE_RT_DEBUG_COEX_FORCE_STOP_RX */ 1148 1149 #if (USE_RT_DEBUG_LLHWC_ADV_DONE == 1) 1150 [RT_DEBUG_LLHWC_ADV_DONE] = GPIO_DEBUG_LLHWC_ADV_DONE, 1151 #endif /* USE_RT_DEBUG_LLHWC_ADV_DONE */ 1152 1153 #if (USE_RT_DEBUG_LLHWC_SCN_DONE == 1) 1154 [RT_DEBUG_LLHWC_SCN_DONE] = GPIO_DEBUG_LLHWC_SCN_DONE, 1155 #endif /* USE_RT_DEBUG_LLHWC_SCN_DONE */ 1156 1157 #if (USE_RT_DEBUG_LLHWC_INIT_DONE == 1) 1158 [RT_DEBUG_LLHWC_INIT_DONE] = GPIO_DEBUG_LLHWC_INIT_DONE, 1159 #endif /* USE_RT_DEBUG_LLHWC_INIT_DONE */ 1160 1161 #if (USE_RT_DEBUG_LLHWC_CONN_DONE == 1) 1162 [RT_DEBUG_LLHWC_CONN_DONE] = GPIO_DEBUG_LLHWC_CONN_DONE, 1163 #endif /* USE_RT_DEBUG_LLHWC_CONN_DONE */ 1164 1165 #if (USE_RT_DEBUG_LLHWC_CIG_DONE == 1) 1166 [RT_DEBUG_LLHWC_CIG_DONE] = GPIO_DEBUG_LLHWC_CIG_DONE, 1167 #endif /* USE_RT_DEBUG_LLHWC_CIG_DONE */ 1168 1169 #if (USE_RT_DEBUG_LLHWC_BIG_DONE == 1) 1170 [RT_DEBUG_LLHWC_BIG_DONE] = GPIO_DEBUG_LLHWC_BIG_DONE, 1171 #endif /* USE_RT_DEBUG_LLHWC_BIG_DONE */ 1172 1173 #if (USE_RT_DEBUG_OS_TMR_CREATE == 1) 1174 [RT_DEBUG_OS_TMR_CREATE] = GPIO_DEBUG_OS_TMR_CREATE, 1175 #endif /* USE_RT_DEBUG_OS_TMR_CREATE */ 1176 1177 #if (USE_RT_DEBUG_ADV_EXT_TIMEOUT_CBK == 1) 1178 [RT_DEBUG_ADV_EXT_TIMEOUT_CBK] = GPIO_DEBUG_ADV_EXT_TIMEOUT_CBK, 1179 #endif /* USE_RT_DEBUG_ADV_EXT_TIMEOUT_CBK */ 1180 1181 #if (USE_RT_DEBUG_ADV_EXT_SCN_DUR_CBK == 1) 1182 [RT_DEBUG_ADV_EXT_SCN_DUR_CBK] = GPIO_DEBUG_ADV_EXT_SCN_DUR_CBK, 1183 #endif /* USE_RT_DEBUG_ADV_EXT_SCN_DUR_CBK */ 1184 1185 #if (USE_RT_DEBUG_ADV_EXT_SCN_PERIOD_CBK == 1) 1186 [RT_DEBUG_ADV_EXT_SCN_PERIOD_CBK] = GPIO_DEBUG_ADV_EXT_SCN_PERIOD_CBK, 1187 #endif /* USE_RT_DEBUG_ADV_EXT_SCN_PERIOD_CBK */ 1188 1189 #if (USE_RT_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK == 1) 1190 [RT_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK] = GPIO_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK, 1191 #endif /* USE_RT_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK */ 1192 1193 #if (USE_RT_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK == 1) 1194 [RT_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK] = GPIO_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK, 1195 #endif /* USE_RT_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK */ 1196 1197 #if (USE_RT_DEBUG_BIS_TERM_TMR_CBK == 1) 1198 [RT_DEBUG_BIS_TERM_TMR_CBK] = GPIO_DEBUG_BIS_TERM_TMR_CBK, 1199 #endif /* USE_RT_DEBUG_BIS_TERM_TMR_CBK */ 1200 1201 #if (USE_RT_DEBUG_BIS_TST_MODE_CBK == 1) 1202 [RT_DEBUG_BIS_TST_MODE_CBK] = GPIO_DEBUG_BIS_TST_MODE_CBK, 1203 #endif /* USE_RT_DEBUG_BIS_TST_MODE_CBK */ 1204 1205 #if (USE_RT_DEBUG_BIS_TST_MODE_TMR_CBK == 1) 1206 [RT_DEBUG_BIS_TST_MODE_TMR_CBK] = GPIO_DEBUG_BIS_TST_MODE_TMR_CBK, 1207 #endif /* USE_RT_DEBUG_BIS_TST_MODE_TMR_CBK */ 1208 1209 #if (USE_RT_DEBUG_ISO_POST_TMR_CBK == 1) 1210 [RT_DEBUG_ISO_POST_TMR_CBK] = GPIO_DEBUG_ISO_POST_TMR_CBK, 1211 #endif /* USE_RT_DEBUG_ISO_POST_TMR_CBK */ 1212 1213 #if (USE_RT_DEBUG_ISO_TST_MODE_TMR_CBK == 1) 1214 [RT_DEBUG_ISO_TST_MODE_TMR_CBK] = GPIO_DEBUG_ISO_TST_MODE_TMR_CBK, 1215 #endif /* USE_RT_DEBUG_ISO_TST_MODE_TMR_CBK */ 1216 1217 #if (USE_RT_DEBUG_CONN_POST_TMR_CBK == 1) 1218 [RT_DEBUG_CONN_POST_TMR_CBK] = GPIO_DEBUG_CONN_POST_TMR_CBK, 1219 #endif /* USE_RT_DEBUG_CONN_POST_TMR_CBK */ 1220 1221 #if (USE_RT_DEBUG_EVNT_SCHDLR_TMR_CBK == 1) 1222 [RT_DEBUG_EVNT_SCHDLR_TMR_CBK] = GPIO_DEBUG_EVNT_SCHDLR_TMR_CBK, 1223 #endif /* USE_RT_DEBUG_EVNT_SCHDLR_TMR_CBK */ 1224 1225 #if (USE_RT_DEBUG_HCI_POST_TMR_CBK == 1) 1226 [RT_DEBUG_HCI_POST_TMR_CBK] = GPIO_DEBUG_HCI_POST_TMR_CBK, 1227 #endif /* USE_RT_DEBUG_HCI_POST_TMR_CBK */ 1228 1229 #if (USE_RT_DEBUG_LLCP_POST_TMR_CBK == 1) 1230 [RT_DEBUG_LLCP_POST_TMR_CBK] = GPIO_DEBUG_LLCP_POST_TMR_CBK, 1231 #endif /* USE_RT_DEBUG_LLCP_POST_TMR_CBK */ 1232 1233 #if (USE_RT_DEBUG_LLHWC_ENRGY_DETECT_CBK == 1) 1234 [RT_DEBUG_LLHWC_ENRGY_DETECT_CBK] = GPIO_DEBUG_LLHWC_ENRGY_DETECT_CBK, 1235 #endif /* USE_RT_DEBUG_LLHWC_ENRGY_DETECT_CBK */ 1236 1237 #if (USE_RT_DEBUG_PRVCY_POST_TMR_CBK == 1) 1238 [RT_DEBUG_PRVCY_POST_TMR_CBK] = GPIO_DEBUG_PRVCY_POST_TMR_CBK, 1239 #endif /* USE_RT_DEBUG_PRVCY_POST_TMR_CBK */ 1240 1241 #if (USE_RT_DEBUG_ANT_PRPR_TMR_CBK == 1) 1242 [RT_DEBUG_ANT_PRPR_TMR_CBK] = GPIO_DEBUG_ANT_PRPR_TMR_CBK, 1243 #endif /* USE_RT_DEBUG_ANT_PRPR_TMR_CBK */ 1244 1245 #if (USE_RT_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK == 1) 1246 [RT_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK] = GPIO_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK, 1247 #endif /* USE_RT_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK */ 1248 1249 #if (USE_RT_DEBUG_MLME_RX_EN_TMR_CBK == 1) 1250 [RT_DEBUG_MLME_RX_EN_TMR_CBK] = GPIO_DEBUG_MLME_RX_EN_TMR_CBK, 1251 #endif /* USE_RT_DEBUG_MLME_RX_EN_TMR_CBK */ 1252 1253 #if (USE_RT_DEBUG_MLME_GNRC_TMR_CBK == 1) 1254 [RT_DEBUG_MLME_GNRC_TMR_CBK] = GPIO_DEBUG_MLME_GNRC_TMR_CBK, 1255 #endif /* USE_RT_DEBUG_MLME_GNRC_TMR_CBK */ 1256 1257 #if (USE_RT_DEBUG_MIB_JOIN_LST_TMR_CBK == 1) 1258 [RT_DEBUG_MIB_JOIN_LST_TMR_CBK] = GPIO_DEBUG_MIB_JOIN_LST_TMR_CBK, 1259 #endif /* USE_RT_DEBUG_MIB_JOIN_LST_TMR_CBK */ 1260 1261 #if (USE_RT_DEBUG_MLME_PWR_PRES_TMR_CBK == 1) 1262 [RT_DEBUG_MLME_PWR_PRES_TMR_CBK] = GPIO_DEBUG_MLME_PWR_PRES_TMR_CBK, 1263 #endif /* USE_RT_DEBUG_MLME_PWR_PRES_TMR_CBK */ 1264 1265 #if (USE_RT_DEBUG_PRESISTENCE_TMR_CBK == 1) 1266 [RT_DEBUG_PRESISTENCE_TMR_CBK] = GPIO_DEBUG_PRESISTENCE_TMR_CBK, 1267 #endif /* USE_RT_DEBUG_PRESISTENCE_TMR_CBK */ 1268 1269 #if (USE_RT_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK == 1) 1270 [RT_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK] = GPIO_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK, 1271 #endif /* USE_RT_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK */ 1272 1273 #if (USE_RT_DEBUG_RADIO_CSMA_TMR_CBK == 1) 1274 [RT_DEBUG_RADIO_CSMA_TMR_CBK] = GPIO_DEBUG_RADIO_CSMA_TMR_CBK, 1275 #endif /* USE_RT_DEBUG_RADIO_CSMA_TMR_CBK */ 1276 1277 #if (USE_RT_DEBUG_RADIO_CSL_RCV_TMR_CBK == 1) 1278 [RT_DEBUG_RADIO_CSL_RCV_TMR_CBK] = GPIO_DEBUG_RADIO_CSL_RCV_TMR_CBK, 1279 #endif /* USE_RT_DEBUG_RADIO_CSL_RCV_TMR_CBK */ 1280 1281 #if (USE_RT_DEBUG_ED_TMR_CBK == 1) 1282 [RT_DEBUG_ED_TMR_CBK] = GPIO_DEBUG_ED_TMR_CBK, 1283 #endif /* USE_RT_DEBUG_ED_TMR_CBK */ 1284 1285 #if (USE_RT_DEBUG_DIO_EXT_TMR_CBK == 1) 1286 [RT_DEBUG_DIO_EXT_TMR_CBK] = GPIO_DEBUG_DIO_EXT_TMR_CBK, 1287 #endif /* USE_RT_DEBUG_DIO_EXT_TMR_CBK */ 1288 1289 #if (USE_RT_DEBUG_RCO_CLBR_TMR_CBK == 1) 1290 [RT_DEBUG_RCO_CLBR_TMR_CBK] = GPIO_DEBUG_RCO_CLBR_TMR_CBK, 1291 #endif /* USE_RT_DEBUG_RCO_CLBR_TMR_CBK */ 1292 1293 #if (USE_RT_DEBUG_ADV_EXT_MNGR_ADV_CBK == 1) 1294 [RT_DEBUG_ADV_EXT_MNGR_ADV_CBK] = GPIO_DEBUG_ADV_EXT_MNGR_ADV_CBK, 1295 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_ADV_CBK */ 1296 1297 #if (USE_RT_DEBUG_ADV_EXT_MNGR_SCN_CBK == 1) 1298 [RT_DEBUG_ADV_EXT_MNGR_SCN_CBK] = GPIO_DEBUG_ADV_EXT_MNGR_SCN_CBK, 1299 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_SCN_CBK */ 1300 1301 #if (USE_RT_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK == 1) 1302 [RT_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK] = GPIO_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK, 1303 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK */ 1304 1305 #if (USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK == 1) 1306 [RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK] = GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK, 1307 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK */ 1308 1309 #if (USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK == 1) 1310 [RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK] = GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK, 1311 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK */ 1312 1313 #if (USE_RT_DEBUG_BIG_ADV_CBK == 1) 1314 [RT_DEBUG_BIG_ADV_CBK] = GPIO_DEBUG_BIG_ADV_CBK, 1315 #endif /* USE_RT_DEBUG_BIG_ADV_CBK */ 1316 1317 #if (USE_RT_DEBUG_BIG_ADV_ERR_CBK == 1) 1318 [RT_DEBUG_BIG_ADV_ERR_CBK] = GPIO_DEBUG_BIG_ADV_ERR_CBK, 1319 #endif /* USE_RT_DEBUG_BIG_ADV_ERR_CBK */ 1320 1321 #if (USE_RT_DEBUG_BIG_SYNC_CBK == 1) 1322 [RT_DEBUG_BIG_SYNC_CBK] = GPIO_DEBUG_BIG_SYNC_CBK, 1323 #endif /* USE_RT_DEBUG_BIG_SYNC_CBK */ 1324 1325 #if (USE_RT_DEBUG_BIG_SYNC_ERR_CBK == 1) 1326 [RT_DEBUG_BIG_SYNC_ERR_CBK] = GPIO_DEBUG_BIG_SYNC_ERR_CBK, 1327 #endif /* USE_RT_DEBUG_BIG_SYNC_ERR_CBK */ 1328 1329 #if (USE_RT_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK == 1) 1330 [RT_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK] = GPIO_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK, 1331 #endif /* USE_RT_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK */ 1332 1333 #if (USE_RT_DEBUG_ISO_CIG_ERR_CBK == 1) 1334 [RT_DEBUG_ISO_CIG_ERR_CBK] = GPIO_DEBUG_ISO_CIG_ERR_CBK, 1335 #endif /* USE_RT_DEBUG_ISO_CIG_ERR_CBK */ 1336 1337 #if (USE_RT_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK == 1) 1338 [RT_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK] = GPIO_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK, 1339 #endif /* USE_RT_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK */ 1340 1341 #if (USE_RT_DEBUG_PRDC_CLBR_EXTRL_CBK == 1) 1342 [RT_DEBUG_PRDC_CLBR_EXTRL_CBK] = GPIO_DEBUG_PRDC_CLBR_EXTRL_CBK, 1343 #endif /* USE_RT_DEBUG_PRDC_CLBR_EXTRL_CBK */ 1344 1345 #if (USE_RT_DEBUG_PTR_PRDC_ADV_SYNC_CBK == 1) 1346 [RT_DEBUG_PTR_PRDC_ADV_SYNC_CBK] = GPIO_DEBUG_PTR_PRDC_ADV_SYNC_CBK, 1347 #endif /* USE_RT_DEBUG_PTR_PRDC_ADV_SYNC_CBK */ 1348 1349 #if (USE_RT_DEBUG_NCONN_SCN_CBK == 1) 1350 [RT_DEBUG_NCONN_SCN_CBK] = GPIO_DEBUG_NCONN_SCN_CBK, 1351 #endif /* USE_RT_DEBUG_NCONN_SCN_CBK */ 1352 1353 #if (USE_RT_DEBUG_NCONN_ADV_CBK == 1) 1354 [RT_DEBUG_NCONN_ADV_CBK] = GPIO_DEBUG_NCONN_ADV_CBK, 1355 #endif /* USE_RT_DEBUG_NCONN_ADV_CBK */ 1356 1357 #if (USE_RT_DEBUG_NCONN_INIT_CBK == 1) 1358 [RT_DEBUG_NCONN_INIT_CBK] = GPIO_DEBUG_NCONN_INIT_CBK, 1359 #endif /* USE_RT_DEBUG_NCONN_INIT_CBK */ 1360 1361 #if (USE_RT_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK == 1) 1362 [RT_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK] = GPIO_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK, 1363 #endif /* USE_RT_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK */ 1364 1365 #if (USE_RT_DEBUG_ANT_STACK_EVNT_CBK == 1) 1366 [RT_DEBUG_ANT_STACK_EVNT_CBK] = GPIO_DEBUG_ANT_STACK_EVNT_CBK, 1367 #endif /* USE_RT_DEBUG_ANT_STACK_EVNT_CBK */ 1368 1369 #if (USE_RT_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK == 1) 1370 [RT_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK] = GPIO_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK, 1371 #endif /* USE_RT_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK */ 1372 1373 #if (USE_RT_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT == 1) 1374 [RT_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT] = GPIO_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT, 1375 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT */ 1376 1377 #if (USE_RT_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT == 1) 1378 [RT_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT] = GPIO_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT, 1379 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT */ 1380 1381 #if (USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT == 1) 1382 [RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT] = GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT, 1383 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT */ 1384 1385 #if (USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT == 1) 1386 [RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT] = GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT, 1387 #endif /* USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT */ 1388 1389 #if (USE_RT_DEBUG_BIS_MNGR_BIG_TERM_CBK == 1) 1390 [RT_DEBUG_BIS_MNGR_BIG_TERM_CBK] = GPIO_DEBUG_BIS_MNGR_BIG_TERM_CBK, 1391 #endif /* USE_RT_DEBUG_BIS_MNGR_BIG_TERM_CBK */ 1392 1393 #if (USE_RT_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK == 1) 1394 [RT_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK] = GPIO_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK, 1395 #endif /* USE_RT_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK */ 1396 1397 #if (USE_RT_DEBUG_ISOAL_MNGR_SDU_GEN == 1) 1398 [RT_DEBUG_ISOAL_MNGR_SDU_GEN] = GPIO_DEBUG_ISOAL_MNGR_SDU_GEN, 1399 #endif /* USE_RT_DEBUG_ISOAL_MNGR_SDU_GEN */ 1400 1401 #if (USE_RT_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK == 1) 1402 [RT_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK] = GPIO_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK, 1403 #endif /* USE_RT_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK */ 1404 1405 #if (USE_RT_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK == 1) 1406 [RT_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK] = GPIO_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK, 1407 #endif /* USE_RT_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK */ 1408 1409 #if (USE_RT_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK == 1) 1410 [RT_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK] = GPIO_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK, 1411 #endif /* USE_RT_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK */ 1412 1413 #if (USE_RT_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT == 1) 1414 [RT_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT] = GPIO_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT, 1415 #endif /* USE_RT_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT */ 1416 1417 #if (USE_RT_DEBUG_HCI_EVENT_HNDLR == 1) 1418 [RT_DEBUG_HCI_EVENT_HNDLR] = GPIO_DEBUG_HCI_EVENT_HNDLR, 1419 #endif /* USE_RT_DEBUG_HCI_EVENT_HNDLR */ 1420 1421 #if (USE_RT_DEBUG_MLME_TMRS_CBK == 1) 1422 [RT_DEBUG_MLME_TMRS_CBK] = GPIO_DEBUG_MLME_TMRS_CBK, 1423 #endif /* USE_RT_DEBUG_MLME_TMRS_CBK */ 1424 1425 #if (USE_RT_DEBUG_DIRECT_TX_EVNT_CBK == 1) 1426 [RT_DEBUG_DIRECT_TX_EVNT_CBK] = GPIO_DEBUG_DIRECT_TX_EVNT_CBK, 1427 #endif /* USE_RT_DEBUG_DIRECT_TX_EVNT_CBK */ 1428 1429 #if (USE_RT_DEBUG_INDIRECT_PKT_TOUR_CBK == 1) 1430 [RT_DEBUG_INDIRECT_PKT_TOUR_CBK] = GPIO_DEBUG_INDIRECT_PKT_TOUR_CBK, 1431 #endif /* USE_RT_DEBUG_INDIRECT_PKT_TOUR_CBK */ 1432 1433 #if (USE_RT_DEBUG_RADIO_CSMA_TMR == 1) 1434 [RT_DEBUG_RADIO_CSMA_TMR] = GPIO_DEBUG_RADIO_CSMA_TMR, 1435 #endif /* USE_RT_DEBUG_RADIO_CSMA_TMR */ 1436 1437 #if (USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK == 1) 1438 [RT_DEBUG_RAL_SM_DONE_EVNT_CBK] = GPIO_DEBUG_RAL_SM_DONE_EVNT_CBK, 1439 #endif /* USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK */ 1440 1441 #if (USE_RT_DEBUG_ED_TMR_HNDL == 1) 1442 [RT_DEBUG_ED_TMR_HNDL] = GPIO_DEBUG_ED_TMR_HNDL, 1443 #endif /* USE_RT_DEBUG_ED_TMR_HNDL */ 1444 1445 #if (USE_RT_DEBUG_OS_TMR_EVNT_CBK == 1) 1446 [RT_DEBUG_OS_TMR_EVNT_CBK] = GPIO_DEBUG_OS_TMR_EVNT_CBK, 1447 #endif /* USE_RT_DEBUG_OS_TMR_EVNT_CBK */ 1448 1449 #if (USE_RT_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME == 1) 1450 [RT_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME] = GPIO_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME, 1451 #endif /* USE_RT_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME */ 1452 1453 #if (USE_RT_DEBUG_PROFILE_END_DRIFT_TIME == 1) 1454 [RT_DEBUG_PROFILE_END_DRIFT_TIME] = GPIO_DEBUG_PROFILE_END_DRIFT_TIME, 1455 #endif /* USE_RT_DEBUG_PROFILE_END_DRIFT_TIME */ 1456 1457 #if (USE_RT_DEBUG_PROC_RADIO_RCV == 1) 1458 [RT_DEBUG_PROC_RADIO_RCV] = GPIO_DEBUG_PROC_RADIO_RCV, 1459 #endif /* USE_RT_DEBUG_PROC_RADIO_RCV */ 1460 1461 #if (USE_RT_DEBUG_EVNT_TIME_UPDT == 1) 1462 [RT_DEBUG_EVNT_TIME_UPDT] = GPIO_DEBUG_EVNT_TIME_UPDT, 1463 #endif /* USE_RT_DEBUG_EVNT_TIME_UPDT */ 1464 1465 #if (USE_RT_DEBUG_MAC_RECEIVE_DONE == 1) 1466 [RT_DEBUG_MAC_RECEIVE_DONE] = GPIO_DEBUG_MAC_RECEIVE_DONE, 1467 #endif /* USE_RT_DEBUG_MAC_RECEIVE_DONE */ 1468 1469 #if (USE_RT_DEBUG_MAC_TX_DONE == 1) 1470 [RT_DEBUG_MAC_TX_DONE] = GPIO_DEBUG_MAC_TX_DONE, 1471 #endif /* USE_RT_DEBUG_MAC_TX_DONE */ 1472 1473 #if (USE_RT_DEBUG_RADIO_APPLY_CSMA == 1) 1474 [RT_DEBUG_RADIO_APPLY_CSMA] = GPIO_DEBUG_RADIO_APPLY_CSMA, 1475 #endif /* USE_RT_DEBUG_RADIO_APPLY_CSMA */ 1476 1477 #if (USE_RT_DEBUG_RADIO_TRANSMIT == 1) 1478 [RT_DEBUG_RADIO_TRANSMIT] = GPIO_DEBUG_RADIO_TRANSMIT, 1479 #endif /* USE_RT_DEBUG_RADIO_TRANSMIT */ 1480 1481 #if (USE_RT_DEBUG_PROC_RADIO_TX == 1) 1482 [RT_DEBUG_PROC_RADIO_TX] = GPIO_DEBUG_PROC_RADIO_TX, 1483 #endif /* USE_RT_DEBUG_PROC_RADIO_TX */ 1484 1485 #if (USE_RT_DEBUG_RAL_TX_DONE == 1) 1486 [RT_DEBUG_RAL_TX_DONE] = GPIO_DEBUG_RAL_TX_DONE, 1487 #endif /* USE_RT_DEBUG_RAL_TX_DONE */ 1488 1489 #if (USE_RT_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT == 1) 1490 [RT_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT] = GPIO_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT, 1491 #endif /* USE_RT_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT */ 1492 1493 #if (USE_RT_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT == 1) 1494 [RT_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT] = GPIO_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT, 1495 #endif /* USE_RT_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT */ 1496 1497 #if (USE_RT_DEBUG_RAL_CONTINUE_RX == 1) 1498 [RT_DEBUG_RAL_CONTINUE_RX] = GPIO_DEBUG_RAL_CONTINUE_RX, 1499 #endif /* USE_RT_DEBUG_RAL_CONTINUE_RX */ 1500 1501 #if (USE_RT_DEBUG_RAL_PERFORM_CCA == 1) 1502 [RT_DEBUG_RAL_PERFORM_CCA] = GPIO_DEBUG_RAL_PERFORM_CCA, 1503 #endif /* USE_RT_DEBUG_RAL_PERFORM_CCA */ 1504 1505 #if (USE_RT_DEBUG_RAL_ENABLE_TRANSMITTER == 1) 1506 [RT_DEBUG_RAL_ENABLE_TRANSMITTER] = GPIO_DEBUG_RAL_ENABLE_TRANSMITTER, 1507 #endif /* USE_RT_DEBUG_RAL_ENABLE_TRANSMITTER */ 1508 1509 #if (USE_RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 == 1) 1510 [RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2] = GPIO_DEBUG_LLHWC_GET_CH_IDX_ALGO_2, 1511 #endif /* USE_RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 */ 1512 1513 /************************************************/ 1514 /** Application signals in general debug table **/ 1515 /************************************************/ 1516 1517 #if (USE_RT_DEBUG_APP_APPE_INIT == 1) 1518 [RT_DEBUG_APP_APPE_INIT] = GPIO_DEBUG_APP_APPE_INIT, 1519 #endif /* USE_RT_DEBUG_OS_TMR_EVNT_CBK */ 1520 }; 1521 1522 #endif /* CFG_RT_DEBUG_GPIO_MODULE */ 1523 1524 #endif /* DEBUG_CONFIG_H */ 1525