1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_flash_ex.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H5xx_HAL_FLASH_EX_H 22 #define STM32H5xx_HAL_FLASH_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FLASHEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief FLASH Erase structure definition 46 */ 47 typedef struct 48 { 49 uint32_t TypeErase; /*!< Mass erase or sector Erase. 50 This parameter can be a value of @ref FLASH_Type_Erase */ 51 52 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. 53 This parameter can be a value of @ref FLASH_Banks 54 (FLASH_BANK_BOTH should be used only for mass erase) */ 55 56 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled 57 This parameter can be a value of @ref FLASH_Sectors */ 58 59 uint32_t NbSectors; /*!< Number of sectors to be erased. 60 This parameter can be a value between 1 and (max number of sectors in the bank - 61 value of initial sector)*/ 62 } FLASH_EraseInitTypeDef; 63 64 65 /** 66 * @brief FLASH Option Bytes Program structure definition 67 */ 68 typedef struct 69 { 70 uint32_t OptionType; /*!< Option byte to be configured. 71 This parameter can be a value of @ref FLASH_Option_Type */ 72 73 uint32_t ProductState; /*!< Set the product state. 74 This parameter can be a value of @ref FLASH_OB_Product_State */ 75 76 uint32_t USERType; /*!< Select the User Option Byte(s) to be configured (used for OPTIONBYTE_USER). 77 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 78 79 uint32_t USERConfig; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). 80 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 81 @ref FLASH_OB_USER_BORH_EN, @ref FLASH_OB_USER_IWDG_SW, 82 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nRST_STOP, 83 @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_IO_VDD_HSLV, 84 @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_IWDG_STOP, 85 @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_BOOT_UBE, 86 @ref FLASH_OB_USER_SWAP_BANK */ 87 88 uint32_t USERConfig2; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). 89 This parameter can be a combination of @ref FLASH_OB_USER_SRAM1_3_RST, 90 @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_BKPRAM_ECC, 91 @ref FLASH_OB_USER_SRAM3_ECC, @ref FLASH_OB_USER_SRAM2_ECC, 92 @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_SRAM1_ECC, 93 @ref FLASH_OB_USER_UNIQUE_KEY, @ref FLASH_OB_USER_TZEN */ 94 95 uint32_t Banks; /*!< Select banks for WRP , HDP and secure area configuration. 96 This parameter must be a value of @ref FLASH_Banks */ 97 98 uint32_t WRPState; /*!< Write protection activation or deactivation. 99 This parameter can be a value of @ref FLASH_WRP_State */ 100 101 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. 102 The value of this parameter depend on device used within the same series */ 103 104 uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured: secure or non-secure. 105 This parameter must be a value of @ref FLASH_OB_BOOT_CONFIG enumeration */ 106 107 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 108 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 109 110 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 111 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 112 113 uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. 114 This parameter must be a value of @ref FLASH_OTP_Blocks */ 115 116 uint32_t HDPStartSector; /*!< Start sector of HDP area (used for OPTIONBYTE_HDP). 117 This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ 118 119 uint32_t HDPEndSector; /*!< End sector of HDP area (used for OPTIONBYTE_HDP). 120 This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ 121 122 uint32_t EDATASize; /*!< Specifies the number of Flash high-cycle sectors. 123 This parameter must be a value between 0 and 8 (sectors) */ 124 125 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 126 uint32_t WMSecStartSector; /*!< Start sector of secure area (used for OPTIONBYTE_WMSEC). 127 This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ 128 uint32_t WMSecEndSector; /*!< End sector of secure area (used for OPTIONBYTE_WMSEC). 129 This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ 130 #endif /* __ARM_FEATURE_CMSE */ 131 132 } FLASH_OBProgramInitTypeDef; 133 134 /** 135 * @brief FLASHEx Block-based attributes structure definition 136 */ 137 typedef struct 138 { 139 uint32_t Bank; /*!< Selection of the associated bank of Block-based Area. 140 This parameter must be a value of @ref FLASH_Banks */ 141 uint32_t BBAttributesType; /*!< Block-Based Attributes type. 142 This parameter must be a value of @ref FLASH_BB_Attributes 143 */ 144 uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration 145 of a sector: 146 0 means sector non-protected, 1 means sector protected. 147 Protection (secure or privilege) depends on 148 BBAttributesType value */ 149 } FLASH_BBAttributesTypeDef; 150 151 /** 152 * @brief FLASHEx Operation structure definition 153 */ 154 typedef struct 155 { 156 uint32_t OperationType; /*!< Flash operation Type. 157 This parameter must be a value of @ref FLASH_Operation_Type */ 158 uint32_t FlashArea; /*!< Flash operation memory area. 159 This parameter must be a value of @ref FLASH_Operation_Area */ 160 uint32_t Address; /*!< Flash operation Address offset. 161 This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ 162 } FLASH_OperationTypeDef; 163 164 /** 165 * @brief FLASH HDP Extension structure definition 166 */ 167 typedef struct 168 { 169 uint32_t Banks; /*!< Selection of the associated bank of HDP Area. 170 This parameter must be a value of @ref FLASH_Banks */ 171 uint32_t NbSectors; /*!< Number of sectors to be HDP extended. 172 This parameter can be a value between 1 and max number of sectors in the bank */ 173 } FLASH_HDPExtensionTypeDef; 174 175 /** 176 * @} 177 */ 178 /* Exported constants --------------------------------------------------------*/ 179 180 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants 181 * @{ 182 */ 183 184 /** @defgroup FLASH_Type_Erase FLASH Type Erase 185 * @{ 186 */ 187 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 188 #define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Secure flash sectors 189 erase activation */ 190 #define FLASH_TYPEERASE_SECTORS_NS (FLASH_CR_SER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash 191 sectors erase activation */ 192 #define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Secure flash mass erase 193 activation */ 194 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_CR_BER | FLASH_CR_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass 195 erase activation */ 196 #if defined (FLASH_SR_OBKERR) 197 #define FLASH_TYPEERASE_OBK_ALT FLASH_OBKCFGR_ALT_SECT_ERASE /*!< Flash OBK erase 198 activation */ 199 #endif /* FLASH_SR_OBKERR */ 200 #else 201 #define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Flash sectors erase 202 activation */ 203 #define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Flash mass erase 204 activation */ 205 #if defined (FLASH_SR_OBKERR) 206 #define FLASH_TYPEERASE_OBK_ALT (FLASH_OBKCFGR_ALT_SECT_ERASE | FLASH_NON_SECURE_MASK) /*!< Flash OBK erase 207 activation */ 208 #endif /* FLASH_SR_OBKERR */ 209 #endif /* __ARM_FEATURE_CMSE */ 210 /** 211 * @} 212 */ 213 214 /** @defgroup FLASH_Option_Type FLASH Option Type 215 * @{ 216 */ 217 #define OPTIONBYTE_WRP 0x0001U /*!< WRP option byte configuration */ 218 #define OPTIONBYTE_PROD_STATE 0x0002U /*!< RDP option byte configuration */ 219 #define OPTIONBYTE_USER 0x0004U /*!< USER option byte configuration */ 220 #define OPTIONBYTE_BOOTADDR 0x0008U /*!< BOOT address option byte configuration */ 221 #define OPTIONBYTE_BOOT_LOCK 0x0010U /*!< Boot lock option byte configuration */ 222 #define OPTIONBYTE_OTP_LOCK 0x0020U /*!< OTP Lock option byte configuration */ 223 #define OPTIONBYTE_HDP 0x0040U /*!< Hide Protection area option byte configuration */ 224 #if defined (FLASH_EDATAR_EDATA_EN) 225 #define OPTIONBYTE_EDATA 0x0080U /*!< Flash high-cycle data area option byte configuration */ 226 #endif /* FLASH_EDATAR_EDATA_EN */ 227 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 228 #define OPTIONBYTE_WMSEC 0x0200U /*!< Watermark-based secure area option byte configuration */ 229 #endif /* __ARM_FEATURE_CMSE */ 230 231 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 232 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 233 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 234 OPTIONBYTE_HDP | OPTIONBYTE_EDATA | OPTIONBYTE_WMSEC) /*!< All option 235 byte configuration */ 236 #else 237 #if defined (FLASH_EDATAR_EDATA_EN) 238 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 239 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 240 OPTIONBYTE_HDP | OPTIONBYTE_EDATA) /*!< All option byte configuration */ 241 #else 242 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 243 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 244 OPTIONBYTE_HDP) /*!< All option byte configuration */ 245 #endif /* FLASH_EDATAR_EDATA_EN */ 246 #endif /* __ARM_FEATURE_CMSE */ 247 /** 248 * @} 249 */ 250 251 /** @defgroup FLASH_OB_USER_Type FLASH OB USER Type 252 * @{ 253 */ 254 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 255 #define OB_USER_BORH_EN 0x00000002U /*!< BOR high enable status */ 256 #define OB_USER_IWDG_SW 0x00000004U /*!< Independent watchdog selection */ 257 #define OB_USER_WWDG_SW 0x00000008U /*!< Window watchdog selection */ 258 #define OB_USER_NRST_STOP 0x00000010U /*!< Reset generated when entering the stop mode */ 259 #define OB_USER_NRST_STDBY 0x00000020U /*!< Reset generated when entering the standby mode */ 260 #define OB_USER_IO_VDD_HSLV 0x00000040U /*!< High speed IO at low voltage configuration bit */ 261 #define OB_USER_IO_VDDIO2_HSLV 0x00000080U /*!< High speed IO2 at low voltage configuration bit */ 262 #define OB_USER_IWDG_STOP 0x00000100U /*!< Independent watchdog counter freeze in stop mode */ 263 #define OB_USER_IWDG_STDBY 0x00000200U /*!< Independent watchdog counter freeze in standby mode */ 264 #if defined (FLASH_OPTSR_BOOT_UBE) 265 #define OB_USER_BOOT_UBE 0x00000400U /*!< Unique Boot entry */ 266 #endif /* FLASH_OPTSR_BOOT_UBE */ 267 #define OB_USER_SWAP_BANK 0x00000800U /*!< Swap banks */ 268 269 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 270 #define OB_USER_SRAM1_3_RST 0x00001000U /*!< SRAM1 and SRAM3 erase upon system reset */ 271 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 272 #if defined (FLASH_OPTSR2_SRAM1_RST) 273 #define OB_USER_SRAM1_RST 0x00001000U /*!< SRAM1 Erase when system reset */ 274 #endif /* FLASH_OPTSR2_SRAM1_RST */ 275 #define OB_USER_SRAM2_RST 0x00002000U /*!< SRAM2 Erase when system reset */ 276 #define OB_USER_BKPRAM_ECC 0x00004000U /*!< Backup RAM ECC detection and correction enable */ 277 #define OB_USER_SRAM3_ECC 0x00008000U /*!< SRAM3 ECC detection and correction enable */ 278 #define OB_USER_SRAM2_ECC 0x00010000U /*!< SRAM2 ECC detection and correction enable */ 279 #define OB_USER_SRAM1_ECC 0x00020000U /*!< SRAM1 ECC detection and correction enable */ 280 #if defined (FLASH_SR_PUF_STATE) 281 #define OB_USER_HUK_PUF 0x00040000U /*!< Unique key type */ 282 #endif /* FLASH_SR_PUF_STATE */ 283 #if defined (FLASH_OPTSR2_TZEN) 284 #define OB_USER_TZEN 0x00080000U /*!< Global TrustZone security enable */ 285 #endif /* FLASH_OPTSR2_TZEN */ 286 287 #if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE) 288 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ 289 OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ 290 OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ 291 OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\ 292 OB_USER_SRAM1_3_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\ 293 OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_HUK_PUF |\ 294 OB_USER_TZEN) 295 #else 296 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ 297 OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ 298 OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ 299 OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK | OB_USER_SRAM1_RST |\ 300 OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC | OB_USER_SRAM3_ECC |\ 301 OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC) 302 #endif /* FLASH_OPTSR2_SRAM1_3_RST && FLASH_OPTSR_BOOT_UBE */ 303 /** 304 * @} 305 */ 306 307 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH BOR Reset Level 308 * @{ 309 */ 310 #define OB_BOR_LEVEL_1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 1 threshold */ 311 #define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 2 threshold */ 312 #define OB_BOR_LEVEL_3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level 3 threshold */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup FLASH_OB_USER_BORH_EN FLASH BOR High Enable Status 318 * @{ 319 */ 320 #define OB_BORH_DISABLE 0x00000000U /*!< BOR high status bit disabled */ 321 #define OB_BORH_ENABLE FLASH_OPTSR_BORH_EN /*!< BOR high status bit enabled */ 322 /** 323 * @} 324 */ 325 326 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 327 * @{ 328 */ 329 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 330 #define OB_IWDG_SW FLASH_OPTSR_IWDG_SW /*!< Software independent watchdog */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 336 * @{ 337 */ 338 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 339 #define OB_WWDG_SW FLASH_OPTSR_WWDG_SW /*!< Software window watchdog */ 340 /** 341 * @} 342 */ 343 344 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes nRST_STOP 345 * @{ 346 */ 347 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering in stop mode */ 348 #define OB_STOP_NORST FLASH_OPTSR_NRST_STOP /*!< No reset generated when entering in stop mode */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes nRST_STDBY 354 * @{ 355 */ 356 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering in standby mode */ 357 #define OB_STANDBY_NORST FLASH_OPTSR_NRST_STDBY /*!< No reset generated when entering in standby mode */ 358 /** 359 * @} 360 */ 361 362 /** @defgroup FLASH_OB_Product_State FLASH Product State 363 * @{ 364 */ 365 #define OB_PROD_STATE_OPEN (0xEDU << FLASH_OPTSR_PRODUCT_STATE_Pos) 366 #define OB_PROD_STATE_PROVISIONING (0x17U << FLASH_OPTSR_PRODUCT_STATE_Pos) 367 #define OB_PROD_STATE_IROT_PROVISIONED (0x2EU << FLASH_OPTSR_PRODUCT_STATE_Pos) 368 #define OB_PROD_STATE_TZ_CLOSED (0xC6U << FLASH_OPTSR_PRODUCT_STATE_Pos) 369 #define OB_PROD_STATE_CLOSED (0x72U << FLASH_OPTSR_PRODUCT_STATE_Pos) 370 #define OB_PROD_STATE_LOCKED (0x5CU << FLASH_OPTSR_PRODUCT_STATE_Pos) 371 #define OB_PROD_STATE_REGRESSION (0x9AU << FLASH_OPTSR_PRODUCT_STATE_Pos) 372 #define OB_PROD_STATE_NS_REGRESSION (0xA3U << FLASH_OPTSR_PRODUCT_STATE_Pos) 373 /** 374 * @} 375 */ 376 377 /** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes VDD IO HSLV 378 * @{ 379 */ 380 #define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled */ 381 #define OB_IO_VDD_HSLV_ENABLE FLASH_OPTSR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes VDDIO2 IO HSLV 387 * @{ 388 */ 389 #define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature 390 disabled */ 391 #define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTSR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature 392 enabled */ 393 /** 394 * @} 395 */ 396 397 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH IWDG Counter Freeze in STOP 398 * @{ 399 */ 400 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< IWDG counter frozen in STOP mode */ 401 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_IWDG_STOP /*!< IWDG counter active in STOP mode */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH IWDG Counter Freeze in STANDBY 407 * @{ 408 */ 409 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< IWDG counter frozen in STANDBY mode */ 410 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_IWDG_STDBY /*!< IWDG counter active in STANDBY mode */ 411 /** 412 * @} 413 */ 414 415 /** @defgroup FLASH_OB_USER_BOOT_UBE FLASH OB Boot UBE 416 * @{ 417 */ 418 #if defined (FLASH_OPTSR_BOOT_UBE) 419 #define OB_UBE_OEM_IROT (0xB4U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< OEM-iRoT (user flash) selected */ 420 #define OB_UBE_ST_IROT (0xC3U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< ST-iRoT (system flash) selected */ 421 #endif /* FLASH_OPTSR_BOOT_UBE */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup FLASH_OB_USER_SWAP_BANK FLASH OB SWAP BANK 427 * @{ 428 */ 429 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ 430 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK /*!< Bank swap enabled */ 431 /** 432 * @} 433 */ 434 435 /** @defgroup FLASH_OB_USER_SRAM1_3_RST FLASH Option Bytes SRAM1_3 Erase On Reset 436 * @{ 437 */ 438 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 439 #define OB_SRAM1_3_RST_ERASE 0x00000000U /*!< SRAM1 and SRAM3 erased when a system reset occurs */ 440 #define OB_SRAM1_3_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_3_RST /*!< SRAM1 and SRAM3 are not erased when a system reset 441 occurs */ 442 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup FLASH_OB_USER_SRAM1_RST FLASH Option Bytes SRAM1 Erase On Reset 448 * @{ 449 */ 450 #if defined (FLASH_OPTSR2_SRAM1_RST) 451 #define OB_SRAM1_RST_ERASE 0x00000000U /*!< SRAM1 erased when a system reset occurs */ 452 #define OB_SRAM1_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_RST /*!< SRAM1 is not erased when a system reset occurs */ 453 #endif /* FLASH_OPTSR2_SRAM1_RST */ 454 /** 455 * @} 456 */ 457 458 459 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes SRAM2 Erase On Reset 460 * @{ 461 */ 462 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 463 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTSR2_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 464 /** 465 * @} 466 */ 467 468 /** @defgroup FLASH_OB_USER_BKPRAM_ECC FLASH Option Bytes User BKPRAM ECC check 469 * @{ 470 */ 471 #define OB_BKPRAM_ECC_ENABLE 0x00000000U /*!< BKPRAM ECC check enable */ 472 #define OB_BKPRAM_ECC_DISABLE FLASH_OPTSR2_BKPRAM_ECC /*!< BKPRAM ECC check disable */ 473 /** 474 * @} 475 */ 476 477 /** @defgroup FLASH_OB_USER_SRAM3_ECC FLASH Option Bytes User SRAM3 ECC check 478 * @{ 479 */ 480 #if defined (FLASH_OPTSR2_SRAM3_ECC) 481 #define OB_SRAM3_ECC_ENABLE 0x00000000U /*!< SRAM3 ECC check enable */ 482 #define OB_SRAM3_ECC_DISABLE FLASH_OPTSR2_SRAM3_ECC /*!< SRAM3 ECC check disable */ 483 #endif /* FLASH_OPTSR2_SRAM3_ECC */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup FLASH_OB_USER_SRAM2_ECC FLASH Option Bytes User SRAM2 ECC check 489 * @{ 490 */ 491 #define OB_SRAM2_ECC_ENABLE 0x00000000U /*!< SRAM2 ECC check enable */ 492 #define OB_SRAM2_ECC_DISABLE FLASH_OPTSR2_SRAM2_ECC /*!< SRAM2 ECC check disable */ 493 /** 494 * @} 495 */ 496 497 /** @defgroup FLASH_OB_USER_SRAM1_ECC FLASH Option Bytes User SRAM1 ECC check 498 * @{ 499 */ 500 #if defined (FLASH_OPTSR2_SRAM1_ECC) 501 #define OB_SRAM1_ECC_ENABLE 0x00000000U /*!< SRAM1 ECC check enable */ 502 #define OB_SRAM1_ECC_DISABLE FLASH_OPTSR2_SRAM1_ECC /*!< SRAM1 ECC check disable */ 503 #endif /* FLASH_OPTSR2_SRAM1_ECC */ 504 /** 505 * @} 506 */ 507 508 /** @defgroup FLASH_OB_USER_UNIQUE_KEY FLASH Option Bytes User Unique Key 509 * @{ 510 */ 511 #if defined (FLASH_SR_PUF_STATE) 512 #define OB_UNIQUE_KEY_HUK 0x00000000U /*!< The key is treated as HUK */ 513 #define OB_UNIQUE_KEY_PUF FLASH_OPTSR2_HUK_PUF /*!< The key is treated as PUF */ 514 #endif /* FLASH_SR_PUF_STATE */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes Global TrustZone 520 * @{ 521 */ 522 #if defined (FLASH_OPTSR2_TZEN) 523 #define OB_TZEN_DISABLE (0xC3U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security disabled */ 524 #define OB_TZEN_ENABLE (0xB4U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security enabled */ 525 #endif /* FLASH_OPTSR2_TZEN */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup FLASH_Banks FLASH Banks 531 * @{ 532 */ 533 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 534 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 535 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 536 /** 537 * @} 538 */ 539 540 /** @defgroup FLASH_OB_Write_Protection_Sectors FLASH Option Bytes Write Protection Sectors 541 * @{ 542 */ 543 #if (FLASH_SECTOR_NB == 128) 544 #define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ 545 #define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ 546 #define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ 547 #define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ 548 #define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ 549 #define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ 550 #define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ 551 #define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ 552 #define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ 553 #define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ 554 #define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ 555 #define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ 556 #define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ 557 #define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ 558 #define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ 559 #define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ 560 #define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ 561 #define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ 562 #define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ 563 #define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ 564 #define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ 565 #define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ 566 #define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ 567 #define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ 568 #define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ 569 #define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ 570 #define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ 571 #define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ 572 #define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ 573 #define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ 574 #define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ 575 #define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ 576 #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ 577 #else 578 #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ 579 #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ 580 #define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ 581 #define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ 582 #define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ 583 #define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ 584 #define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ 585 #define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ 586 #define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ 587 #endif /* (FLASH_SECTOR_NB == 128) */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup FLASH_Programming_Delay FLASH Programming Delay 593 * @{ 594 */ 595 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or 596 below */ 597 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz 598 and 185 MHz */ 599 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz 600 and 225 MHz */ 601 #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ 602 /** 603 * @} 604 */ 605 606 /** @defgroup FLASH_OTP_Blocks FLASH OTP blocks 607 * @{ 608 */ 609 #define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ 610 #define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ 611 #define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ 612 #define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ 613 #define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ 614 #define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ 615 #define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ 616 #define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ 617 #define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ 618 #define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ 619 #define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ 620 #define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ 621 #define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ 622 #define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ 623 #define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ 624 #define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ 625 #define FLASH_OTP_BLOCK_16 0x00010000U /*!< OTP Block16 */ 626 #define FLASH_OTP_BLOCK_17 0x00020000U /*!< OTP Block17 */ 627 #define FLASH_OTP_BLOCK_18 0x00040000U /*!< OTP Block18 */ 628 #define FLASH_OTP_BLOCK_19 0x00080000U /*!< OTP Block19 */ 629 #define FLASH_OTP_BLOCK_20 0x00100000U /*!< OTP Block20 */ 630 #define FLASH_OTP_BLOCK_21 0x00200000U /*!< OTP Block21 */ 631 #define FLASH_OTP_BLOCK_22 0x00400000U /*!< OTP Block22 */ 632 #define FLASH_OTP_BLOCK_23 0x00800000U /*!< OTP Block23 */ 633 #define FLASH_OTP_BLOCK_24 0x01000000U /*!< OTP Block24 */ 634 #define FLASH_OTP_BLOCK_25 0x02000000U /*!< OTP Block25 */ 635 #define FLASH_OTP_BLOCK_26 0x04000000U /*!< OTP Block26 */ 636 #define FLASH_OTP_BLOCK_27 0x08000000U /*!< OTP Block27 */ 637 #define FLASH_OTP_BLOCK_28 0x10000000U /*!< OTP Block28 */ 638 #define FLASH_OTP_BLOCK_29 0x20000000U /*!< OTP Block29 */ 639 #define FLASH_OTP_BLOCK_30 0x40000000U /*!< OTP Block30 */ 640 #define FLASH_OTP_BLOCK_31 0x80000000U /*!< OTP Block31 */ 641 #define FLASH_OTP_BLOCK_ALL 0xFFFFFFFFU /*!< OTP All Blocks */ 642 /** 643 * @} 644 */ 645 646 /** @defgroup FLASH_WRP_State FLASH WRP State 647 * @{ 648 */ 649 #define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired flash sectors */ 650 #define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired flash sectors */ 651 /** 652 * @} 653 */ 654 655 /** @defgroup FLASH_OB_BOOT_CONFIG FLASH Option Bytes Boot configuration 656 * @{ 657 */ 658 #define OB_BOOT_NS 0x00000001U /*!< Non-secure boot address */ 659 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 660 #define OB_BOOT_SEC 0x00000002U /*!< Secure boot address */ 661 #endif /* __ARM_FEATURE_CMSE */ 662 /** 663 * @} 664 */ 665 666 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 667 * @{ 668 */ 669 #define OB_BOOT_LOCK_DISABLE 0xC3U /*!< Boot lock disable */ 670 #define OB_BOOT_LOCK_ENABLE 0xB4U /*!< Boot lock enable */ 671 /** 672 * @} 673 */ 674 675 /** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes 676 * @{ 677 */ 678 #define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */ 679 #define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */ 680 /** 681 * @} 682 */ 683 684 /** @defgroup FLASH_PRIV_MODE FLASH privilege mode 685 * @{ 686 */ 687 #define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted to privileged 688 or unprivileged access */ 689 #define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied to 690 non-privilege access */ 691 692 #define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged or 693 unprivileged access */ 694 #if defined (FLASH_PRIVCFGR_SPRIV) 695 #define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied to non-privilege 696 access */ 697 #endif /* FLASH_PRIVCFGR_SPRIV */ 698 /** 699 * @} 700 */ 701 702 #if defined (FLASH_SR_OBKERR) 703 /** @defgroup FLASH_OBK_SWAP_Offset FLASH OBK Swap Offset 704 * @{ 705 */ 706 #define FLASH_OBK_SWAP_OFFSET_NO_DATA 0x000U /*!< No data will be copied from current to alternate OBK */ 707 #define FLASH_OBK_SWAP_OFFSET_HDPL0 0x010U /*!< HDPL0 data will be copied from current to alternate OBK */ 708 #define FLASH_OBK_SWAP_OFFSET_HDPL1 0x090U /*!< HDPL0/1 data will be copied from current to alternate OBK */ 709 #define FLASH_OBK_SWAP_OFFSET_HDPL2 0x0C0U /*!< HDPL0/1/2 data will be copied from current to alternate OBK */ 710 #define FLASH_OBK_SWAP_OFFSET_HDPL3_S 0x180U /*!< HDPL0/1/2/3_S data will be copied from current to alternate 711 OBK */ 712 #define FLASH_OBK_SWAP_OFFSET_ALL 0x1FFU /*!< All OBK data (511) will be copied from current to alternate 713 OBK */ 714 /** 715 * @} 716 */ 717 #endif /* FLASH_SR_OBKERR */ 718 719 /** @defgroup FLASH_Operation_Type FLASH Operation Type 720 * @{ 721 */ 722 #define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ 723 #define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ 724 #if defined (FLASH_SR_OBKERR) 725 #define FLASH_OPERATION_TYPE_OBKALTERASE FLASH_OPSR_CODE_OP_1 /*!< OBK alternate sector erase 726 operation */ 727 #endif /* FLASH_SR_OBKERR */ 728 #define FLASH_OPERATION_TYPE_SECTORERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Sector erase operation */ 729 #define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */ 730 #define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ 731 #define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ 732 #if defined (FLASH_SR_OBKERR) 733 #define FLASH_OPERATION_TYPE_OBKSWAP (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< OBK 734 swap operation */ 735 #endif /* FLASH_SR_OBKERR */ 736 /** 737 * @} 738 */ 739 740 /** @defgroup FLASH_Operation_Area FLASH Operation Area 741 * @{ 742 */ 743 #define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Flash Bank 1 */ 744 #define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Flash Bank 2 */ 745 #define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */ 746 #if defined (FLASH_EDATAR_EDATA_EN) 747 #define FLASH_OPERATION_AREA_DATA FLASH_OPSR_DATA_OP /*!< Operation in Flash high-cycle data area */ 748 #endif /* FLASH_EDATAR_EDATA_EN */ 749 #define FLASH_OPERATION_AREA_OTP FLASH_OPSR_OTP_OP /*!< Operation in Flash OTP area */ 750 /** 751 * @} 752 */ 753 754 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 755 /** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration 756 * @{ 757 */ 758 #define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */ 759 #define FLASH_INV_ENABLE FLASH_CR_INV /*!< Security state of Flash is inverted */ 760 /** 761 * @} 762 */ 763 #endif /* __ARM_FEATURE_CMSE */ 764 /** 765 * @} 766 */ 767 /* Exported macros ------------------------------------------------------------*/ 768 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros 769 * @{ 770 */ 771 772 /** 773 * @brief Enable the FLASH prefetch buffer. 774 * @retval None 775 */ 776 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 777 778 /** 779 * @brief Disable the FLASH prefetch buffer. 780 * @retval None 781 */ 782 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 783 784 /** 785 * @brief Enable the FLASH smart prefetch buffer. 786 * @retval None 787 */ 788 #define __HAL_FLASH_SMART_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) 789 790 /** 791 * @brief Disable the FLASH smart prefetch buffer. 792 * @retval None 793 */ 794 #define __HAL_FLASH_SMART_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) 795 796 /** 797 * @brief Set the FLASH Programming Delay. 798 * @param __DELAY__ FLASH Programming Delay 799 * This parameter can be a value of @ref FLASH_Programming_Delay 800 * @retval none 801 */ 802 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) 803 804 /** 805 * @brief Get the FLASH Programming Delay. 806 * @retval FLASH Programming Delay 807 * This return value can be a value of @ref FLASH_Programming_Delay 808 */ 809 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) 810 811 /** 812 * @} 813 */ 814 /* Exported functions --------------------------------------------------------*/ 815 /** @addtogroup FLASHEx_Exported_Functions 816 * @{ 817 */ 818 819 /** @addtogroup FLASHEx_Exported_Functions_Group1 820 * @{ 821 */ 822 /* Extension Erase and OB Program operation functions ******************************/ 823 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); 824 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 825 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 826 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 827 #if defined (FLASH_SR_OBKERR) 828 HAL_StatusTypeDef HAL_FLASHEx_OBK_Unlock(void); 829 HAL_StatusTypeDef HAL_FLASHEx_OBK_Lock(void); 830 HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset); 831 #endif /* FLASH_SR_OBKERR */ 832 #if defined (FLASH_SR_PUF_STATE) 833 HAL_StatusTypeDef HAL_FLASHEx_PUF_Launch(void); 834 #endif /* FLASH_SR_PUF_STATE */ 835 836 void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); 837 /** 838 * @} 839 */ 840 841 /** @addtogroup FLASHEx_Exported_Functions_Group2 842 * @{ 843 */ 844 /* Extension Protection configuration functions *************************************/ 845 HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); 846 void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); 847 void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); 848 uint32_t HAL_FLASHEx_GetPrivMode(void); 849 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 850 HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); 851 uint32_t HAL_FLASHEx_GetSecInversion(void); 852 #endif /* __ARM_FEATURE_CMSE */ 853 HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(FLASH_HDPExtensionTypeDef *pHDPExtension); 854 /** 855 * @} 856 */ 857 858 /** 859 * @} 860 */ 861 /* Private types -------------------------------------------------------------*/ 862 /* Private variables ---------------------------------------------------------*/ 863 /* Private constants ---------------------------------------------------------*/ 864 /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants 865 * @{ 866 */ 867 #define FLASH_TYPEPROGRAM_OB (0x00008000U | FLASH_NON_SECURE_MASK) /*!< Program Option Bytes operation type */ 868 /** 869 * @} 870 */ 871 /* Private macros ------------------------------------------------------------*/ 872 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros 873 * @{ 874 */ 875 876 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters 877 * @{ 878 */ 879 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 880 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 881 ((VALUE) == FLASH_TYPEERASE_SECTORS_NS) || \ 882 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 883 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS) || \ 884 ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) 885 #else 886 #if defined (FLASH_SR_OBKERR) 887 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 888 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 889 ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) 890 #else 891 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 892 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 893 #endif /* FLASH_SR_OBKERR */ 894 #endif /* __ARM_FEATURE_CMSE */ 895 896 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ 897 ((VALUE) == OB_WRPSTATE_ENABLE)) 898 899 #define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ 900 (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) 901 902 #define IS_OB_PRODUCT_STATE(STATE) (((STATE) == OB_PROD_STATE_OPEN) || \ 903 ((STATE) == OB_PROD_STATE_PROVISIONING) || \ 904 ((STATE) == OB_PROD_STATE_IROT_PROVISIONED) || \ 905 ((STATE) == OB_PROD_STATE_TZ_CLOSED) || \ 906 ((STATE) == OB_PROD_STATE_CLOSED) || \ 907 ((STATE) == OB_PROD_STATE_LOCKED) || \ 908 ((STATE) == OB_PROD_STATE_REGRESSION) || \ 909 ((STATE) == OB_PROD_STATE_NS_REGRESSION)) 910 911 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_1) || ((LEVEL) == OB_BOR_LEVEL_2) || \ 912 ((LEVEL) == OB_BOR_LEVEL_3)) 913 914 #define IS_OB_USER_BORH_EN(VALUE) (((VALUE) == OB_BORH_DISABLE) || ((VALUE) == OB_BORH_ENABLE)) 915 916 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 917 918 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 919 920 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 921 922 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 923 924 #define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || \ 925 ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) 926 927 #define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE) || \ 928 ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) 929 930 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) 931 932 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) 933 934 #define IS_OB_USER_BOOT_UBE(VALUE) (((VALUE) == OB_UBE_OEM_IROT) || ((VALUE) == OB_UBE_ST_IROT)) 935 936 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 937 938 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 939 #define IS_OB_USER_SRAM1_3_RST(VALUE) (((VALUE) == OB_SRAM1_3_RST_ERASE) || ((VALUE) == OB_SRAM1_3_RST_NOT_ERASE)) 940 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 941 942 #if defined (FLASH_OPTSR2_SRAM1_RST) 943 #define IS_OB_USER_SRAM1_RST(VALUE) (((VALUE) == OB_SRAM1_RST_ERASE) || ((VALUE) == OB_SRAM1_RST_NOT_ERASE)) 944 #endif /* FLASH_OPTSR2_SRAM1_RST */ 945 946 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 947 948 #define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) 949 950 #if defined (FLASH_OPTSR2_SRAM3_ECC) 951 #define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) 952 #endif /* FLASH_OPTSR2_SRAM3_ECC */ 953 954 #if defined (FLASH_OPTSR2_SRAM1_ECC) 955 #define IS_OB_USER_SRAM1_ECC(VALUE) (((VALUE) == OB_SRAM1_ECC_ENABLE) || ((VALUE) == OB_SRAM1_ECC_DISABLE)) 956 #endif /* FLASH_OPTSR2_SRAM1_ECC */ 957 958 #define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) 959 960 #if defined (FLASH_SR_PUF_STATE) 961 #define IS_OB_USER_HUK_PUF(VALUE) (((VALUE) == OB_UNIQUE_KEY_HUK) || ((VALUE) == OB_UNIQUE_KEY_PUF)) 962 #endif /* FLASH_SR_PUF_STATE */ 963 964 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 965 966 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ 967 (((TYPE) & ~OB_USER_ALL) == 0U)) 968 969 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 970 #define IS_OB_BOOT_CONFIG(CFG) (((CFG) == OB_BOOT_NS) || ((CFG) == OB_BOOT_SEC)) 971 #else 972 #define IS_OB_BOOT_CONFIG(CFG) ((CFG) == OB_BOOT_NS) 973 #endif /* __ARM_FEATURE_CMSE */ 974 975 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 976 977 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 978 #define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || ((CFG) == FLASH_BB_PRIV)) 979 #else 980 #define IS_FLASH_BB_EXCLUSIVE(CFG) ((CFG) == FLASH_BB_PRIV) 981 #endif /* __ARM_FEATURE_CMSE */ 982 983 #define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U) 984 985 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 986 #define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || ((CFG) == FLASH_INV_ENABLE)) 987 #endif /* __ARM_FEATURE_CMSE */ 988 989 #define IS_FLASH_EDATA_SIZE(SECTOR) ((SECTOR) <= FLASH_EDATA_SECTOR_NB) 990 /** 991 * @} 992 */ 993 994 /** 995 * @} 996 */ 997 /* Private functions ---------------------------------------------------------*/ 998 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions 999 * @{ 1000 */ 1001 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks); 1002 /** 1003 * @} 1004 */ 1005 1006 /** 1007 * @} 1008 */ 1009 1010 /** 1011 * @} 1012 */ 1013 1014 /** 1015 * @} 1016 */ 1017 1018 #ifdef __cplusplus 1019 } 1020 #endif 1021 1022 #endif /* STM32H5xx_HAL_FLASH_EX_H */ 1023
