1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_usb.c
4 * @author MCD Application Team
5 * @brief USB Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the USB Peripheral Controller:
9 * + Initialization/de-initialization functions
10 * + I/O operation functions
11 * + Peripheral Control functions
12 * + Peripheral State functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
20
21 (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
22
23 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
24
25 @endverbatim
26 ******************************************************************************
27 * @attention
28 *
29 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
30 *
31 * Redistribution and use in source and binary forms, with or without modification,
32 * are permitted provided that the following conditions are met:
33 * 1. Redistributions of source code must retain the above copyright notice,
34 * this list of conditions and the following disclaimer.
35 * 2. Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following disclaimer in the documentation
37 * and/or other materials provided with the distribution.
38 * 3. Neither the name of STMicroelectronics nor the names of its contributors
39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
45 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
48 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
49 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
51 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 *
53 ******************************************************************************
54 */
55
56 /* Includes ------------------------------------------------------------------*/
57 #include "stm32l4xx_hal.h"
58
59 /** @addtogroup STM32L4xx_LL_USB_DRIVER
60 * @{
61 */
62
63 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
64
65 #if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS)
66
67 /* Private typedef -----------------------------------------------------------*/
68 /* Private define ------------------------------------------------------------*/
69 /* Private macro -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private function prototypes -----------------------------------------------*/
72 /* Private functions ---------------------------------------------------------*/
73 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
74 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
75
76 /* Exported functions --------------------------------------------------------*/
77 /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
78 * @{
79 */
80
81 /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
82 * @brief Initialization and Configuration functions
83 *
84 @verbatim
85 ===============================================================================
86 ##### Initialization/de-initialization functions #####
87 ===============================================================================
88
89 @endverbatim
90 * @{
91 */
92
93 /**
94 * @brief Initializes the USB Core
95 * @param USBx USB Instance
96 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
97 * the configuration information for the specified USBx peripheral.
98 * @retval HAL status
99 */
USB_CoreInit(USB_OTG_GlobalTypeDef * USBx,USB_OTG_CfgTypeDef cfg)100 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
101 {
102 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
103 {
104 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
105
106 /* Init The ULPI Interface */
107 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
108
109 /* Select vbus source */
110 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
111 if (cfg.use_external_vbus == 1U)
112 {
113 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
114 }
115 /* Reset after a PHY select */
116 (void)USB_CoreReset(USBx);
117 }
118 else /* FS interface (embedded Phy) */
119 {
120 /* Select FS Embedded PHY */
121 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
122
123 /* Reset after a PHY select and set Host mode */
124 (void)USB_CoreReset(USBx);
125
126 /* Deactivate the power down*/
127 USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
128 }
129
130 return HAL_OK;
131 }
132
133 /**
134 * @brief USB_EnableGlobalInt
135 * Enables the controller's Global Int in the AHB Config reg
136 * @param USBx Selected device
137 * @retval HAL status
138 */
USB_EnableGlobalInt(USB_OTG_GlobalTypeDef * USBx)139 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
140 {
141 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
142 return HAL_OK;
143 }
144
145 /**
146 * @brief USB_DisableGlobalInt
147 * Disable the controller's Global Int in the AHB Config reg
148 * @param USBx Selected device
149 * @retval HAL status
150 */
USB_DisableGlobalInt(USB_OTG_GlobalTypeDef * USBx)151 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
152 {
153 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
154 return HAL_OK;
155 }
156
157 /**
158 * @brief USB_SetCurrentMode : Set functional mode
159 * @param USBx Selected device
160 * @param mode current core mode
161 * This parameter can be one of these values:
162 * @arg USB_DEVICE_MODE: Peripheral mode
163 * @arg USB_HOST_MODE: Host mode
164 * @arg USB_DRD_MODE: Dual Role Device mode
165 * @retval HAL status
166 */
USB_SetCurrentMode(USB_OTG_GlobalTypeDef * USBx,USB_ModeTypeDef mode)167 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
168 {
169 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
170
171 if (mode == USB_HOST_MODE)
172 {
173 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
174 }
175 else if (mode == USB_DEVICE_MODE)
176 {
177 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
178 }
179 else
180 {
181 return HAL_ERROR;
182 }
183 HAL_Delay(50U);
184
185 return HAL_OK;
186 }
187
188 /**
189 * @brief USB_DevInit : Initializes the USB_OTG controller registers
190 * for device mode
191 * @param USBx Selected device
192 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
193 * the configuration information for the specified USBx peripheral.
194 * @retval HAL status
195 */
USB_DevInit(USB_OTG_GlobalTypeDef * USBx,USB_OTG_CfgTypeDef cfg)196 HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
197 {
198 uint32_t USBx_BASE = (uint32_t)USBx;
199 uint32_t i;
200
201 for (i = 0U; i < 15U; i++)
202 {
203 USBx->DIEPTXF[i] = 0U;
204 }
205
206 /*Activate VBUS Sensing B */
207 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
208
209 if (cfg.vbus_sensing_enable == 0U)
210 {
211 /* Deactivate VBUS Sensing B */
212 USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
213
214 /* B-peripheral session valid override enable*/
215 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
216 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
217 }
218
219 /* Restart the Phy Clock */
220 USBx_PCGCCTL = 0U;
221
222 /* Device mode configuration */
223 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
224
225 /* Set Full speed phy */
226 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
227
228 /* Flush the FIFOs */
229 (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
230 (void)USB_FlushRxFifo(USBx);
231
232 /* Clear all pending Device Interrupts */
233 USBx_DEVICE->DIEPMSK = 0U;
234 USBx_DEVICE->DOEPMSK = 0U;
235 USBx_DEVICE->DAINTMSK = 0U;
236
237 for (i = 0U; i < cfg.dev_endpoints; i++)
238 {
239 if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
240 {
241 if (i == 0U)
242 {
243 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
244 }
245 else
246 {
247 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
248 }
249 }
250 else
251 {
252 USBx_INEP(i)->DIEPCTL = 0U;
253 }
254
255 USBx_INEP(i)->DIEPTSIZ = 0U;
256 USBx_INEP(i)->DIEPINT = 0xFB7FU;
257 }
258
259 for (i = 0U; i < cfg.dev_endpoints; i++)
260 {
261 if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
262 {
263 if (i == 0U)
264 {
265 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
266 }
267 else
268 {
269 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
270 }
271 }
272 else
273 {
274 USBx_OUTEP(i)->DOEPCTL = 0U;
275 }
276
277 USBx_OUTEP(i)->DOEPTSIZ = 0U;
278 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
279 }
280
281 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
282
283 /* Disable all interrupts. */
284 USBx->GINTMSK = 0U;
285
286 /* Clear any pending interrupts */
287 USBx->GINTSTS = 0xBFFFFFFFU;
288
289 /* Enable the common interrupts */
290 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
291
292 /* Enable interrupts matching to the Device mode ONLY */
293 USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
294 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
295 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
296 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
297
298 if (cfg.Sof_enable != 0U)
299 {
300 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
301 }
302
303 if (cfg.vbus_sensing_enable == 1U)
304 {
305 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
306 }
307
308 return HAL_OK;
309 }
310
311 /**
312 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
313 * @param USBx Selected device
314 * @param num FIFO number
315 * This parameter can be a value from 1 to 15
316 15 means Flush all Tx FIFOs
317 * @retval HAL status
318 */
USB_FlushTxFifo(USB_OTG_GlobalTypeDef * USBx,uint32_t num)319 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
320 {
321 uint32_t count = 0U;
322
323 USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
324
325 do
326 {
327 if (++count > 200000U)
328 {
329 return HAL_TIMEOUT;
330 }
331 }
332 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
333
334 return HAL_OK;
335 }
336
337 /**
338 * @brief USB_FlushRxFifo : Flush Rx FIFO
339 * @param USBx Selected device
340 * @retval HAL status
341 */
USB_FlushRxFifo(USB_OTG_GlobalTypeDef * USBx)342 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
343 {
344 uint32_t count = 0;
345
346 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
347
348 do
349 {
350 if (++count > 200000U)
351 {
352 return HAL_TIMEOUT;
353 }
354 }
355 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
356
357 return HAL_OK;
358 }
359
360 /**
361 * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
362 * depending the PHY type and the enumeration speed of the device.
363 * @param USBx Selected device
364 * @param speed device speed
365 * This parameter can be one of these values:
366 * @arg USB_OTG_SPEED_FULL: Full speed mode
367 * @arg USB_OTG_SPEED_LOW: Low speed mode
368 * @retval Hal status
369 */
USB_SetDevSpeed(USB_OTG_GlobalTypeDef * USBx,uint8_t speed)370 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
371 {
372 uint32_t USBx_BASE = (uint32_t)USBx;
373
374 USBx_DEVICE->DCFG |= speed;
375 return HAL_OK;
376 }
377
378 /**
379 * @brief USB_GetDevSpeed :Return the Dev Speed
380 * @param USBx Selected device
381 * @retval speed : device speed
382 * This parameter can be one of these values:
383 * @arg USB_OTG_SPEED_FULL: Full speed mode
384 * @arg USB_OTG_SPEED_LOW: Low speed mode
385 */
USB_GetDevSpeed(USB_OTG_GlobalTypeDef * USBx)386 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
387 {
388 uint32_t USBx_BASE = (uint32_t)USBx;
389 uint8_t speed;
390 uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
391
392 if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
393 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
394 {
395 speed = USB_OTG_SPEED_FULL;
396 }
397 else if (DevEnumSpeed == DSTS_ENUMSPD_LS_PHY_6MHZ)
398 {
399 speed = USB_OTG_SPEED_LOW;
400 }
401 else
402 {
403 speed = 0U;
404 }
405
406 return speed;
407 }
408
409 /**
410 * @brief Activate and configure an endpoint
411 * @param USBx Selected device
412 * @param ep pointer to endpoint structure
413 * @retval HAL status
414 */
USB_ActivateEndpoint(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)415 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
416 {
417 uint32_t USBx_BASE = (uint32_t)USBx;
418 uint32_t epnum = (uint32_t)ep->num;
419
420 if (ep->is_in == 1U)
421 {
422 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU));
423
424 if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
425 {
426 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
427 ((uint32_t)ep->type << 18) | (epnum << 22) |
428 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
429 USB_OTG_DIEPCTL_USBAEP;
430 }
431 }
432 else
433 {
434 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16);
435
436 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
437 {
438 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
439 ((uint32_t)ep->type << 18) |
440 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
441 USB_OTG_DOEPCTL_USBAEP;
442 }
443 }
444 return HAL_OK;
445 }
446
447 /**
448 * @brief Activate and configure a dedicated endpoint
449 * @param USBx Selected device
450 * @param ep pointer to endpoint structure
451 * @retval HAL status
452 */
USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)453 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
454 {
455 uint32_t USBx_BASE = (uint32_t)USBx;
456 uint32_t epnum = (uint32_t)ep->num;
457
458 /* Read DEPCTLn register */
459 if (ep->is_in == 1U)
460 {
461 if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
462 {
463 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
464 ((uint32_t)ep->type << 18) | (epnum << 22) |
465 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
466 USB_OTG_DIEPCTL_USBAEP;
467 }
468
469 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU));
470 }
471 else
472 {
473 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
474 {
475 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
476 ((uint32_t)ep->type << 18) | (epnum << 22) |
477 USB_OTG_DOEPCTL_USBAEP;
478 }
479
480 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16);
481 }
482
483 return HAL_OK;
484 }
485
486 /**
487 * @brief De-activate and de-initialize an endpoint
488 * @param USBx Selected device
489 * @param ep pointer to endpoint structure
490 * @retval HAL status
491 */
USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)492 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
493 {
494 uint32_t USBx_BASE = (uint32_t)USBx;
495 uint32_t epnum = (uint32_t)ep->num;
496
497 /* Read DEPCTLn register */
498 if (ep->is_in == 1U)
499 {
500 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));
501 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));
502 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
503 USB_OTG_DIEPCTL_MPSIZ |
504 USB_OTG_DIEPCTL_TXFNUM |
505 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
506 USB_OTG_DIEPCTL_EPTYP);
507 }
508 else
509 {
510 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));
511 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));
512 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
513 USB_OTG_DOEPCTL_MPSIZ |
514 USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
515 USB_OTG_DOEPCTL_EPTYP);
516 }
517
518 return HAL_OK;
519 }
520
521 /**
522 * @brief De-activate and de-initialize a dedicated endpoint
523 * @param USBx Selected device
524 * @param ep pointer to endpoint structure
525 * @retval HAL status
526 */
USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)527 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
528 {
529 uint32_t USBx_BASE = (uint32_t)USBx;
530 uint32_t epnum = (uint32_t)ep->num;
531
532 /* Read DEPCTLn register */
533 if (ep->is_in == 1U)
534 {
535 USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
536 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));
537 }
538 else
539 {
540 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
541 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));
542 }
543
544 return HAL_OK;
545 }
546
547 /**
548 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
549 * @param USBx Selected device
550 * @param ep pointer to endpoint structure
551 * @retval HAL status
552 */
USB_EPStartXfer(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)553 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
554 {
555 uint32_t USBx_BASE = (uint32_t)USBx;
556 uint32_t epnum = (uint32_t)ep->num;
557 uint16_t pktcnt;
558
559 /* IN endpoint */
560 if (ep->is_in == 1U)
561 {
562 /* Zero Length Packet? */
563 if (ep->xfer_len == 0U)
564 {
565 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
566 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
567 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
568 }
569 else
570 {
571 /* Program the transfer size and packet count
572 * as follows: xfersize = N * maxpacket +
573 * short_packet pktcnt = N + (short_packet
574 * exist ? 1 : 0)
575 */
576 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
577 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
578 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
579 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
580
581 if (ep->type == EP_TYPE_ISOC)
582 {
583 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
584 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
585 }
586 }
587
588 if (ep->type != EP_TYPE_ISOC)
589 {
590 /* Enable the Tx FIFO Empty Interrupt for this EP */
591 if (ep->xfer_len > 0U)
592 {
593 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU);
594 }
595 }
596
597 if (ep->type == EP_TYPE_ISOC)
598 {
599 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
600 {
601 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
602 }
603 else
604 {
605 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
606 }
607 }
608
609 /* EP enable, IN data in FIFO */
610 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
611
612 if (ep->type == EP_TYPE_ISOC)
613 {
614 (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len);
615 }
616 }
617 else /* OUT endpoint */
618 {
619 /* Program the transfer size and packet count as follows:
620 * pktcnt = N
621 * xfersize = N * maxpacket
622 */
623 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
624 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
625
626 if (ep->xfer_len == 0U)
627 {
628 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
629 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
630 }
631 else
632 {
633 pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
634 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
635 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
636 }
637
638 if (ep->type == EP_TYPE_ISOC)
639 {
640 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
641 {
642 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
643 }
644 else
645 {
646 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
647 }
648 }
649 /* EP enable */
650 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
651 }
652
653 return HAL_OK;
654 }
655
656 /**
657 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
658 * @param USBx Selected device
659 * @param ep pointer to endpoint structure
660 * @retval HAL status
661 */
USB_EP0StartXfer(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)662 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
663 {
664 uint32_t USBx_BASE = (uint32_t)USBx;
665 uint32_t epnum = (uint32_t)ep->num;
666
667 /* IN endpoint */
668 if (ep->is_in == 1U)
669 {
670 /* Zero Length Packet? */
671 if (ep->xfer_len == 0U)
672 {
673 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
674 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
675 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
676 }
677 else
678 {
679 /* Program the transfer size and packet count
680 * as follows: xfersize = N * maxpacket +
681 * short_packet pktcnt = N + (short_packet
682 * exist ? 1 : 0)
683 */
684 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
685 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
686
687 if (ep->xfer_len > ep->maxpacket)
688 {
689 ep->xfer_len = ep->maxpacket;
690 }
691 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
692 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
693 }
694
695 /* Enable the Tx FIFO Empty Interrupt for this EP */
696 if (ep->xfer_len > 0U)
697 {
698 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU);
699 }
700
701 /* EP enable, IN data in FIFO */
702 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
703 }
704 else /* OUT endpoint */
705 {
706 /* Program the transfer size and packet count as follows:
707 * pktcnt = N
708 * xfersize = N * maxpacket
709 */
710 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
711 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
712
713 if (ep->xfer_len > 0U)
714 {
715 ep->xfer_len = ep->maxpacket;
716 }
717
718 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
719 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
720
721 /* EP enable */
722 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
723 }
724
725 return HAL_OK;
726 }
727
728 /**
729 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
730 * with the EP/channel
731 * @param USBx Selected device
732 * @param src pointer to source buffer
733 * @param ch_ep_num endpoint or host channel number
734 * @param len Number of bytes to write
735 * @retval HAL status
736 */
USB_WritePacket(USB_OTG_GlobalTypeDef * USBx,uint8_t * src,uint8_t ch_ep_num,uint16_t len)737 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
738 {
739 uint32_t USBx_BASE = (uint32_t)USBx;
740 uint32_t *pSrc = (uint32_t *)src;
741 uint32_t count32b, i;
742
743 count32b = ((uint32_t)len + 3U) / 4U;
744 for (i = 0U; i < count32b; i++)
745 {
746 USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc);
747 pSrc++;
748 }
749
750 return HAL_OK;
751 }
752
753 /**
754 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
755 * with the EP/channel
756 * @param USBx Selected device
757 * @param dest source pointer
758 * @param len Number of bytes to read
759 * @retval pointer to destination buffer
760 */
USB_ReadPacket(USB_OTG_GlobalTypeDef * USBx,uint8_t * dest,uint16_t len)761 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
762 {
763 uint32_t USBx_BASE = (uint32_t)USBx;
764 uint32_t *pDest = (uint32_t *)dest;
765 uint32_t i;
766 uint32_t count32b = ((uint32_t)len + 3U) / 4U;
767
768 for (i = 0U; i < count32b; i++)
769 {
770 *(__packed uint32_t *)pDest = USBx_DFIFO(0U);
771 pDest++;
772 }
773
774 return ((void *)pDest);
775 }
776
777 /**
778 * @brief USB_EPSetStall : set a stall condition over an EP
779 * @param USBx Selected device
780 * @param ep pointer to endpoint structure
781 * @retval HAL status
782 */
USB_EPSetStall(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)783 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
784 {
785 uint32_t USBx_BASE = (uint32_t)USBx;
786 uint32_t epnum = (uint32_t)ep->num;
787
788 if (ep->is_in == 1U)
789 {
790 if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
791 {
792 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
793 }
794 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
795 }
796 else
797 {
798 if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
799 {
800 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
801 }
802 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
803 }
804
805 return HAL_OK;
806 }
807
808 /**
809 * @brief USB_EPClearStall : Clear a stall condition over an EP
810 * @param USBx Selected device
811 * @param ep pointer to endpoint structure
812 * @retval HAL status
813 */
USB_EPClearStall(USB_OTG_GlobalTypeDef * USBx,USB_OTG_EPTypeDef * ep)814 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
815 {
816 uint32_t USBx_BASE = (uint32_t)USBx;
817 uint32_t epnum = (uint32_t)ep->num;
818
819 if (ep->is_in == 1U)
820 {
821 USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
822 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
823 {
824 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
825 }
826 }
827 else
828 {
829 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
830 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
831 {
832 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
833 }
834 }
835 return HAL_OK;
836 }
837
838 /**
839 * @brief USB_StopDevice : Stop the usb device mode
840 * @param USBx Selected device
841 * @retval HAL status
842 */
USB_StopDevice(USB_OTG_GlobalTypeDef * USBx)843 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
844 {
845 uint32_t USBx_BASE = (uint32_t)USBx;
846 uint32_t i;
847
848 /* Clear Pending interrupt */
849 for (i = 0U; i < 15U; i++)
850 {
851 USBx_INEP(i)->DIEPINT = 0xFB7FU;
852 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
853 }
854
855 /* Clear interrupt masks */
856 USBx_DEVICE->DIEPMSK = 0U;
857 USBx_DEVICE->DOEPMSK = 0U;
858 USBx_DEVICE->DAINTMSK = 0U;
859
860 /* Flush the FIFO */
861 (void)USB_FlushRxFifo(USBx);
862 (void)USB_FlushTxFifo(USBx, 0x10U);
863
864 return HAL_OK;
865 }
866
867 /**
868 * @brief USB_SetDevAddress : Stop the usb device mode
869 * @param USBx Selected device
870 * @param address new device address to be assigned
871 * This parameter can be a value from 0 to 255
872 * @retval HAL status
873 */
USB_SetDevAddress(USB_OTG_GlobalTypeDef * USBx,uint8_t address)874 HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
875 {
876 uint32_t USBx_BASE = (uint32_t)USBx;
877
878 USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
879 USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
880
881 return HAL_OK;
882 }
883
884 /**
885 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
886 * @param USBx Selected device
887 * @retval HAL status
888 */
USB_DevConnect(USB_OTG_GlobalTypeDef * USBx)889 HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
890 {
891 uint32_t USBx_BASE = (uint32_t)USBx;
892
893 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
894 HAL_Delay(3U);
895
896 return HAL_OK;
897 }
898
899 /**
900 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
901 * @param USBx Selected device
902 * @retval HAL status
903 */
USB_DevDisconnect(USB_OTG_GlobalTypeDef * USBx)904 HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
905 {
906 uint32_t USBx_BASE = (uint32_t)USBx;
907
908 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
909 HAL_Delay(3U);
910
911 return HAL_OK;
912 }
913
914 /**
915 * @brief USB_ReadInterrupts: return the global USB interrupt status
916 * @param USBx Selected device
917 * @retval HAL status
918 */
USB_ReadInterrupts(USB_OTG_GlobalTypeDef * USBx)919 uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
920 {
921 uint32_t tmpreg;
922
923 tmpreg = USBx->GINTSTS;
924 tmpreg &= USBx->GINTMSK;
925
926 return tmpreg;
927 }
928
929 /**
930 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
931 * @param USBx Selected device
932 * @retval HAL status
933 */
USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef * USBx)934 uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
935 {
936 uint32_t USBx_BASE = (uint32_t)USBx;
937 uint32_t tmpreg;
938
939 tmpreg = USBx_DEVICE->DAINT;
940 tmpreg &= USBx_DEVICE->DAINTMSK;
941
942 return ((tmpreg & 0xffff0000U) >> 16);
943 }
944
945 /**
946 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
947 * @param USBx Selected device
948 * @retval HAL status
949 */
USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef * USBx)950 uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
951 {
952 uint32_t USBx_BASE = (uint32_t)USBx;
953 uint32_t tmpreg;
954
955 tmpreg = USBx_DEVICE->DAINT;
956 tmpreg &= USBx_DEVICE->DAINTMSK;
957
958 return ((tmpreg & 0xFFFFU));
959 }
960
961 /**
962 * @brief Returns Device OUT EP Interrupt register
963 * @param USBx Selected device
964 * @param epnum endpoint number
965 * This parameter can be a value from 0 to 15
966 * @retval Device OUT EP Interrupt register
967 */
USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef * USBx,uint8_t epnum)968 uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
969 {
970 uint32_t USBx_BASE = (uint32_t)USBx;
971 uint32_t tmpreg;
972
973 tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
974 tmpreg &= USBx_DEVICE->DOEPMSK;
975
976 return tmpreg;
977 }
978
979 /**
980 * @brief Returns Device IN EP Interrupt register
981 * @param USBx Selected device
982 * @param epnum endpoint number
983 * This parameter can be a value from 0 to 15
984 * @retval Device IN EP Interrupt register
985 */
USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef * USBx,uint8_t epnum)986 uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
987 {
988 uint32_t USBx_BASE = (uint32_t)USBx;
989 uint32_t tmpreg, msk, emp;
990
991 msk = USBx_DEVICE->DIEPMSK;
992 emp = USBx_DEVICE->DIEPEMPMSK;
993 msk |= ((emp >> (epnum & 0xFU)) & 0x1U) << 7;
994 tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
995
996 return tmpreg;
997 }
998
999 /**
1000 * @brief USB_ClearInterrupts: clear a USB interrupt
1001 * @param USBx Selected device
1002 * @param interrupt interrupt flag
1003 * @retval None
1004 */
USB_ClearInterrupts(USB_OTG_GlobalTypeDef * USBx,uint32_t interrupt)1005 void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
1006 {
1007 USBx->GINTSTS |= interrupt;
1008 }
1009
1010 /**
1011 * @brief Returns USB core mode
1012 * @param USBx Selected device
1013 * @retval return core mode : Host or Device
1014 * This parameter can be one of these values:
1015 * 0 : Host
1016 * 1 : Device
1017 */
USB_GetMode(USB_OTG_GlobalTypeDef * USBx)1018 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
1019 {
1020 return ((USBx->GINTSTS) & 0x1U);
1021 }
1022
1023 /**
1024 * @brief Activate EP0 for Setup transactions
1025 * @param USBx Selected device
1026 * @retval HAL status
1027 */
USB_ActivateSetup(USB_OTG_GlobalTypeDef * USBx)1028 HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
1029 {
1030 uint32_t USBx_BASE = (uint32_t)USBx;
1031
1032 /* Set the MPS of the IN EP based on the enumeration speed */
1033 USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
1034
1035 if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
1036 {
1037 USBx_INEP(0U)->DIEPCTL |= 3U;
1038 }
1039 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
1040
1041 return HAL_OK;
1042 }
1043
1044 /**
1045 * @brief Prepare the EP0 to start the first control setup
1046 * @param USBx Selected device
1047 * @param psetup pointer to setup packet
1048 * @retval HAL status
1049 */
USB_EP0_OutStart(USB_OTG_GlobalTypeDef * USBx,uint8_t * psetup)1050 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)
1051 {
1052 UNUSED(psetup);
1053 uint32_t USBx_BASE = (uint32_t)USBx;
1054
1055 USBx_OUTEP(0U)->DOEPTSIZ = 0U;
1056 USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
1057 USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
1058 USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
1059
1060 return HAL_OK;
1061 }
1062
1063 /**
1064 * @brief Reset the USB Core (needed after USB clock settings change)
1065 * @param USBx Selected device
1066 * @retval HAL status
1067 */
USB_CoreReset(USB_OTG_GlobalTypeDef * USBx)1068 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
1069 {
1070 uint32_t count = 0U;
1071
1072 /* Wait for AHB master IDLE state. */
1073 do
1074 {
1075 if (++count > 200000U)
1076 {
1077 return HAL_TIMEOUT;
1078 }
1079 }
1080 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
1081
1082 /* Core Soft Reset */
1083 count = 0U;
1084 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
1085
1086 do
1087 {
1088 if (++count > 200000U)
1089 {
1090 return HAL_TIMEOUT;
1091 }
1092 }
1093 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
1094
1095 return HAL_OK;
1096 }
1097
1098 /**
1099 * @brief USB_HostInit : Initializes the USB OTG controller registers
1100 * for Host mode
1101 * @param USBx Selected device
1102 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
1103 * the configuration information for the specified USBx peripheral.
1104 * @retval HAL status
1105 */
USB_HostInit(USB_OTG_GlobalTypeDef * USBx,USB_OTG_CfgTypeDef cfg)1106 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
1107 {
1108 uint32_t USBx_BASE = (uint32_t)USBx;
1109 uint32_t i;
1110
1111 /* Restart the Phy Clock */
1112 USBx_PCGCCTL = 0U;
1113
1114 /* Disable VBUS sensing */
1115 USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
1116
1117 /* Disable Battery chargin detector */
1118 USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
1119
1120 /* Disable the FS/LS support mode only */
1121 if ((cfg.speed == USB_OTG_SPEED_FULL) && (USBx != USB_OTG_FS))
1122 {
1123 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
1124 }
1125 else
1126 {
1127 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1128 }
1129
1130 /* Make sure the FIFOs are flushed. */
1131 (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
1132 (void)USB_FlushRxFifo(USBx);
1133
1134 /* Clear all pending HC Interrupts */
1135 for (i = 0U; i < cfg.Host_channels; i++)
1136 {
1137 USBx_HC(i)->HCINT = 0xFFFFFFFFU;
1138 USBx_HC(i)->HCINTMSK = 0U;
1139 }
1140
1141 /* Enable VBUS driving */
1142 (void)USB_DriveVbus(USBx, 1U);
1143
1144 HAL_Delay(200U);
1145
1146 /* Disable all interrupts. */
1147 USBx->GINTMSK = 0U;
1148
1149 /* Clear any pending interrupts */
1150 USBx->GINTSTS = 0xFFFFFFFFU;
1151
1152 if (USBx == USB_OTG_FS)
1153 {
1154 /* set Rx FIFO size */
1155 USBx->GRXFSIZ = 0x80U;
1156 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
1157 USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
1158 }
1159 else
1160 {
1161 /* set Rx FIFO size */
1162 USBx->GRXFSIZ = 0x200U;
1163 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
1164 USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
1165 }
1166
1167 /* Enable the common interrupts */
1168 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
1169
1170 /* Enable interrupts matching to the Host mode ONLY */
1171 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
1172 USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
1173 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
1174
1175 return HAL_OK;
1176 }
1177
1178 /**
1179 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
1180 * HCFG register on the PHY type and set the right frame interval
1181 * @param USBx Selected device
1182 * @param freq clock frequency
1183 * This parameter can be one of these values:
1184 * HCFG_48_MHZ : Full Speed 48 MHz Clock
1185 * HCFG_6_MHZ : Low Speed 6 MHz Clock
1186 * @retval HAL status
1187 */
USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef * USBx,uint8_t freq)1188 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
1189 {
1190 uint32_t USBx_BASE = (uint32_t)USBx;
1191
1192 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
1193 USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
1194
1195 if (freq == HCFG_48_MHZ)
1196 {
1197 USBx_HOST->HFIR = 48000U;
1198 }
1199 else if (freq == HCFG_6_MHZ)
1200 {
1201 USBx_HOST->HFIR = 6000U;
1202 }
1203 else
1204 {
1205 /* ... */
1206 }
1207
1208 return HAL_OK;
1209 }
1210
1211 /**
1212 * @brief USB_OTG_ResetPort : Reset Host Port
1213 * @param USBx Selected device
1214 * @retval HAL status
1215 * @note (1)The application must wait at least 10 ms
1216 * before clearing the reset bit.
1217 */
USB_ResetPort(USB_OTG_GlobalTypeDef * USBx)1218 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
1219 {
1220 uint32_t USBx_BASE = (uint32_t)USBx;
1221
1222 __IO uint32_t hprt0 = 0U;
1223
1224 hprt0 = USBx_HPRT0;
1225
1226 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1227 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1228
1229 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
1230 HAL_Delay(100U); /* See Note #1 */
1231 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
1232 HAL_Delay(10U);
1233
1234 return HAL_OK;
1235 }
1236
1237 /**
1238 * @brief USB_DriveVbus : activate or de-activate vbus
1239 * @param state VBUS state
1240 * This parameter can be one of these values:
1241 * 0 : VBUS Active
1242 * 1 : VBUS Inactive
1243 * @retval HAL status
1244 */
USB_DriveVbus(USB_OTG_GlobalTypeDef * USBx,uint8_t state)1245 HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
1246 {
1247 uint32_t USBx_BASE = (uint32_t)USBx;
1248 __IO uint32_t hprt0 = 0U;
1249
1250 hprt0 = USBx_HPRT0;
1251
1252 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1253 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1254
1255 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
1256 {
1257 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
1258 }
1259 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
1260 {
1261 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
1262 }
1263 return HAL_OK;
1264 }
1265
1266 /**
1267 * @brief Return Host Core speed
1268 * @param USBx Selected device
1269 * @retval speed : Host speed
1270 * This parameter can be one of these values:
1271 * @arg USB_OTG_SPEED_FULL: Full speed mode
1272 * @arg USB_OTG_SPEED_LOW: Low speed mode
1273 */
USB_GetHostSpeed(USB_OTG_GlobalTypeDef * USBx)1274 uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
1275 {
1276 uint32_t USBx_BASE = (uint32_t)USBx;
1277 __IO uint32_t hprt0 = 0U;
1278
1279 hprt0 = USBx_HPRT0;
1280 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
1281 }
1282
1283 /**
1284 * @brief Return Host Current Frame number
1285 * @param USBx Selected device
1286 * @retval current frame number
1287 */
USB_GetCurrentFrame(USB_OTG_GlobalTypeDef * USBx)1288 uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
1289 {
1290 uint32_t USBx_BASE = (uint32_t)USBx;
1291
1292 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
1293 }
1294
1295 /**
1296 * @brief Initialize a host channel
1297 * @param USBx Selected device
1298 * @param ch_num Channel number
1299 * This parameter can be a value from 1 to 15
1300 * @param epnum Endpoint number
1301 * This parameter can be a value from 1 to 15
1302 * @param dev_address Current device address
1303 * This parameter can be a value from 0 to 255
1304 * @param speed Current device speed
1305 * This parameter can be one of these values:
1306 * @arg USB_OTG_SPEED_FULL: Full speed mode
1307 * @arg USB_OTG_SPEED_LOW: Low speed mode
1308 * @param ep_type Endpoint Type
1309 * This parameter can be one of these values:
1310 * @arg EP_TYPE_CTRL: Control type
1311 * @arg EP_TYPE_ISOC: Isochronous type
1312 * @arg EP_TYPE_BULK: Bulk type
1313 * @arg EP_TYPE_INTR: Interrupt type
1314 * @param mps Max Packet Size
1315 * This parameter can be a value from 0 to32K
1316 * @retval HAL state
1317 */
USB_HC_Init(USB_OTG_GlobalTypeDef * USBx,uint8_t ch_num,uint8_t epnum,uint8_t dev_address,uint8_t speed,uint8_t ep_type,uint16_t mps)1318 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
1319 uint8_t ch_num,
1320 uint8_t epnum,
1321 uint8_t dev_address,
1322 uint8_t speed,
1323 uint8_t ep_type,
1324 uint16_t mps)
1325 {
1326 HAL_StatusTypeDef ret = HAL_OK;
1327 uint32_t USBx_BASE = (uint32_t)USBx;
1328 uint32_t HCcharEpDir, HCcharLowSpeed;
1329
1330 /* Clear old interrupt conditions for this host channel. */
1331 USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
1332
1333 /* Enable channel interrupts required for this transfer. */
1334 switch (ep_type)
1335 {
1336 case EP_TYPE_CTRL:
1337 case EP_TYPE_BULK:
1338 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1339 USB_OTG_HCINTMSK_STALLM |
1340 USB_OTG_HCINTMSK_TXERRM |
1341 USB_OTG_HCINTMSK_DTERRM |
1342 USB_OTG_HCINTMSK_AHBERR |
1343 USB_OTG_HCINTMSK_NAKM;
1344
1345 if ((epnum & 0x80U) == 0x80U)
1346 {
1347 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1348 }
1349 break;
1350
1351 case EP_TYPE_INTR:
1352 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1353 USB_OTG_HCINTMSK_STALLM |
1354 USB_OTG_HCINTMSK_TXERRM |
1355 USB_OTG_HCINTMSK_DTERRM |
1356 USB_OTG_HCINTMSK_NAKM |
1357 USB_OTG_HCINTMSK_AHBERR |
1358 USB_OTG_HCINTMSK_FRMORM;
1359
1360 if ((epnum & 0x80U) == 0x80U)
1361 {
1362 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1363 }
1364
1365 break;
1366
1367 case EP_TYPE_ISOC:
1368 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1369 USB_OTG_HCINTMSK_ACKM |
1370 USB_OTG_HCINTMSK_AHBERR |
1371 USB_OTG_HCINTMSK_FRMORM;
1372
1373 if ((epnum & 0x80U) == 0x80U)
1374 {
1375 USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
1376 }
1377 break;
1378
1379 default:
1380 ret = HAL_ERROR;
1381 break;
1382 }
1383
1384 /* Enable the top level host channel interrupt. */
1385 USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
1386
1387 /* Make sure host channel interrupts are enabled. */
1388 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
1389
1390 /* Program the HCCHAR register */
1391 if ((epnum & 0x80U) == 0x80U)
1392 {
1393 HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
1394 }
1395 else
1396 {
1397 HCcharEpDir = 0U;
1398 }
1399
1400 if (speed == HPRT0_PRTSPD_LOW_SPEED)
1401 {
1402 HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
1403 }
1404 else
1405 {
1406 HCcharLowSpeed = 0U;
1407 }
1408
1409 USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
1410 ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
1411 (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
1412 ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
1413
1414 if (ep_type == EP_TYPE_INTR)
1415 {
1416 USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
1417 }
1418
1419 return ret;
1420 }
1421
1422 /**
1423 * @brief Start a transfer over a host channel
1424 * @param USBx Selected device
1425 * @param hc pointer to host channel structure
1426 * @retval HAL state
1427 */
USB_HC_StartXfer(USB_OTG_GlobalTypeDef * USBx,USB_OTG_HCTypeDef * hc)1428 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc)
1429 {
1430 uint32_t USBx_BASE = (uint32_t)USBx;
1431 uint32_t ch_num = (uint32_t)hc->ch_num;
1432 static __IO uint32_t tmpreg = 0U;
1433 uint8_t is_oddframe;
1434 uint16_t len_words;
1435 uint16_t num_packets;
1436 uint16_t max_hc_pkt_count = 256U;
1437
1438 /* Compute the expected number of packets associated to the transfer */
1439 if (hc->xfer_len > 0U)
1440 {
1441 num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
1442
1443 if (num_packets > max_hc_pkt_count)
1444 {
1445 num_packets = max_hc_pkt_count;
1446 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1447 }
1448 }
1449 else
1450 {
1451 num_packets = 1U;
1452 }
1453 if (hc->ep_is_in != 0U)
1454 {
1455 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1456 }
1457
1458 /* Initialize the HCTSIZn register */
1459 USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
1460 (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
1461 (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
1462
1463 is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
1464 USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
1465 USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
1466
1467 /* Set host channel enable */
1468 tmpreg = USBx_HC(ch_num)->HCCHAR;
1469 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1470
1471 /* make sure to set the correct ep direction */
1472 if (hc->ep_is_in != 0U)
1473 {
1474 tmpreg |= USB_OTG_HCCHAR_EPDIR;
1475 }
1476 else
1477 {
1478 tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
1479 }
1480 tmpreg |= USB_OTG_HCCHAR_CHENA;
1481 USBx_HC(ch_num)->HCCHAR = tmpreg;
1482
1483 if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
1484 {
1485 switch (hc->ep_type)
1486 {
1487 /* Non periodic transfer */
1488 case EP_TYPE_CTRL:
1489 case EP_TYPE_BULK:
1490
1491 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1492
1493 /* check if there is enough space in FIFO space */
1494 if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
1495 {
1496 /* need to process data in nptxfempty interrupt */
1497 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
1498 }
1499 break;
1500
1501 /* Periodic transfer */
1502 case EP_TYPE_INTR:
1503 case EP_TYPE_ISOC:
1504 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1505 /* check if there is enough space in FIFO space */
1506 if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
1507 {
1508 /* need to process data in ptxfempty interrupt */
1509 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
1510 }
1511 break;
1512
1513 default:
1514 break;
1515 }
1516
1517 /* Write packet into the Tx FIFO. */
1518 (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len);
1519 }
1520
1521 return HAL_OK;
1522 }
1523
1524 /**
1525 * @brief Read all host channel interrupts status
1526 * @param USBx Selected device
1527 * @retval HAL state
1528 */
USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef * USBx)1529 uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
1530 {
1531 uint32_t USBx_BASE = (uint32_t)USBx;
1532
1533 return ((USBx_HOST->HAINT) & 0xFFFFU);
1534 }
1535
1536 /**
1537 * @brief Halt a host channel
1538 * @param USBx Selected device
1539 * @param hc_num Host Channel number
1540 * This parameter can be a value from 1 to 15
1541 * @retval HAL state
1542 */
USB_HC_Halt(USB_OTG_GlobalTypeDef * USBx,uint8_t hc_num)1543 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
1544 {
1545 uint32_t USBx_BASE = (uint32_t)USBx;
1546 uint32_t hcnum = (uint32_t)hc_num;
1547 uint32_t count = 0U;
1548 uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
1549
1550 /* Check for space in the request queue to issue the halt. */
1551 if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
1552 {
1553 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1554
1555 if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
1556 {
1557 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1558 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1559 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1560 do
1561 {
1562 if (++count > 1000U)
1563 {
1564 break;
1565 }
1566 }
1567 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1568 }
1569 else
1570 {
1571 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1572 }
1573 }
1574 else
1575 {
1576 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1577
1578 if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
1579 {
1580 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1581 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1582 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1583 do
1584 {
1585 if (++count > 1000U)
1586 {
1587 break;
1588 }
1589 }
1590 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1591 }
1592 else
1593 {
1594 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1595 }
1596 }
1597
1598 return HAL_OK;
1599 }
1600
1601 /**
1602 * @brief Initiate Do Ping protocol
1603 * @param USBx Selected device
1604 * @param hc_num Host Channel number
1605 * This parameter can be a value from 1 to 15
1606 * @retval HAL state
1607 */
USB_DoPing(USB_OTG_GlobalTypeDef * USBx,uint8_t ch_num)1608 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
1609 {
1610 uint32_t USBx_BASE = (uint32_t)USBx;
1611 uint32_t chnum = (uint32_t)ch_num;
1612 uint32_t num_packets = 1U;
1613 uint32_t tmpreg;
1614
1615 USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
1616 USB_OTG_HCTSIZ_DOPING;
1617
1618 /* Set host channel enable */
1619 tmpreg = USBx_HC(chnum)->HCCHAR;
1620 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1621 tmpreg |= USB_OTG_HCCHAR_CHENA;
1622 USBx_HC(chnum)->HCCHAR = tmpreg;
1623
1624 return HAL_OK;
1625 }
1626
1627 /**
1628 * @brief Stop Host Core
1629 * @param USBx Selected device
1630 * @retval HAL state
1631 */
USB_StopHost(USB_OTG_GlobalTypeDef * USBx)1632 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
1633 {
1634 uint32_t USBx_BASE = (uint32_t)USBx;
1635 uint32_t count = 0U;
1636 uint32_t value;
1637 uint32_t i;
1638
1639
1640 (void)USB_DisableGlobalInt(USBx);
1641
1642 /* Flush FIFO */
1643 (void)USB_FlushTxFifo(USBx, 0x10U);
1644 (void)USB_FlushRxFifo(USBx);
1645
1646 /* Flush out any leftover queued requests. */
1647 for (i = 0U; i <= 15U; i++)
1648 {
1649 value = USBx_HC(i)->HCCHAR;
1650 value |= USB_OTG_HCCHAR_CHDIS;
1651 value &= ~USB_OTG_HCCHAR_CHENA;
1652 value &= ~USB_OTG_HCCHAR_EPDIR;
1653 USBx_HC(i)->HCCHAR = value;
1654 }
1655
1656 /* Halt all channels to put them into a known state. */
1657 for (i = 0U; i <= 15U; i++)
1658 {
1659 value = USBx_HC(i)->HCCHAR;
1660 value |= USB_OTG_HCCHAR_CHDIS;
1661 value |= USB_OTG_HCCHAR_CHENA;
1662 value &= ~USB_OTG_HCCHAR_EPDIR;
1663 USBx_HC(i)->HCCHAR = value;
1664
1665 do
1666 {
1667 if (++count > 1000U)
1668 {
1669 break;
1670 }
1671 }
1672 while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1673 }
1674
1675 /* Clear any pending Host interrupts */
1676 USBx_HOST->HAINT = 0xFFFFFFFFU;
1677 USBx->GINTSTS = 0xFFFFFFFFU;
1678 (void)USB_EnableGlobalInt(USBx);
1679
1680 return HAL_OK;
1681 }
1682
1683 /**
1684 * @brief USB_ActivateRemoteWakeup active remote wakeup signalling
1685 * @param USBx Selected device
1686 * @retval HAL status
1687 */
USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef * USBx)1688 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
1689 {
1690 uint32_t USBx_BASE = (uint32_t)USBx;
1691
1692 if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
1693 {
1694 /* active Remote wakeup signalling */
1695 USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
1696 }
1697
1698 return HAL_OK;
1699 }
1700
1701 /**
1702 * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
1703 * @param USBx Selected device
1704 * @retval HAL status
1705 */
USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef * USBx)1706 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
1707 {
1708 uint32_t USBx_BASE = (uint32_t)USBx;
1709
1710 /* active Remote wakeup signalling */
1711 USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
1712
1713 return HAL_OK;
1714 }
1715 #endif /* defined USB_OTG_FS || defined USB_OTG_HS */
1716
1717 #if defined (USB)
1718 /**
1719 * @brief Initializes the USB Core
1720 * @param USBx: USB Instance
1721 * @param cfg : pointer to a USB_CfgTypeDef structure that contains
1722 * the configuration information for the specified USBx peripheral.
1723 * @retval HAL status
1724 */
USB_CoreInit(USB_TypeDef * USBx,USB_CfgTypeDef cfg)1725 HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
1726 {
1727 /* Prevent unused argument(s) compilation warning */
1728 UNUSED(USBx);
1729 UNUSED(cfg);
1730
1731 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
1732 only by USB OTG FS peripheral.
1733 - This function is added to ensure compatibility across platforms.
1734 */
1735
1736 return HAL_OK;
1737 }
1738
1739 /**
1740 * @brief USB_EnableGlobalInt
1741 * Enables the controller's Global Int in the AHB Config reg
1742 * @param USBx : Selected device
1743 * @retval HAL status
1744 */
USB_EnableGlobalInt(USB_TypeDef * USBx)1745 HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
1746 {
1747 uint16_t winterruptmask;
1748
1749 /* Set winterruptmask variable */
1750 winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
1751 USB_CNTR_SUSPM | USB_CNTR_ERRM |
1752 USB_CNTR_SOFM | USB_CNTR_ESOFM |
1753 USB_CNTR_RESETM | USB_CNTR_L1REQM;
1754
1755 /* Set interrupt mask */
1756 USBx->CNTR |= winterruptmask;
1757
1758 return HAL_OK;
1759 }
1760
1761 /**
1762 * @brief USB_DisableGlobalInt
1763 * Disable the controller's Global Int in the AHB Config reg
1764 * @param USBx : Selected device
1765 * @retval HAL status
1766 */
USB_DisableGlobalInt(USB_TypeDef * USBx)1767 HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
1768 {
1769 uint16_t winterruptmask;
1770
1771 /* Set winterruptmask variable */
1772 winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
1773 USB_CNTR_SUSPM | USB_CNTR_ERRM |
1774 USB_CNTR_SOFM | USB_CNTR_ESOFM |
1775 USB_CNTR_RESETM | USB_CNTR_L1REQM;
1776
1777 /* Clear interrupt mask */
1778 USBx->CNTR &= ~winterruptmask;
1779
1780 return HAL_OK;
1781 }
1782
1783 /**
1784 * @brief USB_SetCurrentMode : Set functional mode
1785 * @param USBx : Selected device
1786 * @param mode : current core mode
1787 * This parameter can be one of the these values:
1788 * @arg USB_DEVICE_MODE: Peripheral mode mode
1789 * @retval HAL status
1790 */
USB_SetCurrentMode(USB_TypeDef * USBx,USB_ModeTypeDef mode)1791 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
1792 {
1793 /* Prevent unused argument(s) compilation warning */
1794 UNUSED(USBx);
1795 UNUSED(mode);
1796
1797 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
1798 only by USB OTG FS peripheral.
1799 - This function is added to ensure compatibility across platforms.
1800 */
1801 return HAL_OK;
1802 }
1803
1804 /**
1805 * @brief USB_DevInit : Initializes the USB controller registers
1806 * for device mode
1807 * @param USBx : Selected device
1808 * @param cfg : pointer to a USB_CfgTypeDef structure that contains
1809 * the configuration information for the specified USBx peripheral.
1810 * @retval HAL status
1811 */
USB_DevInit(USB_TypeDef * USBx,USB_CfgTypeDef cfg)1812 HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
1813 {
1814 /* Prevent unused argument(s) compilation warning */
1815 UNUSED(cfg);
1816
1817 /* Init Device */
1818 /*CNTR_FRES = 1*/
1819 USBx->CNTR = USB_CNTR_FRES;
1820
1821 /*CNTR_FRES = 0*/
1822 USBx->CNTR = 0;
1823
1824 /*Clear pending interrupts*/
1825 USBx->ISTR = 0;
1826
1827 /*Set Btable Address*/
1828 USBx->BTABLE = BTABLE_ADDRESS;
1829
1830 /* Enable USB Device Interrupt mask */
1831 (void)USB_EnableGlobalInt(USBx);
1832
1833 return HAL_OK;
1834 }
1835
1836 /**
1837 * @brief USB_FlushTxFifo : Flush a Tx FIFO
1838 * @param USBx : Selected device
1839 * @param num : FIFO number
1840 * This parameter can be a value from 1 to 15
1841 15 means Flush all Tx FIFOs
1842 * @retval HAL status
1843 */
USB_FlushTxFifo(USB_TypeDef * USBx,uint32_t num)1844 HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)
1845 {
1846 /* Prevent unused argument(s) compilation warning */
1847 UNUSED(USBx);
1848 UNUSED(num);
1849
1850 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
1851 only by USB OTG FS peripheral.
1852 - This function is added to ensure compatibility across platforms.
1853 */
1854
1855 return HAL_OK;
1856 }
1857
1858 /**
1859 * @brief USB_FlushRxFifo : Flush Rx FIFO
1860 * @param USBx : Selected device
1861 * @retval HAL status
1862 */
USB_FlushRxFifo(USB_TypeDef * USBx)1863 HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
1864 {
1865 /* Prevent unused argument(s) compilation warning */
1866 UNUSED(USBx);
1867
1868 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
1869 only by USB OTG FS peripheral.
1870 - This function is added to ensure compatibility across platforms.
1871 */
1872
1873 return HAL_OK;
1874 }
1875
1876 /**
1877 * @brief Activate and configure an endpoint
1878 * @param USBx : Selected device
1879 * @param ep: pointer to endpoint structure
1880 * @retval HAL status
1881 */
USB_ActivateEndpoint(USB_TypeDef * USBx,USB_EPTypeDef * ep)1882 HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
1883 {
1884 HAL_StatusTypeDef ret = HAL_OK;
1885 uint16_t wEpRegVal;
1886
1887 wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
1888
1889 /* initialize Endpoint */
1890 switch (ep->type)
1891 {
1892 case EP_TYPE_CTRL:
1893 wEpRegVal |= USB_EP_CONTROL;
1894 break;
1895
1896 case EP_TYPE_BULK:
1897 wEpRegVal |= USB_EP_BULK;
1898 break;
1899
1900 case EP_TYPE_INTR:
1901 wEpRegVal |= USB_EP_INTERRUPT;
1902 break;
1903
1904 case EP_TYPE_ISOC:
1905 wEpRegVal |= USB_EP_ISOCHRONOUS;
1906 break;
1907
1908 default:
1909 ret = HAL_ERROR;
1910 break;
1911 }
1912
1913 PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal);
1914
1915 PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
1916
1917 if (ep->doublebuffer == 0U)
1918 {
1919 if (ep->is_in != 0U)
1920 {
1921 /*Set the endpoint Transmit buffer address */
1922 PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
1923 PCD_CLEAR_TX_DTOG(USBx, ep->num);
1924
1925 if (ep->type != EP_TYPE_ISOC)
1926 {
1927 /* Configure NAK status for the Endpoint */
1928 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
1929 }
1930 else
1931 {
1932 /* Configure TX Endpoint to disabled state */
1933 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
1934 }
1935 }
1936 else
1937 {
1938 /*Set the endpoint Receive buffer address */
1939 PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
1940 /*Set the endpoint Receive buffer counter*/
1941 PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
1942 PCD_CLEAR_RX_DTOG(USBx, ep->num);
1943 /* Configure VALID status for the Endpoint*/
1944 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
1945 }
1946 }
1947 /*Double Buffer*/
1948 else
1949 {
1950 /* Set the endpoint as double buffered */
1951 PCD_SET_EP_DBUF(USBx, ep->num);
1952 /* Set buffer address for double buffered mode */
1953 PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
1954
1955 if (ep->is_in == 0U)
1956 {
1957 /* Clear the data toggle bits for the endpoint IN/OUT */
1958 PCD_CLEAR_RX_DTOG(USBx, ep->num);
1959 PCD_CLEAR_TX_DTOG(USBx, ep->num);
1960
1961 /* Reset value of the data toggle bits for the endpoint out */
1962 PCD_TX_DTOG(USBx, ep->num);
1963
1964 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
1965 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
1966 }
1967 else
1968 {
1969 /* Clear the data toggle bits for the endpoint IN/OUT */
1970 PCD_CLEAR_RX_DTOG(USBx, ep->num);
1971 PCD_CLEAR_TX_DTOG(USBx, ep->num);
1972 PCD_RX_DTOG(USBx, ep->num);
1973
1974 if (ep->type != EP_TYPE_ISOC)
1975 {
1976 /* Configure NAK status for the Endpoint */
1977 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
1978 }
1979 else
1980 {
1981 /* Configure TX Endpoint to disabled state */
1982 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
1983 }
1984
1985 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
1986 }
1987 }
1988
1989 return ret;
1990 }
1991
1992 /**
1993 * @brief De-activate and de-initialize an endpoint
1994 * @param USBx : Selected device
1995 * @param ep: pointer to endpoint structure
1996 * @retval HAL status
1997 */
USB_DeactivateEndpoint(USB_TypeDef * USBx,USB_EPTypeDef * ep)1998 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
1999 {
2000 if (ep->doublebuffer == 0U)
2001 {
2002 if (ep->is_in != 0U)
2003 {
2004 PCD_CLEAR_TX_DTOG(USBx, ep->num);
2005 /* Configure DISABLE status for the Endpoint*/
2006 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
2007 }
2008 else
2009 {
2010 PCD_CLEAR_RX_DTOG(USBx, ep->num);
2011 /* Configure DISABLE status for the Endpoint*/
2012 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
2013 }
2014 }
2015 /*Double Buffer*/
2016 else
2017 {
2018 if (ep->is_in == 0U)
2019 {
2020 /* Clear the data toggle bits for the endpoint IN/OUT*/
2021 PCD_CLEAR_RX_DTOG(USBx, ep->num);
2022 PCD_CLEAR_TX_DTOG(USBx, ep->num);
2023
2024 /* Reset value of the data toggle bits for the endpoint out*/
2025 PCD_TX_DTOG(USBx, ep->num);
2026
2027 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
2028 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
2029 }
2030 else
2031 {
2032 /* Clear the data toggle bits for the endpoint IN/OUT*/
2033 PCD_CLEAR_RX_DTOG(USBx, ep->num);
2034 PCD_CLEAR_TX_DTOG(USBx, ep->num);
2035 PCD_RX_DTOG(USBx, ep->num);
2036 /* Configure DISABLE status for the Endpoint*/
2037 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
2038 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
2039 }
2040 }
2041
2042 return HAL_OK;
2043 }
2044
2045 /**
2046 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
2047 * @param USBx : Selected device
2048 * @param ep: pointer to endpoint structure
2049 * @retval HAL status
2050 */
USB_EPStartXfer(USB_TypeDef * USBx,USB_EPTypeDef * ep)2051 HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
2052 {
2053 uint16_t pmabuffer;
2054 uint32_t len = ep->xfer_len;
2055
2056 /* IN endpoint */
2057 if (ep->is_in == 1U)
2058 {
2059 /*Multi packet transfer*/
2060 if (ep->xfer_len > ep->maxpacket)
2061 {
2062 len = ep->maxpacket;
2063 ep->xfer_len -= len;
2064 }
2065 else
2066 {
2067 len = ep->xfer_len;
2068 ep->xfer_len = 0U;
2069 }
2070
2071 /* configure and validate Tx endpoint */
2072 if (ep->doublebuffer == 0U)
2073 {
2074 USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
2075 PCD_SET_EP_TX_CNT(USBx, ep->num, len);
2076 }
2077 else
2078 {
2079 /* Write the data to the USB endpoint */
2080 if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
2081 {
2082 /* Set the Double buffer counter for pmabuffer1 */
2083 PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
2084 pmabuffer = ep->pmaaddr1;
2085 }
2086 else
2087 {
2088 /* Set the Double buffer counter for pmabuffer0 */
2089 PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
2090 pmabuffer = ep->pmaaddr0;
2091 }
2092 USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
2093 PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
2094 }
2095
2096 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
2097 }
2098 else /* OUT endpoint */
2099 {
2100 /* Multi packet transfer*/
2101 if (ep->xfer_len > ep->maxpacket)
2102 {
2103 len = ep->maxpacket;
2104 ep->xfer_len -= len;
2105 }
2106 else
2107 {
2108 len = ep->xfer_len;
2109 ep->xfer_len = 0U;
2110 }
2111
2112 /* configure and validate Rx endpoint */
2113 if (ep->doublebuffer == 0U)
2114 {
2115 /*Set RX buffer count*/
2116 PCD_SET_EP_RX_CNT(USBx, ep->num, len);
2117 }
2118 else
2119 {
2120 /*Set the Double buffer counter*/
2121 PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
2122 }
2123
2124 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
2125 }
2126
2127 return HAL_OK;
2128 }
2129
2130 /**
2131 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
2132 * with the EP/channel
2133 * @param USBx : Selected device
2134 * @param src : pointer to source buffer
2135 * @param ch_ep_num : endpoint or host channel number
2136 * @param len : Number of bytes to write
2137 * @retval HAL status
2138 */
USB_WritePacket(USB_TypeDef * USBx,uint8_t * src,uint8_t ch_ep_num,uint16_t len)2139 HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
2140 {
2141 /* Prevent unused argument(s) compilation warning */
2142 UNUSED(USBx);
2143 UNUSED(src);
2144 UNUSED(ch_ep_num);
2145 UNUSED(len);
2146 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2147 only by USB OTG FS peripheral.
2148 - This function is added to ensure compatibility across platforms.
2149 */
2150 return HAL_OK;
2151 }
2152
2153 /**
2154 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
2155 * with the EP/channel
2156 * @param USBx : Selected device
2157 * @param dest : destination pointer
2158 * @param len : Number of bytes to read
2159 * @retval pointer to destination buffer
2160 */
USB_ReadPacket(USB_TypeDef * USBx,uint8_t * dest,uint16_t len)2161 void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
2162 {
2163 /* Prevent unused argument(s) compilation warning */
2164 UNUSED(USBx);
2165 UNUSED(dest);
2166 UNUSED(len);
2167 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2168 only by USB OTG FS peripheral.
2169 - This function is added to ensure compatibility across platforms.
2170 */
2171 return ((void *)NULL);
2172 }
2173
2174 /**
2175 * @brief USB_EPSetStall : set a stall condition over an EP
2176 * @param USBx : Selected device
2177 * @param ep: pointer to endpoint structure
2178 * @retval HAL status
2179 */
USB_EPSetStall(USB_TypeDef * USBx,USB_EPTypeDef * ep)2180 HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
2181 {
2182 if (ep->is_in != 0U)
2183 {
2184 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
2185 }
2186 else
2187 {
2188 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
2189 }
2190
2191 return HAL_OK;
2192 }
2193
2194 /**
2195 * @brief USB_EPClearStall : Clear a stall condition over an EP
2196 * @param USBx : Selected device
2197 * @param ep: pointer to endpoint structure
2198 * @retval HAL status
2199 */
USB_EPClearStall(USB_TypeDef * USBx,USB_EPTypeDef * ep)2200 HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
2201 {
2202 if (ep->is_in != 0U)
2203 {
2204 PCD_CLEAR_TX_DTOG(USBx, ep->num);
2205 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
2206 }
2207 else
2208 {
2209 PCD_CLEAR_RX_DTOG(USBx, ep->num);
2210 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
2211 }
2212 return HAL_OK;
2213 }
2214
2215 /**
2216 * @brief USB_StopDevice : Stop the usb device mode
2217 * @param USBx : Selected device
2218 * @retval HAL status
2219 */
USB_StopDevice(USB_TypeDef * USBx)2220 HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
2221 {
2222 /* disable all interrupts and force USB reset */
2223 USBx->CNTR = USB_CNTR_FRES;
2224
2225 /* clear interrupt status register */
2226 USBx->ISTR = 0;
2227
2228 /* switch-off device */
2229 USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
2230
2231 return HAL_OK;
2232 }
2233
2234 /**
2235 * @brief USB_SetDevAddress : Stop the usb device mode
2236 * @param USBx : Selected device
2237 * @param address : new device address to be assigned
2238 * This parameter can be a value from 0 to 255
2239 * @retval HAL status
2240 */
USB_SetDevAddress(USB_TypeDef * USBx,uint8_t address)2241 HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
2242 {
2243 if (address == 0U)
2244 {
2245 /* set device address and enable function */
2246 USBx->DADDR = USB_DADDR_EF;
2247 }
2248
2249 return HAL_OK;
2250 }
2251
2252 /**
2253 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
2254 * @param USBx : Selected device
2255 * @retval HAL status
2256 */
USB_DevConnect(USB_TypeDef * USBx)2257 HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
2258 {
2259 /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
2260 USBx->BCDR |= USB_BCDR_DPPU;
2261
2262 return HAL_OK;
2263 }
2264
2265 /**
2266 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
2267 * @param USBx : Selected device
2268 * @retval HAL status
2269 */
USB_DevDisconnect(USB_TypeDef * USBx)2270 HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
2271 {
2272 /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
2273 USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
2274
2275 return HAL_OK;
2276 }
2277
2278 /**
2279 * @brief USB_ReadInterrupts: return the global USB interrupt status
2280 * @param USBx : Selected device
2281 * @retval HAL status
2282 */
USB_ReadInterrupts(USB_TypeDef * USBx)2283 uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
2284 {
2285 uint32_t tmpreg;
2286
2287 tmpreg = USBx->ISTR;
2288 return tmpreg;
2289 }
2290
2291 /**
2292 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
2293 * @param USBx : Selected device
2294 * @retval HAL status
2295 */
USB_ReadDevAllOutEpInterrupt(USB_TypeDef * USBx)2296 uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
2297 {
2298 /* Prevent unused argument(s) compilation warning */
2299 UNUSED(USBx);
2300 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2301 only by USB OTG FS peripheral.
2302 - This function is added to ensure compatibility across platforms.
2303 */
2304 return (0);
2305 }
2306
2307 /**
2308 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
2309 * @param USBx : Selected device
2310 * @retval HAL status
2311 */
USB_ReadDevAllInEpInterrupt(USB_TypeDef * USBx)2312 uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
2313 {
2314 /* Prevent unused argument(s) compilation warning */
2315 UNUSED(USBx);
2316 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2317 only by USB OTG FS peripheral.
2318 - This function is added to ensure compatibility across platforms.
2319 */
2320 return (0);
2321 }
2322
2323 /**
2324 * @brief Returns Device OUT EP Interrupt register
2325 * @param USBx : Selected device
2326 * @param epnum : endpoint number
2327 * This parameter can be a value from 0 to 15
2328 * @retval Device OUT EP Interrupt register
2329 */
USB_ReadDevOutEPInterrupt(USB_TypeDef * USBx,uint8_t epnum)2330 uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
2331 {
2332 /* Prevent unused argument(s) compilation warning */
2333 UNUSED(USBx);
2334 UNUSED(epnum);
2335 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2336 only by USB OTG FS peripheral.
2337 - This function is added to ensure compatibility across platforms.
2338 */
2339 return (0);
2340 }
2341
2342 /**
2343 * @brief Returns Device IN EP Interrupt register
2344 * @param USBx : Selected device
2345 * @param epnum : endpoint number
2346 * This parameter can be a value from 0 to 15
2347 * @retval Device IN EP Interrupt register
2348 */
USB_ReadDevInEPInterrupt(USB_TypeDef * USBx,uint8_t epnum)2349 uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
2350 {
2351 /* Prevent unused argument(s) compilation warning */
2352 UNUSED(USBx);
2353 UNUSED(epnum);
2354 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2355 only by USB OTG FS peripheral.
2356 - This function is added to ensure compatibility across platforms.
2357 */
2358 return (0);
2359 }
2360
2361 /**
2362 * @brief USB_ClearInterrupts: clear a USB interrupt
2363 * @param USBx Selected device
2364 * @param interrupt interrupt flag
2365 * @retval None
2366 */
USB_ClearInterrupts(USB_TypeDef * USBx,uint32_t interrupt)2367 void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
2368 {
2369 /* Prevent unused argument(s) compilation warning */
2370 UNUSED(USBx);
2371 UNUSED(interrupt);
2372 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2373 only by USB OTG FS peripheral.
2374 - This function is added to ensure compatibility across platforms.
2375 */
2376 }
2377
2378 /**
2379 * @brief Prepare the EP0 to start the first control setup
2380 * @param USBx Selected device
2381 * @param psetup pointer to setup packet
2382 * @retval HAL status
2383 */
USB_EP0_OutStart(USB_TypeDef * USBx,uint8_t * psetup)2384 HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
2385 {
2386 /* Prevent unused argument(s) compilation warning */
2387 UNUSED(USBx);
2388 UNUSED(psetup);
2389 /* NOTE : - This function is not required by USB Device FS peripheral, it is used
2390 only by USB OTG FS peripheral.
2391 - This function is added to ensure compatibility across platforms.
2392 */
2393 return HAL_OK;
2394 }
2395
2396 /**
2397 * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
2398 * @param USBx Selected device
2399 * @retval HAL status
2400 */
USB_ActivateRemoteWakeup(USB_TypeDef * USBx)2401 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
2402 {
2403 USBx->CNTR |= USB_CNTR_RESUME;
2404
2405 return HAL_OK;
2406 }
2407
2408 /**
2409 * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
2410 * @param USBx Selected device
2411 * @retval HAL status
2412 */
USB_DeActivateRemoteWakeup(USB_TypeDef * USBx)2413 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
2414 {
2415 USBx->CNTR &= ~(USB_CNTR_RESUME);
2416 return HAL_OK;
2417 }
2418
2419 /**
2420 * @brief Copy a buffer from user memory area to packet memory area (PMA)
2421 * @param USBx USB peripheral instance register address.
2422 * @param pbUsrBuf pointer to user memory area.
2423 * @param wPMABufAddr address into PMA.
2424 * @param wNBytes: no. of bytes to be copied.
2425 * @retval None
2426 */
USB_WritePMA(USB_TypeDef * USBx,uint8_t * pbUsrBuf,uint16_t wPMABufAddr,uint16_t wNBytes)2427 void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
2428 {
2429 uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
2430 uint32_t BaseAddr = (uint32_t)USBx;
2431 uint32_t i, temp1, temp2;
2432 uint16_t *pdwVal;
2433 uint8_t *pBuf = pbUsrBuf;
2434
2435 pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
2436
2437 for (i = n; i != 0U; i--)
2438 {
2439 temp1 = (uint16_t) * pBuf;
2440 pBuf++;
2441 temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8));
2442 *pdwVal = (uint16_t)temp2;
2443 pdwVal++;
2444
2445 if (PMA_ACCESS > 1U)
2446 {
2447 pdwVal++;
2448 }
2449 pBuf++;
2450 }
2451 }
2452
2453 /**
2454 * @brief Copy a buffer from user memory area to packet memory area (PMA)
2455 * @param USBx: USB peripheral instance register address.
2456 * @param pbUsrBuf pointer to user memory area.
2457 * @param wPMABufAddr address into PMA.
2458 * @param wNBytes: no. of bytes to be copied.
2459 * @retval None
2460 */
USB_ReadPMA(USB_TypeDef * USBx,uint8_t * pbUsrBuf,uint16_t wPMABufAddr,uint16_t wNBytes)2461 void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
2462 {
2463 uint32_t n = (uint32_t)wNBytes >> 1;
2464 uint32_t BaseAddr = (uint32_t)USBx;
2465 uint32_t i, temp;
2466 uint16_t *pdwVal;
2467 uint8_t *pBuf = pbUsrBuf;
2468
2469 pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
2470
2471 for (i = n; i != 0U; i--)
2472 {
2473 temp = *pdwVal;
2474 pdwVal++;
2475 *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
2476 pBuf++;
2477 *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
2478 pBuf++;
2479
2480 if (PMA_ACCESS > 1U)
2481 {
2482 pdwVal++;
2483 }
2484 }
2485
2486 if ((wNBytes % 2U) != 0U)
2487 {
2488 temp = *pdwVal;
2489 pdwVal++;
2490 *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
2491 pBuf++;
2492 }
2493 }
2494 #endif /* USB */
2495
2496 /**
2497 * @}
2498 */
2499
2500 /**
2501 * @}
2502 */
2503
2504 #endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */
2505
2506 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
2507
2508 /**
2509 * @}
2510 */
2511
2512 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2513
