1 /* 2 * Copyright (c) 2016 Intel Corporation 3 * Copyright (c) 2023 Nordic Semiconductor ASA 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_USB_COMMON_USB_DWC2_HW 9 #define ZEPHYR_DRIVERS_USB_COMMON_USB_DWC2_HW 10 11 #include <stdint.h> 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /* This file describes register set for the DesignWare USB 2.0 controller IP */ 18 19 /* IN endpoint register block */ 20 struct usb_dwc2_in_ep { 21 volatile uint32_t diepctl; 22 uint32_t reserved; 23 volatile uint32_t diepint; 24 uint32_t reserved1; 25 volatile uint32_t dieptsiz; 26 volatile uint32_t diepdma; 27 volatile uint32_t dtxfsts; 28 volatile uint32_t diepdmab; 29 }; 30 31 /* OUT endpoint register block */ 32 struct usb_dwc2_out_ep { 33 volatile uint32_t doepctl; 34 uint32_t reserved; 35 volatile uint32_t doepint; 36 uint32_t reserved1; 37 volatile uint32_t doeptsiz; 38 volatile uint32_t doepdma; 39 uint32_t reserved2; 40 volatile uint32_t doepdmab; 41 }; 42 43 /* DWC2 register map 44 * TODO: This should probably be split into global, host, and device register 45 * blocks 46 */ 47 struct usb_dwc2_reg { 48 volatile uint32_t gotgctl; 49 volatile uint32_t gotgint; 50 volatile uint32_t gahbcfg; 51 volatile uint32_t gusbcfg; 52 volatile uint32_t grstctl; 53 volatile uint32_t gintsts; 54 volatile uint32_t gintmsk; 55 volatile uint32_t grxstsr; 56 volatile uint32_t grxstsp; 57 volatile uint32_t grxfsiz; 58 volatile uint32_t gnptxfsiz; 59 volatile uint32_t gnptxsts; 60 volatile uint32_t gi2cctl; 61 volatile uint32_t gpvndctl; 62 volatile uint32_t ggpio; 63 volatile uint32_t guid; 64 volatile uint32_t gsnpsid; 65 volatile uint32_t ghwcfg1; 66 volatile uint32_t ghwcfg2; 67 volatile uint32_t ghwcfg3; 68 volatile uint32_t ghwcfg4; 69 volatile uint32_t glpmcfg; 70 volatile uint32_t gpwrdn; 71 volatile uint32_t gdfifocfg; 72 volatile uint32_t gadpctl; 73 volatile uint32_t grefclk; 74 volatile uint32_t gintmsk2; 75 volatile uint32_t gintsts2; 76 volatile uint32_t reserved1[36]; 77 volatile uint32_t hptxfsiz; 78 union { 79 volatile uint32_t dptxfsiz[15]; 80 volatile uint32_t dieptxf[15]; 81 }; 82 volatile uint32_t reserved2[176]; 83 /* Host mode register 0x0400 .. 0x0670 */ 84 uint32_t reserved3[256]; 85 /* Device mode register 0x0800 .. 0x0D00 */ 86 volatile uint32_t dcfg; 87 volatile uint32_t dctl; 88 volatile uint32_t dsts; 89 uint32_t reserved4; 90 volatile uint32_t diepmsk; 91 volatile uint32_t doepmsk; 92 volatile uint32_t daint; 93 volatile uint32_t daintmsk; 94 volatile uint32_t dtknqr1; 95 volatile uint32_t dtknqr2; 96 volatile uint32_t dvbusdis; 97 volatile uint32_t dvbuspulse; 98 union { 99 volatile uint32_t dtknqr3; 100 volatile uint32_t dthrctl; 101 }; 102 union { 103 volatile uint32_t dtknqr4; 104 volatile uint32_t diepempmsk; 105 }; 106 volatile uint32_t deachint; 107 volatile uint32_t deachintmsk; 108 volatile uint32_t diepeachmsk[16]; 109 volatile uint32_t doepeachmsk[16]; 110 volatile uint32_t reserved5[16]; 111 struct usb_dwc2_in_ep in_ep[16]; 112 struct usb_dwc2_out_ep out_ep[16]; 113 }; 114 115 /* 116 * With the maximum number of supported endpoints, register map 117 * of the controller must be equal to 0x0D00. 118 */ 119 BUILD_ASSERT(sizeof(struct usb_dwc2_reg) == 0x0D00); 120 121 /* 122 * GET_FIELD/SET_FIELD macros below are intended to be used to define functions 123 * to get/set a bitfield of a register from/into a value. They should not be 124 * used to get/set a bitfield consisting of only one bit. 125 */ 126 #define USB_DWC2_GET_FIELD_DEFINE(name, reg_name_and_field) \ 127 static inline uint32_t usb_dwc2_get_##name(const uint32_t value) \ 128 { \ 129 return (value & USB_DWC2_##reg_name_and_field##_MASK) >> \ 130 USB_DWC2_##reg_name_and_field##_POS; \ 131 } 132 133 #define USB_DWC2_SET_FIELD_DEFINE(name, reg_name_and_field) \ 134 static inline uint32_t usb_dwc2_set_##name(const uint32_t value) \ 135 { \ 136 return (value << USB_DWC2_##reg_name_and_field##_POS) & \ 137 USB_DWC2_##reg_name_and_field##_MASK; \ 138 } 139 140 #define USB_DWC2_GET_FIELD_AND_IDX_DEFINE(name, reg_name_and_field) \ 141 static inline uint32_t usb_dwc2_get_##name(const uint32_t value, \ 142 const uint32_t idx) \ 143 { \ 144 return (value & USB_DWC2_##reg_name_and_field##_MASK(idx)) >> \ 145 USB_DWC2_##reg_name_and_field##_POS(idx); \ 146 } 147 148 /* AHB configuration register */ 149 #define USB_DWC2_GAHBCFG 0x0008UL 150 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_POS 27UL 151 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_MASK (0x3UL << USB_DWC2_GAHBCFG_LOA_EOP_WORD_POS) 152 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_ONE 1 153 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_TWO 2 154 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_POS 25UL 155 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_MASK (0x3UL << USB_DWC2_GAHBCFG_LOA_EOP_BYTE_POS) 156 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_ONE 1 157 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_TWO 2 158 #define USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS 24UL 159 #define USB_DWC2_GAHBCFG_INVDESCENDIANESS BIT(USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS) 160 #define USB_DWC2_GAHBCFG_AHBSINGLE_POS 23UL 161 #define USB_DWC2_GAHBCFG_AHBSINGLE BIT(USB_DWC2_GAHBCFG_AHBSINGLE_POS) 162 #define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS 22UL 163 #define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT BIT(USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS) 164 #define USB_DWC2_GAHBCFG_REMMEMSUPP_POS 21UL 165 #define USB_DWC2_GAHBCFG_REMMEMSUPP BIT(USB_DWC2_GAHBCFG_REMMEMSUPP_POS) 166 #define USB_DWC2_GAHBCFG_PTXFEMPLVL_POS 8UL 167 #define USB_DWC2_GAHBCFG_PTXFEMPLVL BIT(USB_DWC2_GAHBCFG_PTXFEMPLVL_POS) 168 #define USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS 7UL 169 #define USB_DWC2_GAHBCFG_NPTXFEMPLVL BIT(USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS) 170 #define USB_DWC2_GAHBCFG_DMAEN_POS 5UL 171 #define USB_DWC2_GAHBCFG_DMAEN BIT(USB_DWC2_GAHBCFG_DMAEN_POS) 172 #define USB_DWC2_GAHBCFG_HBSTLEN_POS 1UL 173 #define USB_DWC2_GAHBCFG_HBSTLEN_MASK (0xFUL << USB_DWC2_GAHBCFG_HBSTLEN_POS) 174 #define USB_DWC2_GAHBCFG_HBSTLEN_SINGLE 0 175 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR 1 176 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR4 3 177 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR8 5 178 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR16 7 179 #define USB_DWC2_GAHBCFG_GLBINTRMASK_POS 0UL 180 #define USB_DWC2_GAHBCFG_GLBINTRMASK BIT(USB_DWC2_GAHBCFG_GLBINTRMASK_POS) 181 182 USB_DWC2_SET_FIELD_DEFINE(gahbcfg_loa_eop_word, GAHBCFG_LOA_EOP_WORD) 183 USB_DWC2_SET_FIELD_DEFINE(gahbcfg_loa_eop_byte, GAHBCFG_LOA_EOP_BYTE) 184 USB_DWC2_SET_FIELD_DEFINE(gahbcfg_hbstlen, GAHBCFG_HBSTLEN) 185 USB_DWC2_GET_FIELD_DEFINE(gahbcfg_loa_eop_word, GAHBCFG_LOA_EOP_WORD) 186 USB_DWC2_GET_FIELD_DEFINE(gahbcfg_loa_eop_byte, GAHBCFG_LOA_EOP_BYTE) 187 USB_DWC2_GET_FIELD_DEFINE(gahbcfg_hbstlen, GAHBCFG_HBSTLEN) 188 189 /* USB configuration register */ 190 #define USB_DWC2_GUSBCFG 0x000CUL 191 #define USB_DWC2_GUSBCFG_FORCEDEVMODE_POS 30UL 192 #define USB_DWC2_GUSBCFG_FORCEDEVMODE BIT(USB_DWC2_GUSBCFG_FORCEDEVMODE_POS) 193 #define USB_DWC2_GUSBCFG_FORCEHSTMODE_POS 29UL 194 #define USB_DWC2_GUSBCFG_FORCEHSTMODE BIT(USB_DWC2_GUSBCFG_FORCEHSTMODE_POS) 195 #define USB_DWC2_GUSBCFG_PHYSEL_POS 6UL 196 #define USB_DWC2_GUSBCFG_PHYSEL_USB11 BIT(USB_DWC2_GUSBCFG_PHYSEL_POS) 197 #define USB_DWC2_GUSBCFG_PHYSEL_USB20 0UL 198 #define USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_POS 4UL 199 #define USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_ULPI BIT(USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_POS) 200 #define USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_UTMI 0UL 201 #define USB_DWC2_GUSBCFG_PHYIF_POS 3UL 202 #define USB_DWC2_GUSBCFG_PHYIF_16_BIT BIT(USB_DWC2_GUSBCFG_PHYIF_POS) 203 #define USB_DWC2_GUSBCFG_PHYIF_8_BIT 0UL 204 205 /* Reset register */ 206 #define USB_DWC2_GRSTCTL 0x0010UL 207 #define USB_DWC2_GRSTCTL_AHBIDLE_POS 31UL 208 #define USB_DWC2_GRSTCTL_AHBIDLE BIT(USB_DWC2_GRSTCTL_AHBIDLE_POS) 209 #define USB_DWC2_GRSTCTL_CSFTRSTDONE_POS 29UL 210 #define USB_DWC2_GRSTCTL_CSFTRSTDONE BIT(USB_DWC2_GRSTCTL_CSFTRSTDONE_POS) 211 #define USB_DWC2_GRSTCTL_TXFNUM_POS 6UL 212 #define USB_DWC2_GRSTCTL_TXFNUM_MASK (0x1FUL << USB_DWC2_GRSTCTL_TXFNUM_POS) 213 #define USB_DWC2_GRSTCTL_TXFFLSH_POS 5UL 214 #define USB_DWC2_GRSTCTL_TXFFLSH BIT(USB_DWC2_GRSTCTL_TXFFLSH_POS) 215 #define USB_DWC2_GRSTCTL_RXFFLSH_POS 4UL 216 #define USB_DWC2_GRSTCTL_RXFFLSH BIT(USB_DWC2_GRSTCTL_RXFFLSH_POS) 217 #define USB_DWC2_GRSTCTL_CSFTRST_POS 0UL 218 #define USB_DWC2_GRSTCTL_CSFTRST BIT(USB_DWC2_GRSTCTL_CSFTRST_POS) 219 220 USB_DWC2_SET_FIELD_DEFINE(grstctl_txfnum, GRSTCTL_TXFNUM) 221 222 /* Core interrupt registers */ 223 #define USB_DWC2_GINTSTS 0x0014UL 224 #define USB_DWC2_GINTMSK 0x0018UL 225 #define USB_DWC2_GINTSTS_WKUPINT_POS 31UL 226 #define USB_DWC2_GINTSTS_WKUPINT BIT(USB_DWC2_GINTSTS_WKUPINT_POS) 227 #define USB_DWC2_GINTSTS_SESSREQINT_POS 30UL 228 #define USB_DWC2_GINTSTS_SESSREQINT BIT(USB_DWC2_GINTSTS_SESSREQINT_POS) 229 #define USB_DWC2_GINTSTS_DISCONNINT_POS 29UL 230 #define USB_DWC2_GINTSTS_DISCONNINT BIT(USB_DWC2_GINTSTS_DISCONNINT_POS) 231 #define USB_DWC2_GINTSTS_CONIDSTSCHNG_POS 28UL 232 #define USB_DWC2_GINTSTS_CONIDSTSCHNG BIT(USB_DWC2_GINTSTS_CONIDSTSCHNG_POS) 233 #define USB_DWC2_GINTSTS_LPM_INT_POS 27UL 234 #define USB_DWC2_GINTSTS_LPM_INT BIT(USB_DWC2_GINTSTS_LPM_INT_POS) 235 #define USB_DWC2_GINTSTS_HCHINT_POS 25UL 236 #define USB_DWC2_GINTSTS_HCHINT BIT(USB_DWC2_GINTSTS_HCHINT_POS) 237 #define USB_DWC2_GINTSTS_PRTINT_POS 24UL 238 #define USB_DWC2_GINTSTS_PRTINT BIT(USB_DWC2_GINTSTS_PRTINT_POS) 239 #define USB_DWC2_GINTSTS_RESETDET_POS 23UL 240 #define USB_DWC2_GINTSTS_RESETDET BIT(USB_DWC2_GINTSTS_RESETDET_POS) 241 #define USB_DWC2_GINTSTS_FETSUSP_POS 22UL 242 #define USB_DWC2_GINTSTS_FETSUSP BIT(USB_DWC2_GINTSTS_FETSUSP_POS) 243 #define USB_DWC2_GINTSTS_INCOMPIP_POS 21UL 244 #define USB_DWC2_GINTSTS_INCOMPIP BIT(USB_DWC2_GINTSTS_INCOMPIP_POS) 245 #define USB_DWC2_GINTSTS_INCOMPISOIN_POS 20UL 246 #define USB_DWC2_GINTSTS_INCOMPISOIN BIT(USB_DWC2_GINTSTS_INCOMPISOIN_POS) 247 #define USB_DWC2_GINTSTS_OEPINT_POS 19UL 248 #define USB_DWC2_GINTSTS_OEPINT BIT(USB_DWC2_GINTSTS_OEPINT_POS) 249 #define USB_DWC2_GINTSTS_IEPINT_POS 18UL 250 #define USB_DWC2_GINTSTS_IEPINT BIT(USB_DWC2_GINTSTS_IEPINT_POS) 251 #define USB_DWC2_GINTSTS_EPMIS_POS 17UL 252 #define USB_DWC2_GINTSTS_EPMIS BIT(USB_DWC2_GINTSTS_EPMIS_POS) 253 #define USB_DWC2_GINTSTS_RSTRDONEINT_POS 16UL 254 #define USB_DWC2_GINTSTS_RSTRDONEINT BIT(USB_DWC2_GINTSTS_RSTRDONEINT_POS) 255 #define USB_DWC2_GINTSTS_EOPF_POS 15UL 256 #define USB_DWC2_GINTSTS_EOPF BIT(USB_DWC2_GINTSTS_EOPF_POS) 257 #define USB_DWC2_GINTSTS_ISOOUTDROP_POS 14UL 258 #define USB_DWC2_GINTSTS_ISOOUTDROP BIT(USB_DWC2_GINTSTS_ISOOUTDROP_POS) 259 #define USB_DWC2_GINTSTS_ENUMDONE_POS 13UL 260 #define USB_DWC2_GINTSTS_ENUMDONE BIT(USB_DWC2_GINTSTS_ENUMDONE_POS) 261 #define USB_DWC2_GINTSTS_USBRST_POS 12UL 262 #define USB_DWC2_GINTSTS_USBRST BIT(USB_DWC2_GINTSTS_USBRST_POS) 263 #define USB_DWC2_GINTSTS_USBSUSP_POS 11UL 264 #define USB_DWC2_GINTSTS_USBSUSP BIT(USB_DWC2_GINTSTS_USBSUSP_POS) 265 #define USB_DWC2_GINTSTS_ERLYSUSP_POS 10UL 266 #define USB_DWC2_GINTSTS_ERLYSUSP BIT(USB_DWC2_GINTSTS_ERLYSUSP_POS) 267 #define USB_DWC2_GINTSTS_GOUTNAKEFF_POS 7UL 268 #define USB_DWC2_GINTSTS_GOUTNAKEFF BIT(USB_DWC2_GINTSTS_GOUTNAKEFF_POS) 269 #define USB_DWC2_GINTSTS_GINNAKEFF_POS 6UL 270 #define USB_DWC2_GINTSTS_GINNAKEFF BIT(USB_DWC2_GINTSTS_GINNAKEFF_POS) 271 #define USB_DWC2_GINTSTS_NPTXFEMP_POS 5UL 272 #define USB_DWC2_GINTSTS_NPTXFEMP BIT(USB_DWC2_GINTSTS_NPTXFEMP_POS) 273 #define USB_DWC2_GINTSTS_RXFLVL_POS 4UL 274 #define USB_DWC2_GINTSTS_RXFLVL BIT(USB_DWC2_GINTSTS_RXFLVL_POS) 275 #define USB_DWC2_GINTSTS_SOF_POS 3UL 276 #define USB_DWC2_GINTSTS_SOF BIT(USB_DWC2_GINTSTS_SOF_POS) 277 #define USB_DWC2_GINTSTS_OTGINT_POS 2UL 278 #define USB_DWC2_GINTSTS_OTGINT BIT(USB_DWC2_GINTSTS_OTGINT_POS) 279 #define USB_DWC2_GINTSTS_MODEMIS_POS 1UL 280 #define USB_DWC2_GINTSTS_MODEMIS BIT(USB_DWC2_GINTSTS_MODEMIS_POS) 281 #define USB_DWC2_GINTSTS_CURMOD_POS 0UL 282 #define USB_DWC2_GINTSTS_CURMOD BIT(USB_DWC2_GINTSTS_CURMOD_POS) 283 284 /* Status read and pop registers */ 285 #define USB_DWC2_GRXSTSR 0x001CUL 286 #define USB_DWC2_GRXSTSP 0x0020UL 287 #define USB_DWC2_GRXSTSR_FN_POS 21UL 288 #define USB_DWC2_GRXSTSR_FN_MASK (0xFUL << USB_DWC2_GRXSTSR_FN_POS) 289 #define USB_DWC2_GRXSTSR_PKTSTS_POS 17UL 290 #define USB_DWC2_GRXSTSR_PKTSTS_MASK (0xFUL << USB_DWC2_GRXSTSR_PKTSTS_POS) 291 #define USB_DWC2_GRXSTSR_PKTSTS_GLOBAL_OUT_NAK 1 292 #define USB_DWC2_GRXSTSR_PKTSTS_OUT_DATA 2 293 #define USB_DWC2_GRXSTSR_PKTSTS_OUT_DATA_DONE 3 294 #define USB_DWC2_GRXSTSR_PKTSTS_SETUP_DONE 4 295 #define USB_DWC2_GRXSTSR_PKTSTS_SETUP 6 296 #define USB_DWC2_GRXSTSR_DPID_POS 15UL 297 #define USB_DWC2_GRXSTSR_DPID_MASK (0x3UL << USB_DWC2_GRXSTSR_DPID_POS) 298 #define USB_DWC2_GRXSTSR_DPID_DATA0 0 299 #define USB_DWC2_GRXSTSR_DPID_DATA2 1 300 #define USB_DWC2_GRXSTSR_DPID_DATA1 2 301 #define USB_DWC2_GRXSTSR_DPID_MDATA 3 302 #define USB_DWC2_GRXSTSR_BCNT_POS 4UL 303 #define USB_DWC2_GRXSTSR_BCNT_MASK (0x000007FFUL << USB_DWC2_GRXSTSR_BCNT_POS) 304 #define USB_DWC2_GRXSTSR_EPNUM_POS 0UL 305 #define USB_DWC2_GRXSTSR_EPNUM_MASK 0x0000000FUL 306 #define USB_DWC2_GRXSTSR_CHNUM_POS 0UL 307 #define USB_DWC2_GRXSTSR_CHNUM_MASK 0x0000000FUL 308 309 USB_DWC2_GET_FIELD_DEFINE(grxstsp_fn, GRXSTSR_FN) 310 USB_DWC2_GET_FIELD_DEFINE(grxstsp_pktsts, GRXSTSR_PKTSTS) 311 USB_DWC2_GET_FIELD_DEFINE(grxstsp_bcnt, GRXSTSR_BCNT) 312 USB_DWC2_GET_FIELD_DEFINE(grxstsp_epnum, GRXSTSR_EPNUM) 313 314 /* Receive FIFO size register (device mode) */ 315 #define USB_DWC2_GRXFSIZ 0x0024UL 316 #define USB_DWC2_GRXFSIZ_RXFDEP_POS 0UL 317 #define USB_DWC2_GRXFSIZ_RXFDEP_MASK (0xFFFFUL << USB_DWC2_GRXFSIZ_RXFDEP_POS) 318 319 USB_DWC2_GET_FIELD_DEFINE(grxfsiz, GRXFSIZ_RXFDEP) 320 USB_DWC2_SET_FIELD_DEFINE(grxfsiz, GRXFSIZ_RXFDEP) 321 322 /* Non-periodic transmit FIFO size register (device mode) */ 323 #define USB_DWC2_GNPTXFSIZ 0x0028UL 324 #define USB_DWC2_GNPTXFSIZ_NPTXFDEP_POS 16UL 325 #define USB_DWC2_GNPTXFSIZ_NPTXFDEP_MASK (0xFFFFUL << USB_DWC2_GNPTXFSIZ_NPTXFDEP_POS) 326 #define USB_DWC2_GNPTXFSIZ_NPTXFSTADDR_POS 0UL 327 #define USB_DWC2_GNPTXFSIZ_NPTXFSTADDR_MASK (0xFFFFUL << USB_DWC2_GNPTXFSIZ_NPTXFSTADDR_POS) 328 329 USB_DWC2_GET_FIELD_DEFINE(gnptxfsiz_nptxfdep, GNPTXFSIZ_NPTXFDEP) 330 USB_DWC2_GET_FIELD_DEFINE(gnptxfsiz_nptxfstaddr, GNPTXFSIZ_NPTXFSTADDR) 331 USB_DWC2_SET_FIELD_DEFINE(gnptxfsiz_nptxfdep, GNPTXFSIZ_NPTXFDEP) 332 USB_DWC2_SET_FIELD_DEFINE(gnptxfsiz_nptxfstaddr, GNPTXFSIZ_NPTXFSTADDR) 333 334 /* Application (vendor) general purpose registers */ 335 #define USB_DWC2_GGPIO 0x0038UL 336 #define USB_DWC2_GGPIO_STM32_VBDEN_POS 21UL 337 #define USB_DWC2_GGPIO_STM32_VBDEN BIT(USB_DWC2_GGPIO_STM32_VBDEN_POS) 338 #define USB_DWC2_GGPIO_STM32_PWRDWN_POS 16UL 339 #define USB_DWC2_GGPIO_STM32_PWRDWN BIT(USB_DWC2_GGPIO_STM32_PWRDWN_POS) 340 341 /* GHWCFG1 register */ 342 #define USB_DWC2_GHWCFG1 0x0044UL 343 #define USB_DWC2_GHWCFG1_EPDIR_POS(i) (i * 2) 344 #define USB_DWC2_GHWCFG1_EPDIR_MASK(i) (0x3UL << USB_DWC2_GHWCFG1_EPDIR_POS(i)) 345 #define USB_DWC2_GHWCFG1_EPDIR_OUT 2 346 #define USB_DWC2_GHWCFG1_EPDIR_IN 1 347 #define USB_DWC2_GHWCFG1_EPDIR_BDIR 0 348 349 USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR) 350 351 /* GHWCFG2 register */ 352 #define USB_DWC2_GHWCFG2 0x0048UL 353 #define USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS 19UL 354 #define USB_DWC2_GHWCFG2_DYNFIFOSIZING BIT(USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS) 355 #define USB_DWC2_GHWCFG2_NUMDEVEPS_POS 10UL 356 #define USB_DWC2_GHWCFG2_NUMDEVEPS_MASK (0xFUL << USB_DWC2_GHWCFG2_NUMDEVEPS_POS) 357 #define USB_DWC2_GHWCFG2_FSPHYTYPE_POS 8UL 358 #define USB_DWC2_GHWCFG2_FSPHYTYPE_MASK (0x3UL << USB_DWC2_GHWCFG2_FSPHYTYPE_POS) 359 #define USB_DWC2_GHWCFG2_FSPHYTYPE_FSPLUSULPI 3 360 #define USB_DWC2_GHWCFG2_FSPHYTYPE_FSPLUSUTMI 2 361 #define USB_DWC2_GHWCFG2_FSPHYTYPE_FS 1 362 #define USB_DWC2_GHWCFG2_FSPHYTYPE_NO_FS 0 363 #define USB_DWC2_GHWCFG2_HSPHYTYPE_POS 6UL 364 #define USB_DWC2_GHWCFG2_HSPHYTYPE_MASK (0x3UL << USB_DWC2_GHWCFG2_HSPHYTYPE_POS) 365 #define USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUSULPI 3 366 #define USB_DWC2_GHWCFG2_HSPHYTYPE_ULPI 2 367 #define USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUS 1 368 #define USB_DWC2_GHWCFG2_HSPHYTYPE_NO_HS 0 369 #define USB_DWC2_GHWCFG2_OTGARCH_POS 3UL 370 #define USB_DWC2_GHWCFG2_OTGARCH_MASK (0x3UL << USB_DWC2_GHWCFG2_OTGARCH_POS) 371 #define USB_DWC2_GHWCFG2_OTGARCH_INTERNALDMA 2 372 #define USB_DWC2_GHWCFG2_OTGARCH_EXTERNALDMA 1 373 #define USB_DWC2_GHWCFG2_OTGARCH_SLAVEMODE 0 374 #define USB_DWC2_GHWCFG2_OTGMODE_POS 0UL 375 #define USB_DWC2_GHWCFG2_OTGMODE_MASK (0x7UL << USB_DWC2_GHWCFG2_OTGMODE_POS) 376 #define USB_DWC2_GHWCFG2_OTGMODE_NONOTGH 6 377 #define USB_DWC2_GHWCFG2_OTGMODE_SRPCAPH 5 378 #define USB_DWC2_GHWCFG2_OTGMODE_NONOTGD 4 379 #define USB_DWC2_GHWCFG2_OTGMODE_SRPCAPD 3 380 #define USB_DWC2_GHWCFG2_OTGMODE_NHNPNSRP 2 381 #define USB_DWC2_GHWCFG2_OTGMODE_SRPOTG 1 382 #define USB_DWC2_GHWCFG2_OTGMODE_HNPSRP 0 383 384 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_numdeveps, GHWCFG2_NUMDEVEPS) 385 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_fsphytype, GHWCFG2_FSPHYTYPE) 386 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_hsphytype, GHWCFG2_HSPHYTYPE) 387 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_otgarch, GHWCFG2_OTGARCH) 388 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_otgmode, GHWCFG2_OTGMODE) 389 390 /* GHWCFG3 register */ 391 #define USB_DWC2_GHWCFG3 0x004CUL 392 #define USB_DWC2_GHWCFG3_DFIFODEPTH_POS 16UL 393 #define USB_DWC2_GHWCFG3_DFIFODEPTH_MASK (0xFFFFUL << USB_DWC2_GHWCFG3_DFIFODEPTH_POS) 394 #define USB_DWC2_GHWCFG3_LPMMODE_POS 15UL 395 #define USB_DWC2_GHWCFG3_LPMMODE BIT(USB_DWC2_GHWCFG3_LPMMODE_POS) 396 #define USB_DWC2_GHWCFG3_OPTFEATURE_POS 10UL 397 #define USB_DWC2_GHWCFG3_OPTFEATURE BIT(USB_DWC2_GHWCFG3_OPTFEATURE_POS) 398 #define USB_DWC2_GHWCFG3_VNDCTLSUPT_POS 9UL 399 #define USB_DWC2_GHWCFG3_VNDCTLSUPT BIT(USB_DWC2_GHWCFG3_VNDCTLSUPT_POS) 400 #define USB_DWC2_GHWCFG3_OTGEN_POS 7UL 401 #define USB_DWC2_GHWCFG3_OTGEN BIT(USB_DWC2_GHWCFG3_OTGEN_POS) 402 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_POS 4UL 403 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_MASK (0x7UL << USB_DWC2_GHWCFG3_PKTSIZEWIDTH_POS) 404 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS10 6U 405 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS9 5U 406 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS8 4U 407 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS7 3U 408 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS6 2U 409 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS5 1U 410 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS4 0U 411 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_POS 0UL 412 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_MASK (0xFUL << USB_DWC2_GHWCFG3_XFERSIZEWIDTH_POS) 413 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH19 8U 414 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH18 7U 415 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH17 6U 416 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH16 5U 417 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH15 4U 418 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH14 3U 419 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH13 2U 420 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH12 1U 421 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH11 0U 422 423 #define GHWCFG3_PKTCOUNT(pktsizewidth) BIT_MASK(pktsizewidth + 4) 424 #define GHWCFG3_XFERSIZE(xfersizewidth) BIT_MASK(xfersizewidth + 11) 425 426 USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_dfifodepth, GHWCFG3_DFIFODEPTH) 427 USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_pktsizewidth, GHWCFG3_PKTSIZEWIDTH) 428 USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_xfersizewidth, GHWCFG3_XFERSIZEWIDTH) 429 430 /* GHWCFG4 register */ 431 #define USB_DWC2_GHWCFG4 0x0050UL 432 #define USB_DWC2_GHWCFG4_INEPS_POS 26UL 433 #define USB_DWC2_GHWCFG4_INEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_INEPS_POS) 434 #define USB_DWC2_GHWCFG4_DEDFIFOMODE_POS 25UL 435 #define USB_DWC2_GHWCFG4_DEDFIFOMODE BIT(USB_DWC2_GHWCFG4_DEDFIFOMODE_POS) 436 #define USB_DWC2_GHWCFG4_NUMCTLEPS_POS 16UL 437 #define USB_DWC2_GHWCFG4_NUMCTLEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMCTLEPS_POS) 438 #define USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS 14UL 439 #define USB_DWC2_GHWCFG4_PHYDATAWIDTH_MASK (0x3UL << USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS) 440 #define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS 0UL 441 #define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS) 442 443 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_ineps, GHWCFG4_INEPS) 444 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numctleps, GHWCFG4_NUMCTLEPS) 445 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_phydatawidth, GHWCFG4_PHYDATAWIDTH) 446 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numdevperioeps, GHWCFG4_NUMDEVPERIOEPS) 447 448 /* GDFIFOCFG register */ 449 #define USB_DWC2_GDFIFOCFG 0x005CUL 450 #define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS 16UL 451 #define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_MASK (0xFFFFUL << USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS) 452 #define USB_DWC2_GDFIFOCFG_GDFIFOCFG_POS 0UL 453 #define USB_DWC2_GDFIFOCFG_GDFIFOCFG_MASK (0xFFFFUL << USB_DWC2_GDFIFOCFG_GDFIFOCFG_POS) 454 455 USB_DWC2_GET_FIELD_DEFINE(gdfifocfg_epinfobaseaddr, GDFIFOCFG_EPINFOBASEADDR) 456 USB_DWC2_GET_FIELD_DEFINE(gdfifocfg_gdfifocfg, GDFIFOCFG_GDFIFOCFG) 457 USB_DWC2_SET_FIELD_DEFINE(gdfifocfg_epinfobaseaddr, GDFIFOCFG_EPINFOBASEADDR) 458 USB_DWC2_SET_FIELD_DEFINE(gdfifocfg_gdfifocfg, GDFIFOCFG_GDFIFOCFG) 459 460 /* Device IN endpoint transmit FIFO size register */ 461 #define USB_DWC2_DIEPTXF1 0x0104UL 462 #define USB_DWC2_DIEPTXF_INEPNTXFDEP_POS 16UL 463 #define USB_DWC2_DIEPTXF_INEPNTXFDEP_MASK (0xFFFFUL << USB_DWC2_DIEPTXF_INEPNTXFDEP_POS) 464 #define USB_DWC2_DIEPTXF_INEPNTXFSTADDR_POS 0UL 465 #define USB_DWC2_DIEPTXF_INEPNTXFSTADDR_MASK (0xFFFFUL << USB_DWC2_DIEPTXF_INEPNTXFSTADDR_POS) 466 467 USB_DWC2_GET_FIELD_DEFINE(dieptxf_inepntxfdep, DIEPTXF_INEPNTXFDEP) 468 USB_DWC2_GET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR) 469 USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfdep, DIEPTXF_INEPNTXFDEP) 470 USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR) 471 472 /* Device configuration registers */ 473 #define USB_DWC2_DCFG 0x0800UL 474 #define USB_DWC2_DCFG_RESVALID_POS 26UL 475 #define USB_DWC2_DCFG_RESVALID_MASK (0x3FUL << USB_DWC2_DCFG_RESVALID_POS) 476 #define USB_DWC2_DCFG_PERSCHINTVL_POS 24UL 477 #define USB_DWC2_DCFG_PERSCHINTVL_MASK (0x3UL << USB_DWC2_DCFG_PERSCHINTVL_POS) 478 #define USB_DWC2_DCFG_PERSCHINTVL_MF25 0 479 #define USB_DWC2_DCFG_PERSCHINTVL_MF50 1 480 #define USB_DWC2_DCFG_PERSCHINTVL_MF75 2 481 #define USB_DWC2_DCFG_PERSCHINTVL_RESERVED 3 482 #define USB_DWC2_DCFG_DESCDMA_POS 23UL 483 #define USB_DWC2_DCFG_DESCDMA BIT(USB_DWC2_DCFG_DESCDMA_POS) 484 #define USB_DWC2_DCFG_EPMISCNT_POS 18UL 485 #define USB_DWC2_DCFG_EPMISCNT_MASK (0x1FUL << USB_DWC2_DCFG_EPMISCNT_POS) 486 #define USB_DWC2_DCFG_IPGISOCSUPT_POS 17UL 487 #define USB_DWC2_DCFG_IPGISOCSUPT BIT(USB_DWC2_DCFG_IPGISOCSUPT_POS) 488 #define USB_DWC2_DCFG_ERRATICINTMSK_POS 15UL 489 #define USB_DWC2_DCFG_ERRATICINTMSK BIT(USB_DWC2_DCFG_ERRATICINTMSK_POS) 490 #define USB_DWC2_DCFG_XCVRDLY_POS 14UL 491 #define USB_DWC2_DCFG_XCVRDLY BIT(USB_DWC2_DCFG_XCVRDLY_POS) 492 #define USB_DWC2_DCFG_ENDEVOUTNAK_POS 13UL 493 #define USB_DWC2_DCFG_ENDEVOUTNAK BIT(USB_DWC2_DCFG_ENDEVOUTNAK_POS) 494 #define USB_DWC2_DCFG_PERFRINT_POS 11UL 495 #define USB_DWC2_DCFG_PERFRINT_MASK (0x3UL << USB_DWC2_DCFG_PERFRINT_POS) 496 #define USB_DWC2_DCFG_PERFRINT_EOPF80 0 497 #define USB_DWC2_DCFG_PERFRINT_EOPF85 1 498 #define USB_DWC2_DCFG_PERFRINT_EOPF90 2 499 #define USB_DWC2_DCFG_PERFRINT_EOPF95 3 500 #define USB_DWC2_DCFG_DEVADDR_POS 4UL 501 #define USB_DWC2_DCFG_DEVADDR_MASK (0x7FUL << USB_DWC2_DCFG_DEVADDR_POS) 502 #define USB_DWC2_DCFG_ENA32KHZSUSP_POS 3UL 503 #define USB_DWC2_DCFG_ENA32KHZSUSP BIT(USB_DWC2_DCFG_ENA32KHZSUSP_POS) 504 #define USB_DWC2_DCFG_NZSTSOUTHSHK_POS 2UL 505 #define USB_DWC2_DCFG_NZSTSOUTHSHK BIT(USB_DWC2_DCFG_NZSTSOUTHSHK_POS) 506 #define USB_DWC2_DCFG_DEVSPD_POS 0UL 507 #define USB_DWC2_DCFG_DEVSPD_MASK (0x03UL << USB_DWC2_DCFG_DEVSPD_POS) 508 #define USB_DWC2_DCFG_DEVSPD_USBHS20 0 509 #define USB_DWC2_DCFG_DEVSPD_USBFS20 1 510 #define USB_DWC2_DCFG_DEVSPD_USBLS116 2 511 #define USB_DWC2_DCFG_DEVSPD_USBFS1148 3 512 513 USB_DWC2_SET_FIELD_DEFINE(dcfg_resvalid, DCFG_RESVALID) 514 USB_DWC2_SET_FIELD_DEFINE(dcfg_perschintvl, DCFG_PERSCHINTVL) 515 USB_DWC2_SET_FIELD_DEFINE(dcfg_epmiscnt, DCFG_EPMISCNT) 516 USB_DWC2_SET_FIELD_DEFINE(dcfg_perfrint, DCFG_PERFRINT) 517 USB_DWC2_SET_FIELD_DEFINE(dcfg_devaddr, DCFG_DEVADDR) 518 USB_DWC2_SET_FIELD_DEFINE(dcfg_devspd, DCFG_DEVSPD) 519 USB_DWC2_GET_FIELD_DEFINE(dcfg_resvalid, DCFG_RESVALID) 520 USB_DWC2_GET_FIELD_DEFINE(dcfg_perschintvl, DCFG_PERSCHINTVL) 521 USB_DWC2_GET_FIELD_DEFINE(dcfg_epmiscnt, DCFG_EPMISCNT) 522 USB_DWC2_GET_FIELD_DEFINE(dcfg_perfrint, DCFG_PERFRINT) 523 USB_DWC2_GET_FIELD_DEFINE(dcfg_devaddr, DCFG_DEVADDR) 524 USB_DWC2_GET_FIELD_DEFINE(dcfg_devspd, DCFG_DEVSPD) 525 526 /* Device control register */ 527 #define USB_DWC2_DCTL 0x0804UL 528 #define USB_DWC2_DCTL_SERVINT_POS 19UL 529 #define USB_DWC2_DCTL_SERVINT BIT(USB_DWC2_DCTL_SERVINT_POS) 530 #define USB_DWC2_DCTL_DEEPSLEEPBESLREJECT_POS 18UL 531 #define USB_DWC2_DCTL_DEEPSLEEPBESLREJECT BIT(USB_DWC2_DCTL_DEEPSLEEPBESLREJECT_POS) 532 #define USB_DWC2_DCTL_NAKONBBLE_POS 16UL 533 #define USB_DWC2_DCTL_NAKONBBLE BIT(USB_DWC2_DCTL_NAKONBBLE_POS) 534 #define USB_DWC2_DCTL_IGNRFRMNUM_POS 15UL 535 #define USB_DWC2_DCTL_IGNRFRMNUM BIT(USB_DWC2_DCTL_IGNRFRMNUM_POS) 536 #define USB_DWC2_DCTL_PWRONPRGDONE_POS 11UL 537 #define USB_DWC2_DCTL_PWRONPRGDONE BIT(USB_DWC2_DCTL_PWRONPRGDONE_POS) 538 #define USB_DWC2_DCTL_CGOUTNAK_POS 10UL 539 #define USB_DWC2_DCTL_CGOUTNAK BIT(USB_DWC2_DCTL_CGOUTNAK_POS) 540 #define USB_DWC2_DCTL_SGOUTNAK_POS 9UL 541 #define USB_DWC2_DCTL_SGOUTNAK BIT(USB_DWC2_DCTL_SGOUTNAK_POS) 542 #define USB_DWC2_DCTL_CGNPINNAK_POS 8UL 543 #define USB_DWC2_DCTL_CGNPINNAK BIT(USB_DWC2_DCTL_CGNPINNAK_POS) 544 #define USB_DWC2_DCTL_SGNPINNAK_POS 7UL 545 #define USB_DWC2_DCTL_SGNPINNAK BIT(USB_DWC2_DCTL_SGNPINNAK_POS) 546 #define USB_DWC2_DCTL_TSTCTL_POS 4UL 547 #define USB_DWC2_DCTL_TSTCTL_MASK (0x7UL << USB_DWC2_DCTL_TSTCTL_POS) 548 #define USB_DWC2_DCTL_TSTCTL_TESTFE 5UL 549 #define USB_DWC2_DCTL_TSTCTL_TESTPM 4UL 550 #define USB_DWC2_DCTL_TSTCTL_TESTSN 3UL 551 #define USB_DWC2_DCTL_TSTCTL_TESTK 2UL 552 #define USB_DWC2_DCTL_TSTCTL_TESTJ 1UL 553 #define USB_DWC2_DCTL_TSTCTL_DISABLED 0UL 554 #define USB_DWC2_DCTL_GOUTNAKSTS_POS 3UL 555 #define USB_DWC2_DCTL_GOUTNAKSTS BIT(USB_DWC2_DCTL_GOUTNAKSTS_POS) 556 #define USB_DWC2_DCTL_GNPINNAKSTS_POS 2UL 557 #define USB_DWC2_DCTL_GNPINNAKSTS BIT(USB_DWC2_DCTL_GNPINNAKSTS_POS) 558 #define USB_DWC2_DCTL_SFTDISCON_POS 1UL 559 #define USB_DWC2_DCTL_SFTDISCON BIT(USB_DWC2_DCTL_SFTDISCON_POS) 560 #define USB_DWC2_DCTL_RMTWKUPSIG_POS 0UL 561 #define USB_DWC2_DCTL_RMTWKUPSIG BIT(USB_DWC2_DCTL_RMTWKUPSIG_POS) 562 563 USB_DWC2_GET_FIELD_DEFINE(dctl_tstctl, DCTL_TSTCTL) 564 USB_DWC2_SET_FIELD_DEFINE(dctl_tstctl, DCTL_TSTCTL) 565 566 /* Device status register */ 567 #define USB_DWC2_DSTS 0x0808UL 568 #define USB_DWC2_DSTS_ENUMSPD_POS 1UL 569 #define USB_DWC2_DSTS_ENUMSPD_MASK (0x3UL << USB_DWC2_DSTS_ENUMSPD_POS) 570 #define USB_DWC2_DSTS_ENUMSPD_HS3060 0 571 #define USB_DWC2_DSTS_ENUMSPD_FS3060 1 572 #define USB_DWC2_DSTS_ENUMSPD_LS6 2 573 #define USB_DWC2_DSTS_ENUMSPD_FS48 3 574 575 USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD) 576 577 /* Device all endpoints interrupt registers */ 578 #define USB_DWC2_DAINT 0x0818UL 579 #define USB_DWC2_DAINTMSK 0x081CUL 580 #define USB_DWC2_DAINT_OUTEPINT(ep_num) BIT(16UL + ep_num) 581 #define USB_DWC2_DAINT_INEPINT(ep_num) BIT(ep_num) 582 583 /* Device threshold control register */ 584 #define USB_DWC2_DTHRCTL 0x0830UL 585 #define USB_DWC2_DTHRCTL_ARBPRKEN_POS 27UL 586 #define USB_DWC2_DTHRCTL_ARBPRKEN BIT(USB_DWC2_DTHRCTL_ARBPRKEN_POS) 587 #define USB_DWC2_DTHRCTL_RXTHRLEN_POS 17UL 588 #define USB_DWC2_DTHRCTL_RXTHRLEN_MASK (0x1FFUL << USB_DWC2_DTHRCTL_RXTHRLEN_POS) 589 #define USB_DWC2_DTHRCTL_RXTHREN_POS 16UL 590 #define USB_DWC2_DTHRCTL_RXTHREN BIT(USB_DWC2_DTHRCTL_RXTHREN_POS) 591 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_POS 11UL 592 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_MASK (0x3UL << USB_DWC2_DTHRCTL_AHBTHRRATIO_POS) 593 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESZERO 0 594 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESONE 1 595 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESTWO 2 596 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESTHREE 3 597 #define USB_DWC2_DTHRCTL_TXTHRLEN_POS 2UL 598 #define USB_DWC2_DTHRCTL_TXTHRLEN_MASK (0x1FFUL << USB_DWC2_DTHRCTL_TXTHRLEN_POS) 599 #define USB_DWC2_DTHRCTL_ISOTHREN_POS 1UL 600 #define USB_DWC2_DTHRCTL_ISOTHREN BIT(USB_DWC2_DTHRCTL_ISOTHREN_POS) 601 #define USB_DWC2_DTHRCTL_NONISOTHREN_POS 0UL 602 #define USB_DWC2_DTHRCTL_NONISOTHREN BIT(USB_DWC2_DTHRCTL_NONISOTHREN_POS) 603 604 USB_DWC2_GET_FIELD_DEFINE(dthrctl_rxthrlen, DTHRCTL_RXTHRLEN) 605 USB_DWC2_GET_FIELD_DEFINE(dthrctl_ahbthrratio, DTHRCTL_AHBTHRRATIO) 606 USB_DWC2_GET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN) 607 USB_DWC2_SET_FIELD_DEFINE(dthrctl_rxthrlen, DTHRCTL_RXTHRLEN) 608 USB_DWC2_SET_FIELD_DEFINE(dthrctl_ahbthrratio, DTHRCTL_AHBTHRRATIO) 609 USB_DWC2_SET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN) 610 611 /* 612 * Device IN/OUT endpoint control register 613 * IN endpoint offsets 0x0900 + (0x20 * n), n = 0 .. x, 614 * OUT endpoint offsets 0x0B00 + (0x20 * n), n = 0 .. x, 615 * 616 */ 617 #define USB_DWC2_DIEPCTL0 0x0900UL 618 #define USB_DWC2_DOEPCTL0 0x0B00UL 619 #define USB_DWC2_DEPCTL_EPENA_POS 31UL 620 #define USB_DWC2_DEPCTL_EPENA BIT(USB_DWC2_DEPCTL_EPENA_POS) 621 #define USB_DWC2_DEPCTL_EPDIS_POS 30UL 622 #define USB_DWC2_DEPCTL_EPDIS BIT(USB_DWC2_DEPCTL_EPDIS_POS) 623 #define USB_DWC2_DEPCTL_SETD1PID_POS 29UL 624 #define USB_DWC2_DEPCTL_SETD1PID BIT(USB_DWC2_DEPCTL_SETD1PID_POS) 625 #define USB_DWC2_DEPCTL_SETD0PID_POS 28UL 626 #define USB_DWC2_DEPCTL_SETD0PID BIT(USB_DWC2_DEPCTL_SETD0PID_POS) 627 #define USB_DWC2_DEPCTL_SNAK_POS 27UL 628 #define USB_DWC2_DEPCTL_SNAK BIT(USB_DWC2_DEPCTL_SNAK_POS) 629 #define USB_DWC2_DEPCTL_CNAK_POS 26UL 630 #define USB_DWC2_DEPCTL_CNAK BIT(USB_DWC2_DEPCTL_CNAK_POS) 631 #define USB_DWC2_DEPCTL_TXFNUM_POS 22UL 632 #define USB_DWC2_DEPCTL_TXFNUM_MASK (0xFUL << USB_DWC2_DEPCTL_TXFNUM_POS) 633 #define USB_DWC2_DEPCTL_STALL_POS 21UL 634 #define USB_DWC2_DEPCTL_STALL BIT(USB_DWC2_DEPCTL_STALL_POS) 635 #define USB_DWC2_DEPCTL_EPTYPE_POS 18UL 636 #define USB_DWC2_DEPCTL_EPTYPE_MASK (0x3UL << USB_DWC2_DEPCTL_EPTYPE_POS) 637 #define USB_DWC2_DEPCTL_EPTYPE_INTERRUPT 3 638 #define USB_DWC2_DEPCTL_EPTYPE_BULK 2 639 #define USB_DWC2_DEPCTL_EPTYPE_ISO 1 640 #define USB_DWC2_DEPCTL_EPTYPE_CONTROL 0 641 #define USB_DWC2_DEPCTL_NAKSTS_POS 17UL 642 #define USB_DWC2_DEPCTL_NAKSTS BIT(USB_DWC2_DEPCTL_NAKSTS_POS) 643 #define USB_DWC2_DEPCTL_DPID_POS 16UL 644 #define USB_DWC2_DEPCTL_DPID BIT(USB_DWC2_DEPCTL_DPID_POS) 645 #define USB_DWC2_DEPCTL_USBACTEP_POS 15UL 646 #define USB_DWC2_DEPCTL_USBACTEP BIT(USB_DWC2_DEPCTL_USBACTEP_POS) 647 #define USB_DWC2_DEPCTL0_MPS_POS 0UL 648 #define USB_DWC2_DEPCTL0_MPS_MASK (0x3UL << USB_DWC2_DEPCTL0_MPS_POS) 649 #define USB_DWC2_DEPCTL0_MPS_8 3 650 #define USB_DWC2_DEPCTL0_MPS_16 2 651 #define USB_DWC2_DEPCTL0_MPS_32 1 652 #define USB_DWC2_DEPCTL0_MPS_64 0 653 #define USB_DWC2_DEPCTL_MPS_POS 0UL 654 #define USB_DWC2_DEPCTL_MPS_MASK (0x7FF << USB_DWC2_DEPCTL_MPS_POS) 655 656 USB_DWC2_GET_FIELD_DEFINE(depctl_txfnum, DEPCTL_TXFNUM) 657 USB_DWC2_SET_FIELD_DEFINE(depctl_txfnum, DEPCTL_TXFNUM) 658 USB_DWC2_GET_FIELD_DEFINE(depctl_eptype, DEPCTL_EPTYPE) 659 USB_DWC2_SET_FIELD_DEFINE(depctl_eptype, DEPCTL_EPTYPE) 660 USB_DWC2_GET_FIELD_DEFINE(depctl0_mps, DEPCTL0_MPS) 661 USB_DWC2_SET_FIELD_DEFINE(depctl0_mps, DEPCTL0_MPS) 662 USB_DWC2_GET_FIELD_DEFINE(depctl_mps, DEPCTL_MPS) 663 USB_DWC2_SET_FIELD_DEFINE(depctl_mps, DEPCTL_MPS) 664 665 /* 666 * Device IN endpoint interrupt register 667 * offsets 0x0908 + (0x20 * n), n = 0 .. x 668 */ 669 #define USB_DWC2_DIEPINT0 0x0908UL 670 #define USB_DWC2_DIEPINT_NYETINTRPT_POS 14UL 671 #define USB_DWC2_DIEPINT_NYETINTRPT BIT(USB_DWC2_DIEPINT_NYETINTRPT_POS) 672 #define USB_DWC2_DIEPINT_NAKINTRPT_POS 13UL 673 #define USB_DWC2_DIEPINT_NAKINTRPT BIT(USB_DWC2_DIEPINT_NAKINTRPT_POS) 674 #define USB_DWC2_DIEPINT_BBLEERR_POS 12UL 675 #define USB_DWC2_DIEPINT_BBLEERR BIT(USB_DWC2_DIEPINT_BBLEERR_POS) 676 #define USB_DWC2_DIEPINT_PKTDRPSTS_POS 11UL 677 #define USB_DWC2_DIEPINT_PKTDRPSTS BIT(USB_DWC2_DIEPINT_PKTDRPSTS_POS) 678 #define USB_DWC2_DIEPINT_BNAINTR_POS 9UL 679 #define USB_DWC2_DIEPINT_BNAINTR BIT(USB_DWC2_DIEPINT_BNAINTR_POS) 680 #define USB_DWC2_DIEPINT_TXFIFOUNDRN_POS 8UL 681 #define USB_DWC2_DIEPINT_TXFIFOUNDRN BIT(USB_DWC2_DIEPINT_TXFIFOUNDRN_POS) 682 #define USB_DWC2_DIEPINT_TXFEMP_POS 7UL 683 #define USB_DWC2_DIEPINT_TXFEMP BIT(USB_DWC2_DIEPINT_TXFEMP_POS) 684 #define USB_DWC2_DIEPINT_INEPNAKEFF_POS 6UL 685 #define USB_DWC2_DIEPINT_INEPNAKEFF BIT(USB_DWC2_DIEPINT_INEPNAKEFF_POS) 686 #define USB_DWC2_DIEPINT_INTKNEPMIS_POS 5UL 687 #define USB_DWC2_DIEPINT_INTKNEPMIS BIT(USB_DWC2_DIEPINT_INTKNEPMIS_POS) 688 #define USB_DWC2_DIEPINT_INTKNTXFEMP_POS 4UL 689 #define USB_DWC2_DIEPINT_INTKNTXFEMP BIT(USB_DWC2_DIEPINT_INTKNTXFEMP_POS) 690 #define USB_DWC2_DIEPINT_TIMEOUT_POS 3UL 691 #define USB_DWC2_DIEPINT_TIMEOUT BIT(USB_DWC2_DIEPINT_TIMEOUT_POS) 692 #define USB_DWC2_DIEPINT_AHBERR_POS 2UL 693 #define USB_DWC2_DIEPINT_AHBERR BIT(USB_DWC2_DIEPINT_AHBERR_POS) 694 #define USB_DWC2_DIEPINT_EPDISBLD_POS 1UL 695 #define USB_DWC2_DIEPINT_EPDISBLD BIT(USB_DWC2_DIEPINT_EPDISBLD_POS) 696 #define USB_DWC2_DIEPINT_XFERCOMPL_POS 0UL 697 #define USB_DWC2_DIEPINT_XFERCOMPL BIT(USB_DWC2_DIEPINT_XFERCOMPL_POS) 698 699 /* 700 * Device OUT endpoint interrupt register 701 * offsets 0x0B08 + (0x20 * n), n = 0 .. x 702 */ 703 #define USB_DWC2_DOEPINT0 0x0B08UL 704 #define USB_DWC2_DOEPINT_STUPPKTRCVD_POS 15UL 705 #define USB_DWC2_DOEPINT_STUPPKTRCVD BIT(USB_DWC2_DOEPINT_STUPPKTRCVD_POS) 706 #define USB_DWC2_DOEPINT_NYETINTRPT_POS 14UL 707 #define USB_DWC2_DOEPINT_NYETINTRPT BIT(USB_DWC2_DOEPINT_NYETINTRPT_POS) 708 #define USB_DWC2_DOEPINT_NAKINTRPT_POS 13UL 709 #define USB_DWC2_DOEPINT_NAKINTRPT BIT(USB_DWC2_DOEPINT_NAKINTRPT_POS) 710 #define USB_DWC2_DOEPINT_BBLEERR_POS 12UL 711 #define USB_DWC2_DOEPINT_BBLEERR BIT(USB_DWC2_DOEPINT_BBLEERR_POS) 712 #define USB_DWC2_DOEPINT_PKTDRPSTS_POS 11UL 713 #define USB_DWC2_DOEPINT_PKTDRPSTS BIT(USB_DWC2_DOEPINT_PKTDRPSTS_POS) 714 #define USB_DWC2_DOEPINT_BNAINTR_POS 9UL 715 #define USB_DWC2_DOEPINT_BNAINTR BIT(USB_DWC2_DOEPINT_BNAINTR_POS) 716 #define USB_DWC2_DOEPINT_OUTPKTERR_POS 8UL 717 #define USB_DWC2_DOEPINT_OUTPKTERR BIT(USB_DWC2_DOEPINT_OUTPKTERR_POS) 718 #define USB_DWC2_DOEPINT_BACK2BACKSETUP_POS 6UL 719 #define USB_DWC2_DOEPINT_BACK2BACKSETUP BIT(USB_DWC2_DOEPINT_BACK2BACKSETUP_POS) 720 #define USB_DWC2_DOEPINT_STSPHSERCVD_POS 5UL 721 #define USB_DWC2_DOEPINT_STSPHSERCVD BIT(USB_DWC2_DOEPINT_STSPHSERCVD_POS) 722 #define USB_DWC2_DOEPINT_OUTTKNEPDIS_POS 4UL 723 #define USB_DWC2_DOEPINT_OUTTKNEPDIS BIT(USB_DWC2_DOEPINT_OUTTKNEPDIS_POS) 724 #define USB_DWC2_DOEPINT_SETUP_POS 3UL 725 #define USB_DWC2_DOEPINT_SETUP BIT(USB_DWC2_DOEPINT_SETUP_POS) 726 #define USB_DWC2_DOEPINT_AHBERR_POS 2UL 727 #define USB_DWC2_DOEPINT_AHBERR BIT(USB_DWC2_DOEPINT_AHBERR_POS) 728 #define USB_DWC2_DOEPINT_EPDISBLD_POS 1UL 729 #define USB_DWC2_DOEPINT_EPDISBLD BIT(USB_DWC2_DOEPINT_EPDISBLD_POS) 730 #define USB_DWC2_DOEPINT_XFERCOMPL_POS 0UL 731 #define USB_DWC2_DOEPINT_XFERCOMPL BIT(USB_DWC2_DOEPINT_XFERCOMPL_POS) 732 733 /* 734 * Device IN/OUT control endpoint transfer size register 735 */ 736 #define USB_DWC2_DIEPTSIZ0 0x0910UL 737 #define USB_DWC2_DOEPTSIZ0 0x0B10UL 738 #define USB_DWC2_DOEPTSIZ0_SUPCNT_POS 29UL 739 #define USB_DWC2_DOEPTSIZ0_SUPCNT_MASK (0x3UL << USB_DWC2_DOEPTSIZ0_SUPCNT_POS) 740 #define USB_DWC2_DOEPTSIZ0_PKTCNT_POS 19UL 741 #define USB_DWC2_DOEPTSIZ0_PKTCNT_MASK (0x1UL << USB_DWC2_DOEPTSIZ0_PKTCNT_POS) 742 #define USB_DWC2_DIEPTSIZ0_PKTCNT_POS 19UL 743 #define USB_DWC2_DIEPTSIZ0_PKTCNT_MASK (0x3UL << USB_DWC2_DIEPTSIZ0_PKTCNT_POS) 744 #define USB_DWC2_DEPTSIZ0_XFERSIZE_POS 0UL 745 #define USB_DWC2_DEPTSIZ0_XFERSIZE_MASK 0x7FUL 746 747 USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_supcnt, DOEPTSIZ0_SUPCNT) 748 USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_pktcnt, DOEPTSIZ0_PKTCNT) 749 USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_xfersize, DEPTSIZ0_XFERSIZE) 750 USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_pktcnt, DIEPTSIZ0_PKTCNT) 751 USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_xfersize, DEPTSIZ0_XFERSIZE) 752 753 /* 754 * Device IN/OUT endpoint transfer size register 755 * IN at offsets 0x0910 + (0x20 * n), n = 1 .. x, 756 * OUT at offsets 0x0B10 + (0x20 * n), n = 1 .. x 757 */ 758 #define USB_DWC2_DEPTSIZN_PKTCNT_POS 19UL 759 #define USB_DWC2_DEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DEPTSIZN_PKTCNT_POS) 760 #define USB_DWC2_DEPTSIZN_XFERSIZE_POS 0UL 761 #define USB_DWC2_DEPTSIZN_XFERSIZE_MASK 0x7FFFFUL 762 763 USB_DWC2_GET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT) 764 USB_DWC2_GET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE) 765 USB_DWC2_SET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT) 766 USB_DWC2_SET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE) 767 768 /* 769 * Device IN/OUT endpoint transfer size register 770 * IN at offsets 0x0910 + (0x20 * n), n = 0 .. x, 771 * OUT at offsets 0x0B10 + (0x20 * n), n = 0 .. x 772 * 773 * Note: Legacy definitions for the usb_dc_dw.c driver only. 774 */ 775 #define USB_DWC2_DEPTSIZ_PKT_CNT_POS 19UL 776 #define USB_DWC2_DIEPTSIZ0_PKT_CNT_MASK (0x3 << 19) 777 #define USB_DWC2_DIEPTSIZn_PKT_CNT_MASK (0x3FF << 19) 778 #define USB_DWC2_DOEPTSIZn_PKT_CNT_MASK (0x3FF << 19) 779 #define USB_DWC2_DOEPTSIZ0_PKT_CNT_MASK (0x1 << 19) 780 #define USB_DWC2_DOEPTSIZ_SUP_CNT_POS 29UL 781 #define USB_DWC2_DOEPTSIZ_SUP_CNT_MASK (0x3 << 29) 782 #define USB_DWC2_DEPTSIZ_XFER_SIZE_POS 0UL 783 #define USB_DWC2_DEPTSIZ0_XFER_SIZE_MASK 0x7F 784 #define USB_DWC2_DEPTSIZn_XFER_SIZE_MASK 0x7FFFF 785 786 /* 787 * Device IN endpoint transmit FIFO status register, 788 * offsets 0x0918 + (0x20 * n), n = 0 .. x 789 */ 790 #define USB_DWC2_DTXFSTS0 0x0918UL 791 #define USB_DWC2_DTXFSTS_INEPTXFSPCAVAIL_POS 0UL 792 #define USB_DWC2_DTXFSTS_INEPTXFSPCAVAIL_MASK 0xFFFFUL 793 794 USB_DWC2_GET_FIELD_DEFINE(dtxfsts_ineptxfspcavail, DTXFSTS_INEPTXFSPCAVAIL) 795 796 #ifdef __cplusplus 797 } 798 #endif 799 800 #endif /* ZEPHYR_DRIVERS_USB_COMMON_USB_DWC2_HW */ 801
