1 /* 2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _USBC_X_H_ 8 #define _USBC_X_H_ 9 10 #define REG8 __IO uint8_t 11 #define REG16 __IO uint16_t 12 #define REG32 __IO uint32_t 13 14 // ============================================================================= 15 // MACROS 16 // ============================================================================= 17 #define SPFIFORAM_SIZE (264) 18 #define DIEP_NUM (3) 19 #define DOEP_NUM (2) 20 21 // ============================================================================= 22 // TYPES 23 // ============================================================================= 24 25 // ============================================================================ 26 // USBC_T 27 // ----------------------------------------------------------------------------- 28 /// 29 // ============================================================================= 30 31 /* EP0 */ 32 struct musb_ep0_regs 33 { 34 REG16 reserved4; 35 REG16 csr0; 36 REG16 reserved5; 37 REG16 reserved6; 38 REG16 count0; 39 REG8 host_type0; 40 REG8 host_naklimit0; 41 REG8 reserved7; 42 REG8 reserved8; 43 REG8 reserved9; 44 REG8 configdata; 45 }; 46 47 48 /* EP 1-15 */ 49 struct musb_epN_regs 50 { 51 REG16 txmaxp; 52 REG16 txcsr; 53 REG16 rxmaxp; 54 REG16 rxcsr; 55 REG16 rxcount; 56 REG8 txtype; 57 REG8 txinterval; 58 REG8 rxtype; 59 REG8 rxinterval; 60 REG8 reserved0; 61 REG8 fifosize; 62 }; 63 64 typedef volatile struct 65 { 66 /* common registers */ 67 REG8 faddr; //0x0000 68 REG8 power; //0x0001 69 REG16 intrtx; //0x0002 70 REG16 intrrx; //0x0004 71 REG16 intrtxe; //0x0006 72 REG16 intrrxe; //0x0008 73 REG8 intrusb; //0x000a 74 REG8 intrusbe; //0x000b 75 REG16 frame; //0x000c 76 REG8 index; //0x000e 77 REG8 testmode; //0x000f 78 /* indexed registers */ 79 REG16 txmaxp; //0x0010 80 REG16 csr0_txcsr; //0x0012 81 REG16 rxmaxp; //0x0014 82 REG16 rxcsr; //0x0016 83 REG16 rxcount; //0x0018 84 REG8 txtype; //0x001a 85 REG8 txinterval; //0x001b 86 REG8 rxtype; //0x001c 87 REG8 rxinterval; //0x001d 88 REG8 reserved0; //0x001e 89 REG8 cfdt_fifosz; //0x001f 90 /* fifo */ 91 REG32 fifox[0x10]; //0x0020 92 /* OTG, dynamic FIFO, version & vendor registers */ 93 REG8 devctl; //0x0060 94 REG8 reserved1; //0x0061 95 REG8 txfifosz; //0x0062 96 REG8 rxfifosz; //0x0063 97 REG16 txfifoadd; //0x0064 98 REG16 rxfifoadd; //0x0066 99 REG32 vcontrol; //0x0068 100 REG16 hwvers; //0x006c 101 REG16 reserved2a[1]; //0x006e 102 REG8 ulpi_busctl; //0x0070 103 REG8 reserved2b[1]; //0x0071 104 REG16 reserved2[3]; //0x0072 105 REG8 epinfo; //0x0078 106 REG8 raminfo; //0x0079 107 REG8 linkinfo; //0x007a 108 REG8 vplen; //0x007b 109 REG8 hseof1; //0x007c 110 REG8 fseof1; //0x007d 111 REG8 lseof1; //0x007e 112 REG8 soft_rst; //0x007f 113 /* target address registers */ //0x0080 114 struct musb_tar_regs 115 { 116 REG8 txfuncaddr; 117 REG8 reserved0; 118 REG8 txhubaddr; 119 REG8 txhubport; 120 REG8 rxfuncaddr; 121 REG8 reserved1; 122 REG8 rxhubaddr; 123 REG8 rxhubport; 124 } tar[0x10]; 125 /* 126 * endpoint registers 127 * ep0 elements are valid when array index is 0 128 * otherwise epN is valid 129 */ 130 union musb_ep_regs //0x0100 131 { 132 struct musb_ep0_regs ep0; 133 struct musb_epN_regs epN; 134 } ep[0x10]; 135 136 //REG32 reserved1fe; //0x0200 137 REG32 dmaintr; 138 139 struct musb_dma_regs 140 { 141 REG32 cntl; //0x0204 142 REG32 addr; //0x0208 143 REG32 count; //0x020c 144 REG32 rsvd; //0x0210 145 } dma[0x10]; 146 147 148 struct musb_rqpktcount 149 { 150 REG32 count; //0x0304 151 } rqpktcount[0xf]; 152 153 REG8 dpbrxdisl; //0x0340 154 REG8 dpbrxdish; //0x0341 155 REG8 dpbtxdisl; //0x0342 156 REG8 dpbtxdish; //0x0343 157 158 struct musb_reserved_2 159 { 160 REG32 reserved_2; //0x0344 161 } rsvd_2[0x9]; 162 163 REG8 dbgl; //0x0368 164 REG8 dbgh; //0x0369 165 REG16 reserved_0; //0x036a 166 REG32 reserved_1; //0x036c 167 REG8 usbcfg; //0x0370 168 169 struct musb_reserved_3 170 { 171 REG8 reserved_3; //0x0371~0x3bb 172 } rsvd_3[0x4b]; 173 174 REG8 dbgcntl0; //0x3bc 175 REG8 dbgcntl1; //0x3bd 176 } __attribute__((packed, aligned(32))) USBC_X_Typedef; 177 178 179 180 #define BIT0 (0x0001) 181 #define BIT1 (0x0002) 182 #define BIT2 (0x0004) 183 #define BIT3 (0x0008) 184 #define BIT4 (0x0010) 185 #define BIT5 (0x0020) 186 #define BIT6 (0x0040) 187 #define BIT7 (0x0080) 188 189 190 /* CSR0 */ 191 #define USB_CSR0_FLUSHFIFO (0x0100) 192 #define USB_CSR0_TXPKTRDY (0x0002) 193 #define USB_CSR0_RXPKTRDY (0x0001) 194 195 /* CSR0 in Peripheral mode */ 196 #define USB_CSR0_P_SVDSETUPEND (0x0080) 197 #define USB_CSR0_P_SVDRXPKTRDY (0x0040) 198 #define USB_CSR0_P_SENDSTALL (0x0020) 199 #define USB_CSR0_P_SETUPEND (0x0010) 200 #define USB_CSR0_P_DATAEND (0x0008) 201 #define USB_CSR0_P_SENTSTALL (0x0004) 202 203 /* CSR0 in Host mode */ 204 #define USB_CSR0_H_DIS_PING (0x0800) 205 #define USB_CSR0_H_WR_DATATOGGLE (0x0400) /* Set to allow setting: */ 206 #define USB_CSR0_H_DATATOGGLE (0x0200) /* Data toggle control */ 207 #define USB_CSR0_H_NAKTIMEOUT (0x0080) 208 #define USB_CSR0_H_STATUSPKT (0x0040) 209 #define USB_CSR0_H_REQPKT (0x0020) 210 #define USB_CSR0_H_ERROR (0x0010) 211 #define USB_CSR0_H_SETUPPKT (0x0008) 212 #define USB_CSR0_H_RXSTALL (0x0004) 213 214 215 /* DEVCTL */ 216 #define USB_DEVCTL_BDEVICE 0x80 217 #define USB_DEVCTL_FSDEV 0x40 218 #define USB_DEVCTL_LSDEV 0x20 219 #define USB_DEVCTL_VBUS 0x18 220 #define USB_DEVCTL_VBUS_SHIFT 3 221 #define USB_DEVCTL_HM 0x04 222 #define USB_DEVCTL_HR 0x02 223 #define USB_DEVCTL_SESSION 0x01 224 225 /* ULPI VBUSCONTROL */ 226 #define ULPI_USE_EXTVBUS 0x01 227 #define ULPI_USE_EXTVBUSIND 0x02 228 229 /* TESTMODE */ 230 #define USB_TEST_FORCE_HOST 0x80 231 #define USB_TEST_FIFO_ACCESS 0x40 232 #define USB_TEST_FORCE_FS 0x20 233 #define USB_TEST_FORCE_HS 0x10 234 #define USB_TEST_PACKET 0x08 235 #define USB_TEST_K 0x04 236 #define USB_TEST_J 0x02 237 #define USB_TEST_SE0_NAK 0x01 238 239 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ 240 #define USB_FIFOSZ_DPB 0x10 241 /* Allocation size (8, 16, 32, ... 4096) */ 242 #define USB_FIFOSZ_SIZE 0x0f 243 244 245 246 247 /* TxType/RxType */ 248 #define USB_TYPE_SPEED 0xc0 249 #define USB_TYPE_SPEED_SHIFT 6 250 #define USB_TYPE_SPEED_HIGH 1 251 #define USB_TYPE_SPEED_FULL 2 252 #define USB_TYPE_SPEED_LOW 3 253 #define USB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ 254 #define USB_TYPE_PROTO_SHIFT 4 255 #define USB_TYPE_PROTO_CTRL 0 256 #define USB_TYPE_PROTO_ISO 1 257 #define USB_TYPE_PROTO_BULK 2 258 #define USB_TYPE_PROTO_INTR 3 259 #define USB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ 260 261 /* CONFIGDATA */ 262 #define USB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ 263 #define USB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ 264 #define USB_CONFIGDATA_BIGENDIAN 0x20 /* Always 0 indicate Little Endian ordering.*/ 265 #define USB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ 266 #define USB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ 267 #define USB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ 268 #define USB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ 269 #define USB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ 270 271 #define USB_POWER_ISOUPDATE (BIT7) 272 #define USB_POWER_SOFTCONN (BIT6) 273 #define USB_POWER_HSENAB (BIT5) 274 #define USB_POWER_HSMODE (BIT4) 275 #define USB_POWER_RESET (BIT3) 276 #define USB_POWER_RESUME (BIT2) 277 #define USB_POWER_SUSPENDM (BIT1) 278 #define USB_POWER_ENSUSPEND (BIT0) 279 280 #define USB_INTR_VBUSERROR (BIT7) 281 #define USB_INTR_SESSREQ (BIT6) 282 #define USB_INTR_DISCONNECT (BIT5) 283 #define USB_INTR_CONNECT (BIT4) 284 #define USB_INTR_SOF (BIT3) 285 #define USB_INTR_BABBLE (BIT2) 286 #define USB_INTR_RESET (BIT2) 287 #define USB_INTR_RESUME (BIT1) 288 #define USB_INTR_SUSPEND (BIT0) 289 290 /* TXCSR in Peripheral and Host mode */ 291 #define USB_TXCSR_AUTOSET (0x8000) 292 #define USB_TXCSR_MODE (0x2000) 293 #define USB_TXCSR_DMAENAB (0x1000) 294 #define USB_TXCSR_FRCDATATOG (0x0800) 295 #define USB_TXCSR_DMAMODE (0x0400) 296 #define USB_TXCSR_CLRDATATOG (0x0040) 297 #define USB_TXCSR_FLUSHFIFO (0x0008) 298 #define USB_TXCSR_FIFONOTEMPTY (0x0002) 299 #define USB_TXCSR_TXPKTRDY (0x0001) 300 301 302 /* TXCSR in Peripheral mode */ 303 #define USB_TXCSR_P_ISO (0x4000) 304 #define USB_TXCSR_P_INCOMPTX (0x0080) 305 #define USB_TXCSR_P_SENTSTALL (0x0020) 306 #define USB_TXCSR_P_SENDSTALL (0x0010) 307 #define USB_TXCSR_P_UNDERRUN (0x0004) 308 309 /* TXCSR in Host mode */ 310 #define USB_TXCSR_H_WR_DATATOGGLE (0x0200) 311 #define USB_TXCSR_H_DATATOGGLE (0x0100) 312 #define USB_TXCSR_H_NAKTIMEOUT (0x0080) 313 #define USB_TXCSR_H_RXSTALL (0x0020) 314 #define USB_TXCSR_H_ERROR (0x0004) 315 316 317 #define USB_MAX_EP_NUM (16) 318 319 #define USB_MAX_EP_USED_NUM (2) 320 321 /* HUBADDR */ 322 #define USB_HUBADDR_MULTI_TT 0x80 323 324 //Usb intr mask 325 #define USBC_EP0_INTR_MASK (1<<0) 326 327 /* RXCSR in Peripheral and Host mode */ 328 #define USB_RXCSR_AUTOCLEAR (0x8000) 329 #define USB_RXCSR_DMAENAB (0x2000) 330 #define USB_RXCSR_DISNYET (0x1000) 331 #define USB_RXCSR_PID_ERR (0x1000) 332 #define USB_RXCSR_DMAMODE (0x0800) 333 #define USB_RXCSR_INCOMPRX (0x0100) 334 #define USB_RXCSR_CLRDATATOG (0x0080) 335 #define USB_RXCSR_FLUSHFIFO (0x0010) 336 #define USB_RXCSR_DATAERROR (0x0008) 337 #define USB_RXCSR_FIFOFULL (0x0002) 338 #define USB_RXCSR_RXPKTRDY (0x0001) 339 340 /* RXCSR in Peripheral mode */ 341 #define USB_RXCSR_P_ISO (0x4000) 342 #define USB_RXCSR_P_SENTSTALL (0x0040) 343 #define USB_RXCSR_P_SENDSTALL (0x0020) 344 #define USB_RXCSR_P_OVERRUN (0x0004) 345 346 /* RXCSR in Host mode */ 347 #define USB_RXCSR_H_AUTOREQ (0x4000) 348 #define USB_RXCSR_H_WR_DATATOGGLE (0x0400) 349 #define USB_RXCSR_H_DATATOGGLE (0x0200) 350 #define USB_RXCSR_H_RXSTALL (0x0040) 351 #define USB_RXCSR_H_REQPKT (0x0020) 352 #define USB_RXCSR_H_ERROR (0x0004) 353 354 355 356 357 /* DMA channel number 0 ~ 8 */ 358 #define USB_DMA_CHANNEL1 1 359 #define USB_DMA_CHANNEL2 2 360 #define USB_DMA_CHANNEL3 3 361 #define USB_DMA_CHANNEL4 4 362 #define USB_DMA_CHANNEL5 5 363 #define USB_DMA_CHANNEL6 6 364 #define USB_DMA_CHANNEL7 7 365 #define USB_DMA_CHANNEL8 8 366 367 /* Control register (16-bit) */ 368 #define USB_DMACTRL_ENABLE_SHIFT (0) 369 #define USB_DMACTRL_TRANSMIT_SHIFT (1) 370 #define USB_DMACTRL_MODE1_SHIFT (2) 371 #define USB_DMACTRL_IRQENABLE_SHIFT (3) 372 #define USB_DMACTRL_ENDPOINT_SHIFT (4) 373 #define USB_DMACTRL_BUSERROR_SHIFT (8) 374 #define USB_DMACTRL_BURSTMODE_SHIFT (9) 375 #define USB_DMACTRL_BURSTMODE (3 << USB_DMACTRL_BURSTMODE_SHIFT) 376 #define USB_DMACTRL_BURSTMODE_UNSPEC (0) 377 #define USB_DMACTRL_BURSTMODE_INCR4 (1) 378 #define USB_DMACTRL_BURSTMODE_INCR8 (2) 379 #define USB_DMACTRL_BURSTMODE_INCR16 (3) 380 381 /*Indicates pending DMA interrupts, one bit per DMA channel implemented*/ 382 #define USB_DMAINTR_MASK_CHAN1 (1<<0) 383 #define USB_DMAINTR_MASK_CHAN2 (1<<1) 384 #define USB_DMAINTR_MASK_CHAN3 (1<<2) 385 #define USB_DMAINTR_MASK_CHAN4 (1<<3) 386 #define USB_DMAINTR_MASK_CHAN5 (1<<4) 387 #define USB_DMAINTR_MASK_CHAN6 (1<<5) 388 #define USB_DMAINTR_MASK_CHAN7 (1<<6) 389 #define USB_DMAINTR_MASK_CHAN8 (1<<7) 390 391 392 393 #define USB_DMAADDR(n) (((n)&0x0FFFFFFF)<<0) 394 395 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ 396 #define USB_CSR0_P_WZC_BITS \ 397 (USB_CSR0_P_SENTSTALL) 398 399 #define USB_CSR0_H_WZC_BITS \ 400 (USB_CSR0_H_NAKTIMEOUT | USB_CSR0_H_RXSTALL \ 401 | USB_CSR0_RXPKTRDY) 402 403 404 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 405 #define USB_TXCSR_P_WZC_BITS \ 406 (USB_TXCSR_P_INCOMPTX | USB_TXCSR_P_SENTSTALL \ 407 | USB_TXCSR_P_UNDERRUN | USB_TXCSR_FIFONOTEMPTY) 408 #define USB_TXCSR_H_WZC_BITS \ 409 (USB_TXCSR_H_NAKTIMEOUT | USB_TXCSR_H_RXSTALL \ 410 | USB_TXCSR_H_ERROR | USB_TXCSR_FIFONOTEMPTY) 411 412 413 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 414 #define USB_RXCSR_P_WZC_BITS \ 415 (USB_RXCSR_P_SENTSTALL | USB_RXCSR_P_OVERRUN \ 416 | USB_RXCSR_RXPKTRDY) 417 #define USB_RXCSR_H_WZC_BITS \ 418 (USB_RXCSR_H_RXSTALL | USB_RXCSR_H_ERROR \ 419 | USB_RXCSR_DATAERROR | USB_RXCSR_RXPKTRDY) 420 421 422 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 423 #define USB_RXCSR_P_WZC_BITS \ 424 (USB_RXCSR_P_SENTSTALL | USB_RXCSR_P_OVERRUN \ 425 | USB_RXCSR_RXPKTRDY) 426 427 #define USB_RXCSR_H_WZC_BITS \ 428 (USB_RXCSR_H_RXSTALL | USB_RXCSR_H_ERROR \ 429 | USB_RXCSR_DATAERROR | USB_RXCSR_RXPKTRDY) 430 431 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 432 #define USB_TXCSR_P_WZC_BITS \ 433 (USB_TXCSR_P_INCOMPTX | USB_TXCSR_P_SENTSTALL \ 434 | USB_TXCSR_P_UNDERRUN | USB_TXCSR_FIFONOTEMPTY) 435 436 #define USB_TXCSR_H_WZC_BITS \ 437 (USB_TXCSR_H_NAKTIMEOUT | USB_TXCSR_H_RXSTALL \ 438 | USB_TXCSR_H_ERROR | USB_TXCSR_FIFONOTEMPTY) 439 440 441 #endif
