1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef _NRF5340_PERIPHERALS_H 36 #define _NRF5340_PERIPHERALS_H 37 38 39 /* Clock Peripheral */ 40 #define CLOCK_PRESENT 41 #define CLOCK_COUNT 1 42 43 #define CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT 44 45 /* Power Peripheral */ 46 #define POWER_PRESENT 47 #define POWER_COUNT 1 48 49 /* Non-Volatile Memory Controller */ 50 #define NVMC_PRESENT 51 #define NVMC_COUNT 1 52 53 /* NVM instruction and data cache */ 54 #define CACHE_PRESENT 55 #define CACHE_COUNT 1 56 57 /* Memory Protection Unit */ 58 #define MPU_REGION_NUM 8 59 60 /* Regulators Peripheral */ 61 #define REGULATORS_PRESENT 62 #define REGULATORS_COUNT 1 63 64 #define REGULATORS_FEATURE_VDDH_PRESENT 65 66 /* USB Regulator Peripheral */ 67 #define USBREG_PRESENT 68 #define USBREG_COUNT 1 69 70 /* Volatile Memory Controller Peripheral */ 71 #define VMC_PRESENT 72 #define VMC_COUNT 1 73 74 #define VMC_FEATURE_RAM_REGISTERS_PRESENT 75 #define VMC_FEATURE_RAM_REGISTERS_COUNT 8 76 77 /* Floating Point Unit */ 78 #define FPU_PRESENT 79 #define FPU_COUNT 1 80 81 /* Systick timer */ 82 #define SYSTICK_PRESENT 83 #define SYSTICK_COUNT 1 84 85 /* Inter-Processor Communication */ 86 #define IPC_PRESENT 87 #define IPC_COUNT 1 88 89 #define IPC_CH_NUM 16 90 #define IPC_CONF_NUM 16 91 #define IPC_GPMEM_NUM 2 92 93 /* GPIO */ 94 #define GPIO_PRESENT 95 #define GPIO_COUNT 2 96 97 #define P0_PIN_NUM 32 98 #define P1_PIN_NUM 16 99 100 #define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL 101 #define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL 102 103 /* NFC Tag */ 104 #define NFCT_PRESENT 105 #define NFCT_COUNT 1 106 107 #define NFCT_EASYDMA_MAXCNT_SIZE 9 108 109 /* Distributed Peripheral to Peripheral Interconnect */ 110 #define DPPIC_PRESENT 111 #define DPPIC_COUNT 1 112 113 #define DPPIC_CH_NUM 32 114 #define DPPIC_GROUP_NUM 6 115 116 /* Event Generator Unit */ 117 #define EGU_PRESENT 118 #define EGU_COUNT 6 119 120 #define EGU0_CH_NUM 16 121 #define EGU1_CH_NUM 16 122 #define EGU2_CH_NUM 16 123 #define EGU3_CH_NUM 16 124 #define EGU4_CH_NUM 16 125 #define EGU5_CH_NUM 16 126 127 /* Timer/Counter */ 128 #define TIMER_PRESENT 129 #define TIMER_COUNT 3 130 131 #define TIMER0_MAX_SIZE 32 132 #define TIMER1_MAX_SIZE 32 133 #define TIMER2_MAX_SIZE 32 134 135 #define TIMER0_CC_NUM 6 136 #define TIMER1_CC_NUM 6 137 #define TIMER2_CC_NUM 6 138 139 /* Real Time Counter */ 140 #define RTC_PRESENT 141 #define RTC_COUNT 2 142 143 #define RTC0_CC_NUM 4 144 #define RTC1_CC_NUM 4 145 146 /* Watchdog Timer */ 147 #define WDT_PRESENT 148 #define WDT_COUNT 2 149 150 /* Serial Peripheral Interface Master with DMA */ 151 #define SPIM_PRESENT 152 #define SPIM_COUNT 5 153 154 #define SPIM0_MAX_DATARATE 8 155 #define SPIM1_MAX_DATARATE 8 156 #define SPIM2_MAX_DATARATE 8 157 #define SPIM3_MAX_DATARATE 8 158 #define SPIM4_MAX_DATARATE 32 159 160 #define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 161 #define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 162 #define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0 163 #define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 0 164 #define SPIM4_FEATURE_HARDWARE_CSN_PRESENT 1 165 166 #define SPIM0_FEATURE_DCX_PRESENT 0 167 #define SPIM1_FEATURE_DCX_PRESENT 0 168 #define SPIM2_FEATURE_DCX_PRESENT 0 169 #define SPIM3_FEATURE_DCX_PRESENT 0 170 #define SPIM4_FEATURE_DCX_PRESENT 1 171 172 #define SPIM0_FEATURE_RXDELAY_PRESENT 0 173 #define SPIM1_FEATURE_RXDELAY_PRESENT 0 174 #define SPIM2_FEATURE_RXDELAY_PRESENT 0 175 #define SPIM3_FEATURE_RXDELAY_PRESENT 0 176 #define SPIM4_FEATURE_RXDELAY_PRESENT 1 177 178 #define SPIM0_EASYDMA_MAXCNT_SIZE 16 179 #define SPIM1_EASYDMA_MAXCNT_SIZE 16 180 #define SPIM2_EASYDMA_MAXCNT_SIZE 16 181 #define SPIM3_EASYDMA_MAXCNT_SIZE 16 182 #define SPIM4_EASYDMA_MAXCNT_SIZE 16 183 184 /* Serial Peripheral Interface Slave with DMA*/ 185 #define SPIS_PRESENT 186 #define SPIS_COUNT 4 187 188 #define SPIS0_EASYDMA_MAXCNT_SIZE 16 189 #define SPIS1_EASYDMA_MAXCNT_SIZE 16 190 #define SPIS2_EASYDMA_MAXCNT_SIZE 16 191 #define SPIS3_EASYDMA_MAXCNT_SIZE 16 192 193 /* Two Wire Interface Master with DMA */ 194 #define TWIM_PRESENT 195 #define TWIM_COUNT 4 196 197 #define TWIM0_EASYDMA_MAXCNT_SIZE 16 198 #define TWIM1_EASYDMA_MAXCNT_SIZE 16 199 #define TWIM2_EASYDMA_MAXCNT_SIZE 16 200 #define TWIM3_EASYDMA_MAXCNT_SIZE 16 201 202 /* Two Wire Interface Slave with DMA */ 203 #define TWIS_PRESENT 204 #define TWIS_COUNT 4 205 206 #define TWIS0_EASYDMA_MAXCNT_SIZE 16 207 #define TWIS1_EASYDMA_MAXCNT_SIZE 16 208 #define TWIS2_EASYDMA_MAXCNT_SIZE 16 209 #define TWIS3_EASYDMA_MAXCNT_SIZE 16 210 211 /* Universal Asynchronous Receiver-Transmitter with DMA */ 212 #define UARTE_PRESENT 213 #define UARTE_COUNT 4 214 215 #define UARTE0_EASYDMA_MAXCNT_SIZE 16 216 #define UARTE1_EASYDMA_MAXCNT_SIZE 16 217 #define UARTE2_EASYDMA_MAXCNT_SIZE 16 218 #define UARTE3_EASYDMA_MAXCNT_SIZE 16 219 220 /* Quadrature Decoder */ 221 #define QDEC_PRESENT 222 #define QDEC_COUNT 2 223 224 /* Successive Approximation Analog to Digital Converter */ 225 #define SAADC_PRESENT 226 #define SAADC_COUNT 1 227 228 #define SAADC_CH_NUM 8 229 #define SAADC_EASYDMA_MAXCNT_SIZE 15 230 231 /* GPIO Tasks and Events */ 232 #define GPIOTE_PRESENT 233 #define GPIOTE_COUNT 2 234 235 #define GPIOTE_CH_NUM 8 236 237 #define GPIOTE_FEATURE_SET_PRESENT 238 #define GPIOTE_FEATURE_CLR_PRESENT 239 240 /* Low Power Comparator */ 241 #define LPCOMP_PRESENT 242 #define LPCOMP_COUNT 1 243 244 #define LPCOMP_REFSEL_RESOLUTION 16 245 246 #define LPCOMP_FEATURE_HYST_PRESENT 247 248 /* Comparator */ 249 #define COMP_PRESENT 250 #define COMP_COUNT 1 251 252 /* Pulse Width Modulator */ 253 #define PWM_PRESENT 254 #define PWM_COUNT 4 255 256 #define PWM0_CH_NUM 4 257 #define PWM1_CH_NUM 4 258 #define PWM2_CH_NUM 4 259 #define PWM3_CH_NUM 4 260 261 #define PWM0_EASYDMA_MAXCNT_SIZE 15 262 #define PWM1_EASYDMA_MAXCNT_SIZE 15 263 #define PWM2_EASYDMA_MAXCNT_SIZE 15 264 #define PWM3_EASYDMA_MAXCNT_SIZE 15 265 266 267 /* Quad SPI */ 268 #define QSPI_PRESENT 269 #define QSPI_COUNT 1 270 271 #define QSPI_EASYDMA_MAXCNT_SIZE 20 272 273 /* Mutex*/ 274 #define MUTEX_PRESENT 275 #define MUTEX_COUNT 1 276 277 /* Key management Unit */ 278 #define KMU_PRESENT 279 #define KMU_COUNT 1 280 281 /* Pulse density modulation */ 282 #define PDM_PRESENT 283 #define PDM_COUNT 1 284 285 /* Secure Peripheral Unit */ 286 #define SPU_PRESENT 287 #define SPU_COUNT 1 288 289 #define SPU_RAMREGION_SIZE 0x2000ul 290 291 /* Inter-IC Sound Interface */ 292 #define I2S_PRESENT 293 #define I2S_COUNT 1 294 295 #define I2S_EASYDMA_MAXCNT_SIZE 14 296 297 /* Universal Serial Bus Device */ 298 #define USBD_PRESENT 299 #define USBD_COUNT 1 300 301 #define USBD_EASYDMA_MAXCNT_SIZE 7 302 303 /* Oscillators */ 304 #define OSCILLATORS_PRESENT 305 #define OSCILLATORS_COUNT 1 306 307 /*CRYPTOCELL register interface*/ 308 #define CRYPTOCELL_PRESENT 1 309 #define CRYPTOCELL_COUNT 1 310 #define CRYPTOCELL_VERSION 312 311 312 /*CRYPTOCELL AES engine*/ 313 #define CC_AES_PRESENT 1 314 #define CC_AES_COUNT 1 315 316 /*CRYPTOCELL AHB interface*/ 317 #define CC_AHB_PRESENT 1 318 #define CC_AHB_COUNT 1 319 320 /*CryptoCell AO*/ 321 #define CC_AO_PRESENT 1 322 #define CC_AO_COUNT 1 323 324 /*CRYPTOCELL CHACHA engine*/ 325 #define CC_CHACHA_PRESENT 1 326 #define CC_CHACHA_COUNT 1 327 328 /*CRYPTOCELL CTL interface*/ 329 #define CC_CTL_PRESENT 1 330 #define CC_CTL_COUNT 1 331 332 /*CRYPTOCELL Data IN interface*/ 333 #define CC_DIN_PRESENT 1 334 #define CC_DIN_COUNT 1 335 336 /*CRYPTOCELL Data OUT interface*/ 337 #define CC_DOUT_PRESENT 1 338 #define CC_DOUT_COUNT 1 339 340 /*CRYPTOCELL GHASH engine*/ 341 #define CC_GHASH_PRESENT 1 342 #define CC_GHASH_COUNT 1 343 344 /*CRYPTOCELL HASH engine*/ 345 #define CC_HASH_PRESENT 1 346 #define CC_HASH_COUNT 1 347 348 /*CRYPTOCELL HOST register interface*/ 349 #define CC_HOST_RGF_PRESENT 1 350 #define CC_HOST_RGF_COUNT 1 351 352 /*CRYPTOCELL MISC interface*/ 353 #define CC_MISC_PRESENT 1 354 #define CC_MISC_COUNT 1 355 356 /*CRYPTOCELL PKA engine*/ 357 #define CC_PKA_PRESENT 1 358 #define CC_PKA_COUNT 1 359 360 /*CRYPTOCELL RNG engine*/ 361 #define CC_RNG_PRESENT 1 362 #define CC_RNG_COUNT 1 363 364 /*CRYPTOCELL RNG SRAM interface*/ 365 #define CC_RNG_SRAM_PRESENT 1 366 #define CC_RNG_SRAM_COUNT 1 367 368 #endif // _NRF5340_PERIPHERALS_H 369
