1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2022 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7rsxx_ll_rcc.h"
23 #include "stm32h7rsxx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @addtogroup RCC_LL
37 * @{
38 */
39
40 /* Private variables ---------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Exported_Variables
42 * @{
43 */
44 const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
45
46 /**
47 * @}
48 */
49
50 /* Private types -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52 /* Private constants ---------------------------------------------------------*/
53 /* Private macros ------------------------------------------------------------*/
54 /** @addtogroup RCC_LL_Private_Macros
55 * @{
56 */
57 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ADC_CLKSOURCE)
58
59 #define IS_LL_RCC_ADF1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADF1_CLKSOURCE))
60
61 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
62
63 #define IS_LL_RCC_CLKP_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CLKP_CLKSOURCE))
64
65 #define IS_LL_RCC_ETH1PHY_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ETH1PHY_CLKSOURCE))
66
67 #define IS_LL_RCC_ETHREF_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ETHREF_CLKSOURCE))
68
69 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
70
71 #define IS_LL_RCC_FMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FMC_CLKSOURCE))
72
73 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
74 || ((__VALUE__) == LL_RCC_I2C23_CLKSOURCE))
75
76 #define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I3C1_CLKSOURCE)
77
78 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
79 || ((__VALUE__) == LL_RCC_LPTIM23_CLKSOURCE) \
80 || ((__VALUE__) == LL_RCC_LPTIM45_CLKSOURCE))
81
82 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)
83
84 #define IS_LL_RCC_PSSI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_PSSI_CLKSOURCE)
85
86 #define IS_LL_RCC_RTC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_RTC_CLKSOURCE)
87
88 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
89 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
90
91 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SDMMC_CLKSOURCE)
92
93 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
94 || ((__VALUE__) == LL_RCC_SPI23_CLKSOURCE) \
95 || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
96 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
97
98 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX_CLKSOURCE))
99
100 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
101 || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
102
103 #define IS_LL_RCC_XSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_XSPI1_CLKSOURCE) \
104 || ((__VALUE__) == LL_RCC_XSPI2_CLKSOURCE))
105
106 #define IS_LL_RCC_USBPHYC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USBPHYC_CLKSOURCE))
107
108 #define IS_LL_RCC_OTGFS_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OTGFS_CLKSOURCE))
109
110 /**
111 * @}
112 */
113
114 /* Private function prototypes -----------------------------------------------*/
115 /** @defgroup RCC_LL_Private_Functions RCC Private functions
116 * @{
117 */
118 static uint32_t RCC_GetSystemClockFreq(void);
119 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
120 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
121 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
122 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
123 static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency);
124
125 /**
126 * @}
127 */
128
129
130 /* Exported functions --------------------------------------------------------*/
131 /** @addtogroup RCC_LL_Exported_Functions
132 * @{
133 */
134
135 /** @addtogroup RCC_LL_EF_Init
136 * @{
137 */
138
139 /**
140 * @brief Resets the RCC clock configuration to the default reset state.
141 * @note The default reset state of the clock configuration is given below:
142 * - HSI ON and used as system clock source
143 * - HSE, PLL1, PLL2 and PLL3 OFF
144 * - AHB, APB Bus pre-scaler set to 1.
145 * - CSS, MCO1 and MCO2 OFF
146 * - All interrupts disabled
147 * @note This function doesn't modify the configuration of the
148 * - Peripheral clocks
149 * - LSI, LSE and RTC clocks
150 * @note In case the FMC or XSPI clock protection have been set, it must be disabled
151 * prior to calling this API.
152 * @warning FLASH latency must be adjusted according to the targeted system clock
153 * frequency and voltage scaling.
154 * @retval None
155 */
LL_RCC_DeInit(void)156 void LL_RCC_DeInit(void)
157 {
158 /* Increasing the CPU frequency */
159 if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
160 {
161 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
162 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
163 }
164
165 /* Set HSION bit */
166 SET_BIT(RCC->CR, RCC_CR_HSION);
167
168 /* Wait for HSI READY bit */
169 while (LL_RCC_HSI_IsReady() == 0U)
170 {}
171
172 /* Reset CFGR register to select HSI as system clock */
173 CLEAR_REG(RCC->CFGR);
174
175 /* Reset CSION, CSIKERON, HSEON, HSEEXT, HSI48ON, HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
176 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEEXT | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_CSION | RCC_CR_CSIKERON | \
177 RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
178
179 /* Wait for PLL1 READY bit to be reset */
180 while (LL_RCC_PLL1_IsReady() != 0U)
181 {}
182
183 /* Wait for PLL2 READY bit to be reset */
184 while (LL_RCC_PLL2_IsReady() != 0U)
185 {}
186
187 /* Wait for PLL3 READY bit to be reset */
188 while (LL_RCC_PLL3_IsReady() != 0U)
189 {}
190
191 /* Reset CDCFGR register */
192 CLEAR_REG(RCC->CDCFGR);
193
194 /* Reset BMCFGR register */
195 CLEAR_REG(RCC->BMCFGR);
196
197 /* Reset APBCFGR register */
198 CLEAR_REG(RCC->APBCFGR);
199
200 /* Reset PLLCKSELR register to default value */
201 LL_RCC_WriteReg(PLLCKSELR, \
202 (32U << RCC_PLLCKSELR_DIVM1_Pos) | (32U << RCC_PLLCKSELR_DIVM2_Pos) | (32U << RCC_PLLCKSELR_DIVM3_Pos));
203
204 /* Reset PLLCFGR register to default value */
205 LL_RCC_WriteReg(PLLCFGR, 0U);
206
207 /* Reset PLL1DIVR1/PLL1DIVR2 registers to default value */
208 LL_RCC_WriteReg(PLL1DIVR1, 0x01010280U);
209 LL_RCC_WriteReg(PLL1DIVR2, 0x00000101U);
210
211 /* Reset PLL1FRACR register */
212 CLEAR_REG(RCC->PLL1FRACR);
213
214 /* Reset PLL2DIVR1/PLL2DIVR2 registers to default value */
215 LL_RCC_WriteReg(PLL2DIVR1, 0x01010280U);
216 LL_RCC_WriteReg(PLL2DIVR2, 0x00000101U);
217
218 /* Reset PLL2FRACR register */
219 CLEAR_REG(RCC->PLL2FRACR);
220
221 /* Reset PLL2DIVR1/PLL2DIVR2 registers to default value */
222 LL_RCC_WriteReg(PLL2DIVR1, 0x01010280U);
223 LL_RCC_WriteReg(PLL2DIVR2, 0x00000101U);
224
225 /* Reset PLL3FRACR register */
226 CLEAR_REG(RCC->PLL3FRACR);
227
228 /* Reset HSEBYP bit */
229 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
230
231 /* Disable all interrupts */
232 CLEAR_REG(RCC->CIER);
233
234 /* Clear all interrupts */
235 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \
236 RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | \
237 RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
238
239 /* Clear reset source flags */
240 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
241
242 /* Decreasing the number of wait states because of lower CPU frequency */
243 if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
244 {
245 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
246 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
247 }
248 }
249
250 /**
251 * @}
252 */
253
254 /** @addtogroup RCC_LL_EF_Get_Freq
255 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
256 * and different peripheral clocks available on the device.
257 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
258 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
259 * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
260 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
261 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
262 * @note (*) HSI_VALUE is a constant defined in header file (default value
263 * 64 MHz) divider by HSIDIV, but the real value may vary depending on
264 * on the variations in voltage and temperature.
265 * @note (**) HSE_VALUE is a constant defined in header file (default value
266 * 24 MHz), user has to ensure that HSE_VALUE is same as the real
267 * frequency of the crystal used. Otherwise, this function may
268 * have wrong result.
269 * @note (***) CSI_VALUE is a constant defined in header file (default value
270 * 4 MHz) but the real value may vary depending on the variations
271 * in voltage and temperature.
272 * @note The result of this function could be incorrect when using fractional
273 * value for HSE crystal.
274 * @note This function can be used by the user application to compute the
275 * baud-rate for the communication peripherals or configure other parameters.
276 * @{
277 */
278
279 /**
280 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB4 and APB5 buses clocks.
281 * @note Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK4 and/or PCLK5 clock changes, this function
282 * must be called to update structure fields. Otherwise, any
283 * configuration based on this function will be incorrect.
284 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
285 * @retval None
286 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)287 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
288 {
289 /* Get SYSCLK frequency */
290 RCC_Clocks->SYSCLK_Frequency = LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler());
291
292 /* HCLK clock frequency */
293 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
294
295 /* PCLK1 clock frequency */
296 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
297
298 /* PCLK2 clock frequency */
299 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
300
301 /* PCLK4 clock frequency */
302 RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
303
304 /* PCLK5 clock frequency */
305 RCC_Clocks->PCLK5_Frequency = RCC_GetPCLK5ClockFreq(RCC_Clocks->HCLK_Frequency);
306 }
307
308 /**
309 * @brief Return PLL1 clocks frequencies
310 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
311 * @retval None
312 */
LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)313 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
314 {
315 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
316 uint32_t m, n, fracn = 0U;
317
318 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
319 SYSCLK = PLL_VCO / PLLP
320 */
321 pllsource = LL_RCC_PLL_GetSource();
322
323 switch (pllsource)
324 {
325 case LL_RCC_PLLSOURCE_HSI:
326 if (LL_RCC_HSI_IsReady() != 0U)
327 {
328 if (LL_RCC_HSI_IsDividerReady() != 0U)
329 {
330 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
331 }
332 }
333 break;
334
335 case LL_RCC_PLLSOURCE_CSI:
336 if (LL_RCC_CSI_IsReady() != 0U)
337 {
338 pllinputfreq = CSI_VALUE;
339 }
340 break;
341
342 case LL_RCC_PLLSOURCE_HSE:
343 if (LL_RCC_HSE_IsReady() != 0U)
344 {
345 pllinputfreq = HSE_VALUE;
346 }
347 break;
348
349 case LL_RCC_PLLSOURCE_NONE:
350 default:
351 /* PLL clock disabled */
352 break;
353 }
354
355 PLL_Clocks->PLL_P_Frequency = 0U;
356 PLL_Clocks->PLL_Q_Frequency = 0U;
357 PLL_Clocks->PLL_R_Frequency = 0U;
358 PLL_Clocks->PLL_S_Frequency = 0U;
359 PLL_Clocks->PLL_T_Frequency = 0U;
360
361 m = LL_RCC_PLL1_GetM();
362 n = LL_RCC_PLL1_GetN();
363 if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
364 {
365 fracn = LL_RCC_PLL1_GetFRACN();
366 }
367
368 if (m != 0U)
369 {
370 if (LL_RCC_PLL1P_IsEnabled() != 0U)
371 {
372 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
373 }
374
375 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
376 {
377 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
378 }
379
380 if (LL_RCC_PLL1R_IsEnabled() != 0U)
381 {
382 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
383 }
384
385 if (LL_RCC_PLL1S_IsEnabled() != 0U)
386 {
387 PLL_Clocks->PLL_S_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetS());
388 }
389 }
390 }
391
392 /**
393 * @brief Return PLL2 clocks frequencies
394 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
395 * @retval None
396 */
LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)397 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
398 {
399 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
400 uint32_t m, n, fracn = 0U;
401
402 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
403 SYSCLK = PLL_VCO / PLLP
404 */
405 pllsource = LL_RCC_PLL_GetSource();
406
407 switch (pllsource)
408 {
409 case LL_RCC_PLLSOURCE_HSI:
410 if (LL_RCC_HSI_IsReady() != 0U)
411 {
412 if (LL_RCC_HSI_IsDividerReady() != 0U)
413 {
414 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
415 }
416 }
417 break;
418
419 case LL_RCC_PLLSOURCE_CSI:
420 if (LL_RCC_CSI_IsReady() != 0U)
421 {
422 pllinputfreq = CSI_VALUE;
423 }
424 break;
425
426 case LL_RCC_PLLSOURCE_HSE:
427 if (LL_RCC_HSE_IsReady() != 0U)
428 {
429 pllinputfreq = HSE_VALUE;
430 }
431 break;
432
433 case LL_RCC_PLLSOURCE_NONE:
434 default:
435 /* PLL clock disabled */
436 break;
437 }
438
439 PLL_Clocks->PLL_P_Frequency = 0U;
440 PLL_Clocks->PLL_Q_Frequency = 0U;
441 PLL_Clocks->PLL_R_Frequency = 0U;
442 PLL_Clocks->PLL_S_Frequency = 0U;
443 PLL_Clocks->PLL_T_Frequency = 0U;
444
445 m = LL_RCC_PLL2_GetM();
446 n = LL_RCC_PLL2_GetN();
447 if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
448 {
449 fracn = LL_RCC_PLL2_GetFRACN();
450 }
451
452 if (m != 0U)
453 {
454 if (LL_RCC_PLL2P_IsEnabled() != 0U)
455 {
456 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
457 }
458
459 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
460 {
461 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
462 }
463
464 if (LL_RCC_PLL2R_IsEnabled() != 0U)
465 {
466 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
467 }
468
469 if (LL_RCC_PLL2S_IsEnabled() != 0U)
470 {
471 PLL_Clocks->PLL_S_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetS());
472 }
473
474 if (LL_RCC_PLL2T_IsEnabled() != 0U)
475 {
476 PLL_Clocks->PLL_T_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetT());
477 }
478 }
479 }
480
481 /**
482 * @brief Return PLL3 clocks frequencies
483 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
484 * @retval None
485 */
LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)486 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
487 {
488 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
489 uint32_t m, n, fracn = 0U;
490
491 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
492 SYSCLK = PLL_VCO / PLLP
493 */
494 pllsource = LL_RCC_PLL_GetSource();
495
496 switch (pllsource)
497 {
498 case LL_RCC_PLLSOURCE_HSI:
499 if (LL_RCC_HSI_IsReady() != 0U)
500 {
501 if (LL_RCC_HSI_IsDividerReady() != 0U)
502 {
503 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
504 }
505 }
506 break;
507
508 case LL_RCC_PLLSOURCE_CSI:
509 if (LL_RCC_CSI_IsReady() != 0U)
510 {
511 pllinputfreq = CSI_VALUE;
512 }
513 break;
514
515 case LL_RCC_PLLSOURCE_HSE:
516 if (LL_RCC_HSE_IsReady() != 0U)
517 {
518 pllinputfreq = HSE_VALUE;
519 }
520 break;
521
522 case LL_RCC_PLLSOURCE_NONE:
523 default:
524 /* PLL clock disabled */
525 break;
526 }
527
528 PLL_Clocks->PLL_P_Frequency = 0U;
529 PLL_Clocks->PLL_Q_Frequency = 0U;
530 PLL_Clocks->PLL_R_Frequency = 0U;
531 PLL_Clocks->PLL_S_Frequency = 0U;
532 PLL_Clocks->PLL_T_Frequency = 0U;
533
534 m = LL_RCC_PLL3_GetM();
535 n = LL_RCC_PLL3_GetN();
536 if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
537 {
538 fracn = LL_RCC_PLL3_GetFRACN();
539 }
540
541 if ((m != 0U) && (pllinputfreq != 0U))
542 {
543 if (LL_RCC_PLL3P_IsEnabled() != 0U)
544 {
545 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
546 }
547
548 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
549 {
550 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
551 }
552
553 if (LL_RCC_PLL3R_IsEnabled() != 0U)
554 {
555 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
556 }
557
558 if (LL_RCC_PLL3S_IsEnabled() != 0U)
559 {
560 PLL_Clocks->PLL_S_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetS());
561 }
562 }
563 }
564
565 /**
566 * @brief Configure Spread Spectrum used for PLL1
567 * @note These bits must be written before enabling PLL1
568 * @note MODPER x INCSTEP shall not exceed 2^15-1
569 * @rmtoll PLL1SSCGR MODPER LL_RCC_PLL1_ConfigSpreadSpectrum\n
570 * PLL1SSCGR INCSTEP LL_RCC_PLL1_ConfigSpreadSpectrum\n
571 * PLL1SSCGR SPREADSEL LL_RCC_PLL1_ConfigSpreadSpectrum\n
572 * PLL1SSCGR TPDFNDIS LL_RCC_PLL1_ConfigSpreadSpectrum\n
573 * PLL1SSCGR RPDFNDIS LL_RCC_PLL1_ConfigSpreadSpectrum
574 * @param pConfig Pointer to LL_PLL_SpreadSpectrumTypeDef structure
575 * @retval None
576 */
LL_RCC_PLL1_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef * pConfig)577 void LL_RCC_PLL1_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig)
578 {
579 MODIFY_REG(RCC->PLL1SSCGR, \
580 (RCC_PLL1SSCGR_MODPER | RCC_PLL1SSCGR_INCSTEP | RCC_PLL1SSCGR_SPREADSEL | \
581 RCC_PLL1SSCGR_TPDFNDIS | RCC_PLL1SSCGR_RPDFNDIS), \
582 (pConfig->ModulationPeriod | ((uint32_t)pConfig->IncrementStep << RCC_PLL1SSCGR_INCSTEP_Pos) | \
583 pConfig->SpreadMode | pConfig->DitheringTPDFN | pConfig->DitheringRPDFN));
584 }
585
586 /**
587 * @brief Configure Spread Spectrum used for PLL2
588 * @note These bits must be written before enabling PLL2
589 * @rmtoll PLL2SSCGR MODPER LL_RCC_PLL2_ConfigSpreadSpectrum\n
590 * PLL2SSCGR INCSTEP LL_RCC_PLL2_ConfigSpreadSpectrum\n
591 * PLL2SSCGR SPREADSEL LL_RCC_PLL2_ConfigSpreadSpectrum\n
592 * PLL2SSCGR TPDFNDIS LL_RCC_PLL2_ConfigSpreadSpectrum\n
593 * PLL2SSCGR RPDFNDIS LL_RCC_PLL2_ConfigSpreadSpectrum
594 * @param pConfig Pointer to LL_PLL_SpreadSpectrumTypeDef structure
595 * @retval None
596 */
LL_RCC_PLL2_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef * pConfig)597 void LL_RCC_PLL2_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig)
598 {
599 MODIFY_REG(RCC->PLL2SSCGR, \
600 (RCC_PLL2SSCGR_MODPER | RCC_PLL2SSCGR_INCSTEP | RCC_PLL2SSCGR_SPREADSEL | \
601 RCC_PLL2SSCGR_TPDFNDIS | RCC_PLL2SSCGR_RPDFNDIS), \
602 (pConfig->ModulationPeriod | ((uint32_t)pConfig->IncrementStep << RCC_PLL2SSCGR_INCSTEP_Pos) | \
603 pConfig->SpreadMode | pConfig->DitheringTPDFN | pConfig->DitheringRPDFN));
604 }
605
606 /**
607 * @brief Configure Spread Spectrum used for PLL3
608 * @note These bits must be written before enabling PLL3
609 * @rmtoll PLL3SSCGR MODPER LL_RCC_PLL3_ConfigSpreadSpectrum\n
610 * PLL3SSCGR INCSTEP LL_RCC_PLL3_ConfigSpreadSpectrum\n
611 * PLL3SSCGR SPREADSEL LL_RCC_PLL3_ConfigSpreadSpectrum\n
612 * PLL3SSCGR TPDFNDIS LL_RCC_PLL3_ConfigSpreadSpectrum\n
613 * PLL3SSCGR RPDFNDIS LL_RCC_PLL3_ConfigSpreadSpectrum
614 * @param pConfig Pointer to LL_PLL_SpreadSpectrumTypeDef structure
615 * @retval None
616 */
LL_RCC_PLL3_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef * pConfig)617 void LL_RCC_PLL3_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig)
618 {
619 MODIFY_REG(RCC->PLL3SSCGR, \
620 (RCC_PLL3SSCGR_MODPER | RCC_PLL3SSCGR_INCSTEP | RCC_PLL3SSCGR_SPREADSEL | \
621 RCC_PLL3SSCGR_TPDFNDIS | RCC_PLL3SSCGR_RPDFNDIS), \
622 (pConfig->ModulationPeriod | ((uint32_t)pConfig->IncrementStep << RCC_PLL3SSCGR_INCSTEP_Pos) | \
623 pConfig->SpreadMode | pConfig->DitheringTPDFN | pConfig->DitheringRPDFN));
624 }
625
626
627 /**
628 * @brief Return USARTx clock frequency
629 * @param USARTxSource This parameter can be one of the following values:
630 * @arg @ref LL_RCC_USART1_CLKSOURCE
631 * @arg @ref LL_RCC_USART234578_CLKSOURCE
632 * @retval USART clock frequency (in Hz)
633 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
634 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)635 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
636 {
637 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
638 LL_PLL_ClocksTypeDef PLL_Clocks;
639
640 /* Check parameter */
641 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
642
643 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
644 {
645 case LL_RCC_USART1_CLKSOURCE_PCLK2:
646 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
647 break;
648
649 case LL_RCC_USART234578_CLKSOURCE_PCLK1:
650 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
651 break;
652
653 case LL_RCC_USART1_CLKSOURCE_PLL2Q:
654 case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
655 if (LL_RCC_PLL2_IsReady() != 0U)
656 {
657 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
658 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
659 }
660 break;
661
662 case LL_RCC_USART1_CLKSOURCE_PLL3Q:
663 case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
664 if (LL_RCC_PLL3_IsReady() != 0U)
665 {
666 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
667 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
668 }
669 break;
670
671 case LL_RCC_USART1_CLKSOURCE_HSI:
672 case LL_RCC_USART234578_CLKSOURCE_HSI:
673 if (LL_RCC_HSI_IsReady() != 0U)
674 {
675 if (LL_RCC_HSI_IsDividerReady() != 0U)
676 {
677 usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
678 }
679 }
680 break;
681
682 case LL_RCC_USART1_CLKSOURCE_CSI:
683 case LL_RCC_USART234578_CLKSOURCE_CSI:
684 if (LL_RCC_CSI_IsReady() != 0U)
685 {
686 usart_frequency = CSI_VALUE;
687 }
688 break;
689
690 case LL_RCC_USART1_CLKSOURCE_LSE:
691 case LL_RCC_USART234578_CLKSOURCE_LSE:
692 if (LL_RCC_LSE_IsReady() != 0U)
693 {
694 usart_frequency = LSE_VALUE;
695 }
696 break;
697
698 default:
699 /* Kernel clock disabled */
700 break;
701 }
702
703 return usart_frequency;
704 }
705
706 /**
707 * @brief Return UARTx clock frequency
708 * @param UARTxSource This parameter can be one of the following values:
709 * @arg @ref LL_RCC_USART234578_CLKSOURCE
710 * @retval USART clock frequency (in Hz)
711 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
712 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)713 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
714 {
715 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
716 LL_PLL_ClocksTypeDef PLL_Clocks;
717
718 /* Check parameter */
719 assert_param(IS_LL_RCC_USART_CLKSOURCE(UARTxSource));
720
721 switch (LL_RCC_GetUSARTClockSource(UARTxSource))
722 {
723 case LL_RCC_USART234578_CLKSOURCE_PCLK1:
724 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
725 break;
726
727 case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
728 if (LL_RCC_PLL2_IsReady() != 0U)
729 {
730 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
731 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
732 }
733 break;
734
735 case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
736 if (LL_RCC_PLL3_IsReady() != 0U)
737 {
738 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
739 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
740 }
741 break;
742
743 case LL_RCC_USART234578_CLKSOURCE_HSI:
744 if (LL_RCC_HSI_IsReady() != 0U)
745 {
746 if (LL_RCC_HSI_IsDividerReady() != 0U)
747 {
748 uart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
749 }
750 }
751 break;
752
753 case LL_RCC_USART234578_CLKSOURCE_CSI:
754 if (LL_RCC_CSI_IsReady() != 0U)
755 {
756 uart_frequency = CSI_VALUE;
757 }
758 break;
759
760 case LL_RCC_USART234578_CLKSOURCE_LSE:
761 if (LL_RCC_LSE_IsReady() != 0U)
762 {
763 uart_frequency = LSE_VALUE;
764 }
765 break;
766
767 default:
768 /* Kernel clock disabled */
769 break;
770 }
771
772 return uart_frequency;
773 }
774
775 /**
776 * @brief Return LPUART clock frequency
777 * @param LPUARTxSource This parameter can be one of the following values:
778 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
779 * @retval LPUART clock frequency (in Hz)
780 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
781 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)782 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
783 {
784 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
785 LL_PLL_ClocksTypeDef PLL_Clocks;
786
787 /* Check parameter */
788 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
789
790 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
791 {
792 case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
793 lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
794 break;
795
796 case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
797 if (LL_RCC_PLL2_IsReady() != 0U)
798 {
799 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
800 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
801 }
802 break;
803
804 case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
805 if (LL_RCC_PLL3_IsReady() != 0U)
806 {
807 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
808 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
809 }
810 break;
811
812 case LL_RCC_LPUART1_CLKSOURCE_HSI:
813 if (LL_RCC_HSI_IsReady() != 0U)
814 {
815 if (LL_RCC_HSI_IsDividerReady() != 0U)
816 {
817 lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
818 }
819 }
820 break;
821
822 case LL_RCC_LPUART1_CLKSOURCE_CSI:
823 if (LL_RCC_CSI_IsReady() != 0U)
824 {
825 lpuart_frequency = CSI_VALUE;
826 }
827 break;
828
829 case LL_RCC_LPUART1_CLKSOURCE_LSE:
830 if (LL_RCC_LSE_IsReady() != 0U)
831 {
832 lpuart_frequency = LSE_VALUE;
833 }
834 break;
835
836 default:
837 /* Kernel clock disabled */
838 break;
839 }
840
841 return lpuart_frequency;
842 }
843
844 /**
845 * @brief Return I2Cx clock frequency
846 * @param I2CxSource This parameter can be one of the following values:
847 * @arg @ref LL_RCC_I2C1_CLKSOURCE
848 * @arg @ref LL_RCC_I2C23_CLKSOURCE
849 * @retval I2C clock frequency (in Hz)
850 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
851 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)852 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
853 {
854 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
855 LL_PLL_ClocksTypeDef PLL_Clocks;
856
857 /* Check parameter */
858 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
859
860 switch (LL_RCC_GetI2CClockSource(I2CxSource))
861 {
862 case LL_RCC_I2C1_CLKSOURCE_PCLK1:
863 case LL_RCC_I2C23_CLKSOURCE_PCLK1:
864 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
865 break;
866
867 case LL_RCC_I2C1_CLKSOURCE_PLL3R:
868 case LL_RCC_I2C23_CLKSOURCE_PLL3R:
869 if (LL_RCC_PLL3_IsReady() != 0U)
870 {
871 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
872 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
873 }
874 break;
875
876 case LL_RCC_I2C1_CLKSOURCE_HSI:
877 case LL_RCC_I2C23_CLKSOURCE_HSI:
878 if (LL_RCC_HSI_IsReady() != 0U)
879 {
880 if (LL_RCC_HSI_IsDividerReady() != 0U)
881 {
882 i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
883 }
884 }
885 break;
886
887 case LL_RCC_I2C1_CLKSOURCE_CSI:
888 case LL_RCC_I2C23_CLKSOURCE_CSI:
889 if (LL_RCC_CSI_IsReady() != 0U)
890 {
891 i2c_frequency = CSI_VALUE;
892 }
893 break;
894
895 default:
896 /* Nothing to do */
897 break;
898 }
899
900 return i2c_frequency;
901 }
902
903 /**
904 * @brief Return I3Cx clock frequency
905 * @param I3CxSource This parameter can be one of the following values:
906 * @arg @ref LL_RCC_I3C1_CLKSOURCE
907 * @retval I3C clock frequency (in Hz)
908 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
909 */
LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)910 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)
911 {
912 uint32_t i3c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
913 LL_PLL_ClocksTypeDef PLL_Clocks;
914
915 /* Check parameter */
916 assert_param(IS_LL_RCC_I3C_CLKSOURCE(I3CxSource));
917
918 switch (LL_RCC_GetI3CClockSource(I3CxSource))
919 {
920 case LL_RCC_I3C1_CLKSOURCE_PCLK1:
921 i3c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
922 break;
923
924 case LL_RCC_I3C1_CLKSOURCE_PLL3R:
925 if (LL_RCC_PLL3_IsReady() != 0U)
926 {
927 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
928 i3c_frequency = PLL_Clocks.PLL_R_Frequency;
929 }
930 break;
931
932 case LL_RCC_I3C1_CLKSOURCE_HSI:
933 if (LL_RCC_HSI_IsReady() != 0U)
934 {
935 if (LL_RCC_HSI_IsDividerReady() != 0U)
936 {
937 i3c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
938 }
939 }
940 break;
941
942 case LL_RCC_I3C1_CLKSOURCE_CSI:
943 if (LL_RCC_CSI_IsReady() != 0U)
944 {
945 i3c_frequency = CSI_VALUE;
946 }
947 break;
948
949 default:
950 /* Nothing to do */
951 break;
952 }
953
954 return i3c_frequency;
955 }
956
957 /**
958 * @brief Return LPTIMx clock frequency
959 * @param LPTIMxSource This parameter can be one of the following values:
960 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
961 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE
962 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE
963 * @retval LPTIM clock frequency (in Hz)
964 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
965 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)966 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
967 {
968 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
969 LL_PLL_ClocksTypeDef PLL_Clocks;
970
971 /* Check parameter */
972 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
973
974 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
975 {
976 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
977 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
978 break;
979
980 case LL_RCC_LPTIM23_CLKSOURCE_PCLK4:
981 case LL_RCC_LPTIM45_CLKSOURCE_PCLK4:
982 lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
983 break;
984
985 case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
986 case LL_RCC_LPTIM23_CLKSOURCE_PLL2P:
987 case LL_RCC_LPTIM45_CLKSOURCE_PLL2P:
988 if (LL_RCC_PLL2_IsReady() != 0U)
989 {
990 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
991 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
992 }
993 break;
994
995 case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
996 case LL_RCC_LPTIM23_CLKSOURCE_PLL3R:
997 case LL_RCC_LPTIM45_CLKSOURCE_PLL3R:
998 if (LL_RCC_PLL3_IsReady() != 0U)
999 {
1000 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1001 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
1002 }
1003 break;
1004
1005 case LL_RCC_LPTIM1_CLKSOURCE_LSE:
1006 case LL_RCC_LPTIM23_CLKSOURCE_LSE:
1007 case LL_RCC_LPTIM45_CLKSOURCE_LSE:
1008 if (LL_RCC_LSE_IsReady() != 0U)
1009 {
1010 lptim_frequency = LSE_VALUE;
1011 }
1012 break;
1013
1014 case LL_RCC_LPTIM1_CLKSOURCE_LSI:
1015 case LL_RCC_LPTIM23_CLKSOURCE_LSI:
1016 case LL_RCC_LPTIM45_CLKSOURCE_LSI:
1017 if (LL_RCC_LSI_IsReady() != 0U)
1018 {
1019 lptim_frequency = LSI_VALUE;
1020 }
1021 break;
1022
1023 case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
1024 case LL_RCC_LPTIM23_CLKSOURCE_CLKP:
1025 case LL_RCC_LPTIM45_CLKSOURCE_CLKP:
1026 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1027 break;
1028
1029 default:
1030 /* Kernel clock disabled */
1031 break;
1032 }
1033
1034 return lptim_frequency;
1035 }
1036
1037 /**
1038 * @brief Return SAIx clock frequency
1039 * @param SAIxSource This parameter can be one of the following values:
1040 * @arg @ref LL_RCC_SAI1_CLKSOURCE
1041 * @arg @ref LL_RCC_SAI2_CLKSOURCE
1042 * @retval SAI clock frequency (in Hz)
1043 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1044 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)1045 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
1046 {
1047 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1048 LL_PLL_ClocksTypeDef PLL_Clocks;
1049
1050 /* Check parameter */
1051 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
1052
1053 switch (LL_RCC_GetSAIClockSource(SAIxSource))
1054 {
1055 case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
1056 case LL_RCC_SAI2_CLKSOURCE_PLL1Q:
1057 if (LL_RCC_PLL1_IsReady() != 0U)
1058 {
1059 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1060 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
1061 }
1062 break;
1063
1064 case LL_RCC_SAI1_CLKSOURCE_PLL2P:
1065 case LL_RCC_SAI2_CLKSOURCE_PLL2P:
1066 if (LL_RCC_PLL2_IsReady() != 0U)
1067 {
1068 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1069 sai_frequency = PLL_Clocks.PLL_P_Frequency;
1070 }
1071 break;
1072
1073 case LL_RCC_SAI1_CLKSOURCE_PLL3P:
1074 case LL_RCC_SAI2_CLKSOURCE_PLL3P:
1075 if (LL_RCC_PLL3_IsReady() != 0U)
1076 {
1077 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1078 sai_frequency = PLL_Clocks.PLL_P_Frequency;
1079 }
1080 break;
1081
1082 case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
1083 case LL_RCC_SAI2_CLKSOURCE_I2S_CKIN:
1084 sai_frequency = EXTERNAL_CLOCK_VALUE;
1085 break;
1086
1087 case LL_RCC_SAI1_CLKSOURCE_CLKP:
1088 case LL_RCC_SAI2_CLKSOURCE_CLKP:
1089 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1090 break;
1091
1092 default:
1093 /* Kernel clock disabled */
1094 break;
1095 }
1096
1097 return sai_frequency;
1098 }
1099
1100 /**
1101 * @brief Return ADC clock frequency
1102 * @param ADCxSource This parameter can be one of the following values:
1103 * @arg @ref LL_RCC_ADC_CLKSOURCE
1104 * @retval ADC clock frequency (in Hz)
1105 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1106 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)1107 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
1108 {
1109 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1110 LL_PLL_ClocksTypeDef PLL_Clocks;
1111
1112 /* Check parameter */
1113 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
1114
1115 switch (LL_RCC_GetADCClockSource(ADCxSource))
1116 {
1117 case LL_RCC_ADC_CLKSOURCE_PLL2P:
1118 if (LL_RCC_PLL2_IsReady() != 0U)
1119 {
1120 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1121 adc_frequency = PLL_Clocks.PLL_P_Frequency;
1122 }
1123 break;
1124
1125 case LL_RCC_ADC_CLKSOURCE_PLL3R:
1126 if (LL_RCC_PLL3_IsReady() != 0U)
1127 {
1128 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1129 adc_frequency = PLL_Clocks.PLL_R_Frequency;
1130 }
1131 break;
1132
1133 case LL_RCC_ADC_CLKSOURCE_CLKP:
1134 adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1135 break;
1136
1137 default:
1138 /* Kernel clock disabled */
1139 break;
1140 }
1141
1142 return adc_frequency;
1143 }
1144
1145 /**
1146 * @brief Return SDMMC clock frequency
1147 * @param SDMMCxSource This parameter can be one of the following values:
1148 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
1149 * @retval SDMMC clock frequency (in Hz)
1150 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1151 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)1152 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
1153 {
1154 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1155 LL_PLL_ClocksTypeDef PLL_Clocks;
1156
1157 /* Check parameter */
1158 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
1159
1160 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
1161 {
1162 case LL_RCC_SDMMC_CLKSOURCE_PLL2S:
1163 if (LL_RCC_PLL2_IsReady() != 0U)
1164 {
1165 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1166 sdmmc_frequency = PLL_Clocks.PLL_S_Frequency;
1167 }
1168 break;
1169
1170 case LL_RCC_SDMMC_CLKSOURCE_PLL2T:
1171 if (LL_RCC_PLL2_IsReady() != 0U)
1172 {
1173 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1174 sdmmc_frequency = PLL_Clocks.PLL_T_Frequency;
1175 }
1176 break;
1177
1178 default:
1179 /* Nothing to do */
1180 break;
1181 }
1182
1183 return sdmmc_frequency;
1184 }
1185
1186 /**
1187 * @brief Return CEC clock frequency
1188 * @param CECxSource This parameter can be one of the following values:
1189 * @arg @ref LL_RCC_CEC_CLKSOURCE
1190 * @retval CEC clock frequency (in Hz)
1191 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1192 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)1193 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1194 {
1195 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1196
1197 /* Check parameter */
1198 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
1199
1200 switch (LL_RCC_GetCECClockSource(CECxSource))
1201 {
1202 case LL_RCC_CEC_CLKSOURCE_LSE:
1203 if (LL_RCC_LSE_IsReady() != 0U)
1204 {
1205 cec_frequency = LSE_VALUE;
1206 }
1207 break;
1208
1209 case LL_RCC_CEC_CLKSOURCE_LSI:
1210 if (LL_RCC_LSI_IsReady() != 0U)
1211 {
1212 cec_frequency = LSI_VALUE;
1213 }
1214 break;
1215
1216 case LL_RCC_CEC_CLKSOURCE_CSI_DIV_122:
1217 if (LL_RCC_CSI_IsReady() != 0U)
1218 {
1219 cec_frequency = CSI_VALUE / 122U;
1220 }
1221 break;
1222
1223 default:
1224 /* Kernel clock disabled */
1225 break;
1226 }
1227
1228 return cec_frequency;
1229 }
1230
1231 /**
1232 * @brief Return PSSI clock frequency
1233 * @param PSSIxSource This parameter can be one of the following values:
1234 * @arg @ref LL_RCC_PSSI_CLKSOURCE
1235 * @retval PSSI clock frequency (in Hz)
1236 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1237 */
LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource)1238 uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource)
1239 {
1240 uint32_t pssi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1241 LL_PLL_ClocksTypeDef pll_clocks;
1242
1243 /* Check parameter */
1244 assert_param(IS_LL_RCC_PSSI_CLKSOURCE(PSSIxSource));
1245
1246 switch (LL_RCC_GetPSSIClockSource(PSSIxSource))
1247 {
1248 case LL_RCC_PSSI_CLKSOURCE_PLL3R:
1249 if (LL_RCC_PLL3_IsReady() != 0U)
1250 {
1251 LL_RCC_GetPLL3ClockFreq(&pll_clocks);
1252 pssi_frequency = pll_clocks.PLL_R_Frequency;
1253 }
1254 break;
1255
1256 case LL_RCC_PSSI_CLKSOURCE_CLKP:
1257 pssi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1258 break;
1259
1260 default:
1261 /* Nothing to do */
1262 break;
1263 }
1264
1265 return pssi_frequency;
1266 }
1267
1268
1269 /**
1270 * @brief Return USBPHYC clock frequency
1271 * @param USBPHYCxSource This parameter can be one of the following values:
1272 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE
1273 * @retval USBPHYC clock frequency (in Hz)
1274 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
1275 */
LL_RCC_GetUSBPHYCClockFreq(uint32_t USBPHYCxSource)1276 uint32_t LL_RCC_GetUSBPHYCClockFreq(uint32_t USBPHYCxSource)
1277 {
1278 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1279 LL_PLL_ClocksTypeDef PLL_Clocks;
1280
1281 /* Check parameter */
1282 assert_param(IS_LL_RCC_USBPHYC_CLKSOURCE(USBPHYCxSource));
1283
1284 switch (LL_RCC_GetUSBPHYCClockSource(USBPHYCxSource))
1285 {
1286 case LL_RCC_USBPHYC_CLKSOURCE_HSE:
1287 if (LL_RCC_HSE_IsReady() != 0U)
1288 {
1289 usb_frequency = HSE_VALUE;
1290 }
1291 break;
1292
1293 case LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2:
1294 if (LL_RCC_HSE_IsReady() != 0U)
1295 {
1296 usb_frequency = (HSE_VALUE / 2U);
1297 }
1298 break;
1299
1300 case LL_RCC_USBPHYC_CLKSOURCE_PLL3Q:
1301 if (LL_RCC_PLL3_IsReady() != 0U)
1302 {
1303 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1304 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1305 }
1306 break;
1307
1308 case LL_RCC_USBPHYC_CLKSOURCE_DISABLE:
1309 default:
1310 /* Nothing to do */
1311 break;
1312 }
1313
1314 return usb_frequency;
1315 }
1316
1317 /**
1318 * @brief Return ADF clock frequency
1319 * @param ADFxSource This parameter can be one of the following values:
1320 * @arg @ref LL_RCC_ADF1_CLKSOURCE
1321 * @retval ADF clock frequency (in Hz)
1322 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1323 */
LL_RCC_GetADFClockFreq(uint32_t ADFxSource)1324 uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource)
1325 {
1326 uint32_t adf_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1327 LL_PLL_ClocksTypeDef PLL_Clocks;
1328
1329 /* Check parameter */
1330 assert_param(IS_LL_RCC_ADF1_CLKSOURCE(ADFxSource));
1331
1332 switch (LL_RCC_GetADFClockSource(ADFxSource))
1333 {
1334 case LL_RCC_ADF1_CLKSOURCE_HCLK:
1335 adf_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1336 break;
1337
1338 case LL_RCC_ADF1_CLKSOURCE_PLL2P:
1339 if (LL_RCC_PLL2_IsReady() != 0U)
1340 {
1341 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1342 adf_frequency = PLL_Clocks.PLL_P_Frequency;
1343 }
1344 break;
1345
1346 case LL_RCC_ADF1_CLKSOURCE_PLL3P:
1347 if (LL_RCC_PLL3_IsReady() != 0U)
1348 {
1349 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1350 adf_frequency = PLL_Clocks.PLL_P_Frequency;
1351 }
1352 break;
1353
1354 case LL_RCC_ADF1_CLKSOURCE_I2S_CKIN:
1355 adf_frequency = EXTERNAL_CLOCK_VALUE;
1356 break;
1357
1358 case LL_RCC_ADF1_CLKSOURCE_CSI:
1359 if (LL_RCC_CSI_IsReady() != 0U)
1360 {
1361 adf_frequency = CSI_VALUE;
1362 }
1363 break;
1364
1365 case LL_RCC_ADF1_CLKSOURCE_HSI:
1366 if (LL_RCC_HSI_IsReady() != 0U)
1367 {
1368 if (LL_RCC_HSI_IsDividerReady() != 0U)
1369 {
1370 adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1371 }
1372 }
1373 break;
1374
1375 default:
1376 /* Nothing to do */
1377 break;
1378 }
1379
1380 return adf_frequency;
1381 }
1382
1383 /**
1384 * @brief Return SPDIFRX clock frequency
1385 * @param SPDIFRXxSource This parameter can be one of the following values:
1386 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE
1387 * @retval SPDIF clock frequency (in Hz)
1388 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1389 */
LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)1390 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1391 {
1392 uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1393 LL_PLL_ClocksTypeDef PLL_Clocks;
1394
1395 /* Check parameter */
1396 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1397
1398 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
1399 {
1400 case LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q:
1401 if (LL_RCC_PLL1_IsReady() != 0U)
1402 {
1403 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1404 spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
1405 }
1406 break;
1407
1408 case LL_RCC_SPDIFRX_CLKSOURCE_PLL2R:
1409 if (LL_RCC_PLL2_IsReady() != 0U)
1410 {
1411 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1412 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1413 }
1414 break;
1415
1416 case LL_RCC_SPDIFRX_CLKSOURCE_PLL3R:
1417 if (LL_RCC_PLL3_IsReady() != 0U)
1418 {
1419 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1420 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1421 }
1422 break;
1423
1424 case LL_RCC_SPDIFRX_CLKSOURCE_HSI:
1425 if (LL_RCC_HSI_IsReady() != 0U)
1426 {
1427 if (LL_RCC_HSI_IsDividerReady() != 0U)
1428 {
1429 spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1430 }
1431 }
1432 break;
1433
1434 default:
1435 /* Nothing to do */
1436 break;
1437 }
1438
1439 return spdif_frequency;
1440 }
1441
1442 /**
1443 * @brief Return SPIx clock frequency
1444 * @param SPIxSource This parameter can be one of the following values:
1445 * @arg @ref LL_RCC_SPI1_CLKSOURCE
1446 * @arg @ref LL_RCC_SPI23_CLKSOURCE
1447 * @arg @ref LL_RCC_SPI45_CLKSOURCE
1448 * @arg @ref LL_RCC_SPI6_CLKSOURCE
1449 * @retval SPI clock frequency (in Hz)
1450 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1451 */
LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)1452 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
1453 {
1454 uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1455 LL_PLL_ClocksTypeDef PLL_Clocks;
1456
1457 /* Check parameter */
1458 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
1459
1460 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1461 {
1462 case LL_RCC_SPI1_CLKSOURCE_PLL1Q:
1463 case LL_RCC_SPI23_CLKSOURCE_PLL1Q:
1464 if (LL_RCC_PLL1_IsReady() != 0U)
1465 {
1466 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1467 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1468 }
1469 break;
1470
1471 case LL_RCC_SPI1_CLKSOURCE_PLL2P:
1472 case LL_RCC_SPI23_CLKSOURCE_PLL2P:
1473 if (LL_RCC_PLL2_IsReady() != 0U)
1474 {
1475 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1476 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1477 }
1478 break;
1479
1480 case LL_RCC_SPI1_CLKSOURCE_PLL3P:
1481 case LL_RCC_SPI23_CLKSOURCE_PLL3P:
1482 if (LL_RCC_PLL3_IsReady() != 0U)
1483 {
1484 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1485 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1486 }
1487 break;
1488
1489 case LL_RCC_SPI1_CLKSOURCE_I2S_CKIN:
1490 case LL_RCC_SPI23_CLKSOURCE_I2S_CKIN:
1491 spi_frequency = EXTERNAL_CLOCK_VALUE;
1492 break;
1493
1494 case LL_RCC_SPI1_CLKSOURCE_CLKP:
1495 case LL_RCC_SPI23_CLKSOURCE_CLKP:
1496 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1497 break;
1498
1499 case LL_RCC_SPI45_CLKSOURCE_PCLK2:
1500 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1501 break;
1502
1503 case LL_RCC_SPI6_CLKSOURCE_PCLK4:
1504 spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1505 break;
1506
1507 case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
1508 case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
1509 if (LL_RCC_PLL2_IsReady() != 0U)
1510 {
1511 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1512 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1513 }
1514 break;
1515
1516 case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
1517 case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
1518 if (LL_RCC_PLL3_IsReady() != 0U)
1519 {
1520 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1521 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1522 }
1523 break;
1524
1525 case LL_RCC_SPI45_CLKSOURCE_HSI:
1526 case LL_RCC_SPI6_CLKSOURCE_HSI:
1527 if (LL_RCC_HSI_IsReady() != 0U)
1528 {
1529 if (LL_RCC_HSI_IsDividerReady() != 0U)
1530 {
1531 spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1532 }
1533 }
1534 break;
1535
1536 case LL_RCC_SPI45_CLKSOURCE_CSI:
1537 case LL_RCC_SPI6_CLKSOURCE_CSI:
1538 if (LL_RCC_CSI_IsReady() != 0U)
1539 {
1540 spi_frequency = CSI_VALUE;
1541 }
1542 break;
1543
1544 case LL_RCC_SPI45_CLKSOURCE_HSE:
1545 case LL_RCC_SPI6_CLKSOURCE_HSE:
1546 if (LL_RCC_HSE_IsReady() != 0U)
1547 {
1548 spi_frequency = HSE_VALUE;
1549 }
1550 break;
1551
1552 default:
1553 /* Kernel clock disabled */
1554 break;
1555 }
1556
1557 return spi_frequency;
1558 }
1559
1560 /**
1561 * @brief Return ETH clock frequency
1562 * @param ETHxSource This parameter can be one of the following values:
1563 * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE
1564 * @retval ETH clock frequency (in Hz)
1565 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
1566 */
LL_RCC_GetETHPHYClockFreq(uint32_t ETHxSource)1567 uint32_t LL_RCC_GetETHPHYClockFreq(uint32_t ETHxSource)
1568 {
1569 uint32_t eth_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1570 LL_PLL_ClocksTypeDef PLL_Clocks;
1571
1572 /* Check parameter */
1573 assert_param(IS_LL_RCC_ETH1PHY_CLKSOURCE(ETHxSource));
1574
1575 switch (LL_RCC_GetETHPHYClockSource(ETHxSource))
1576 {
1577 case LL_RCC_ETH1PHY_CLKSOURCE_HSE:
1578 if (LL_RCC_HSE_IsReady() != 0U)
1579 {
1580 eth_frequency = HSE_VALUE;
1581 }
1582 break;
1583
1584 case LL_RCC_ETH1PHY_CLKSOURCE_PLL3S:
1585 if (LL_RCC_PLL3_IsReady() != 0U)
1586 {
1587 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1588 eth_frequency = PLL_Clocks.PLL_S_Frequency;
1589 }
1590 break;
1591
1592 default:
1593 /* Nothing to do */
1594 break;
1595 }
1596
1597 return eth_frequency;
1598 }
1599
1600
1601 /**
1602 * @brief Return FDCAN clock frequency
1603 * @param FDCANxSource This parameter can be one of the following values:
1604 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1605 * @retval FDCAN clock frequency (in Hz)
1606 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1607 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)1608 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1609 {
1610 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1611 LL_PLL_ClocksTypeDef PLL_Clocks;
1612
1613 /* Check parameter */
1614 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
1615
1616 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1617 {
1618 case LL_RCC_FDCAN_CLKSOURCE_HSE:
1619 if (LL_RCC_HSE_IsReady() != 0U)
1620 {
1621 fdcan_frequency = HSE_VALUE;
1622 }
1623 break;
1624
1625 case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
1626 if (LL_RCC_PLL1_IsReady() != 0U)
1627 {
1628 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1629 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1630 }
1631 break;
1632
1633 case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
1634 if (LL_RCC_PLL2_IsReady() != 0U)
1635 {
1636 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1637 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1638 }
1639 break;
1640
1641 default:
1642 /* Kernel clock disabled */
1643 break;
1644 }
1645
1646 return fdcan_frequency;
1647 }
1648
1649 /**
1650 * @brief Return FMC clock frequency
1651 * @param FMCxSource This parameter can be one of the following values:
1652 * @arg @ref LL_RCC_FMC_CLKSOURCE
1653 * @retval FMC clock frequency (in Hz)
1654 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1655 */
LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)1656 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
1657 {
1658 uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1659 uint32_t clksource;
1660 LL_PLL_ClocksTypeDef PLL_Clocks;
1661
1662 /* Check parameter */
1663 assert_param(IS_LL_RCC_FMC_CLKSOURCE(FMCxSource));
1664
1665 if (LL_RCC_GetFMCSwitchPosition() == LL_RCC_SWP_FMC_HCLK_DIV4)
1666 {
1667 clksource = LL_RCC_FMC_CLKSOURCE_HCLK_DIV4;
1668 }
1669 else
1670 {
1671 clksource = LL_RCC_GetFMCClockSource(FMCxSource);
1672 }
1673
1674 switch (clksource)
1675 {
1676 case LL_RCC_FMC_CLKSOURCE_HCLK:
1677 fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1678 break;
1679
1680 case LL_RCC_FMC_CLKSOURCE_PLL1Q:
1681 if (LL_RCC_PLL1_IsReady() != 0U)
1682 {
1683 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1684 fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
1685 }
1686 break;
1687
1688 case LL_RCC_FMC_CLKSOURCE_PLL2R:
1689 if (LL_RCC_PLL2_IsReady() != 0U)
1690 {
1691 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1692 fmc_frequency = PLL_Clocks.PLL_R_Frequency;
1693 }
1694 break;
1695
1696 case LL_RCC_FMC_CLKSOURCE_HSI:
1697 if (LL_RCC_HSI_IsReady() != 0U)
1698 {
1699 if (LL_RCC_HSI_IsDividerReady() != 0U)
1700 {
1701 fmc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1702 }
1703 }
1704 break;
1705
1706 case LL_RCC_FMC_CLKSOURCE_HCLK_DIV4:
1707 fmc_frequency = (RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())) / 4U);
1708 break;
1709
1710 default:
1711 /* Nothing to do */
1712 break;
1713 }
1714
1715 return fmc_frequency;
1716 }
1717
1718 /**
1719 * @brief Return XSPI clock frequency
1720 * @param XSPIxSource This parameter can be one of the following values:
1721 * @arg @ref LL_RCC_XSPI1_CLKSOURCE
1722 * @arg @ref LL_RCC_XSPI2_CLKSOURCE
1723 * @retval XSPI clock frequency (in Hz)
1724 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1725 */
1726
LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource)1727 uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource)
1728 {
1729 uint32_t xspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1730 uint32_t clksource;
1731 LL_PLL_ClocksTypeDef PLL_Clocks;
1732
1733 /* Check parameter */
1734 assert_param(IS_LL_RCC_XSPI_CLKSOURCE(XSPIxSource));
1735
1736 clksource = LL_RCC_GetXSPIClockSource(XSPIxSource);
1737
1738 /* Update clock source depending on the XSPI clock switch position */
1739 switch (XSPIxSource)
1740 {
1741 case LL_RCC_XSPI1_CLKSOURCE:
1742 if (LL_RCC_GetXSPI1SwitchPosition() == LL_RCC_SWP_XSPI1_HCLK_DIV4)
1743 {
1744 clksource = LL_RCC_XSPI1_CLKSOURCE_HCLK_DIV4;
1745 }
1746 break;
1747 case LL_RCC_XSPI2_CLKSOURCE:
1748 if (LL_RCC_GetXSPI2SwitchPosition() == LL_RCC_SWP_XSPI2_HCLK_DIV4)
1749 {
1750 clksource = LL_RCC_XSPI2_CLKSOURCE_HCLK_DIV4;
1751 }
1752 break;
1753 default:
1754 /* Do nothing */
1755 break;
1756 }
1757
1758 switch (clksource)
1759 {
1760 case LL_RCC_XSPI1_CLKSOURCE_HCLK:
1761 case LL_RCC_XSPI2_CLKSOURCE_HCLK:
1762 xspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1763 break;
1764
1765 case LL_RCC_XSPI1_CLKSOURCE_PLL2S:
1766 case LL_RCC_XSPI2_CLKSOURCE_PLL2S:
1767 if (LL_RCC_PLL2_IsReady() != 0U)
1768 {
1769 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1770 xspi_frequency = PLL_Clocks.PLL_S_Frequency;
1771 }
1772 break;
1773
1774 case LL_RCC_XSPI1_CLKSOURCE_PLL2T:
1775 case LL_RCC_XSPI2_CLKSOURCE_PLL2T:
1776 if (LL_RCC_PLL2_IsReady() != 0U)
1777 {
1778 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1779 xspi_frequency = PLL_Clocks.PLL_T_Frequency;
1780 }
1781 break;
1782
1783 case LL_RCC_XSPI1_CLKSOURCE_HCLK_DIV4:
1784 case LL_RCC_XSPI2_CLKSOURCE_HCLK_DIV4:
1785 xspi_frequency = (RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())) / 4U);
1786 break;
1787
1788 default:
1789 /* Nothing to do */
1790 break;
1791 }
1792
1793 return xspi_frequency;
1794 }
1795
1796 /**
1797 * @brief Return CLKP clock frequency
1798 * @param CLKPxSource This parameter can be one of the following values:
1799 * @arg @ref LL_RCC_CLKP_CLKSOURCE
1800 * @retval CLKP clock frequency (in Hz)
1801 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1802 */
LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)1803 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
1804 {
1805 uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1806
1807 /* Check parameter */
1808 assert_param(IS_LL_RCC_CLKP_CLKSOURCE(CLKPxSource));
1809
1810 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
1811 {
1812 case LL_RCC_CLKP_CLKSOURCE_HSI:
1813 if (LL_RCC_HSI_IsReady() != 0U)
1814 {
1815 if (LL_RCC_HSI_IsDividerReady() != 0U)
1816 {
1817 clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1818 }
1819 }
1820 break;
1821
1822 case LL_RCC_CLKP_CLKSOURCE_CSI:
1823 if (LL_RCC_CSI_IsReady() != 0U)
1824 {
1825 clkp_frequency = CSI_VALUE;
1826 }
1827 break;
1828
1829 case LL_RCC_CLKP_CLKSOURCE_HSE:
1830 if (LL_RCC_HSE_IsReady() != 0U)
1831 {
1832 clkp_frequency = HSE_VALUE;
1833 }
1834 break;
1835
1836 default:
1837 /* CLKP clock disabled */
1838 break;
1839 }
1840
1841 return clkp_frequency;
1842 }
1843
1844 /**
1845 * @}
1846 */
1847
1848 /**
1849 * @}
1850 */
1851
1852 /** @addtogroup RCC_LL_Private_Functions
1853 * @{
1854 */
1855
1856 /**
1857 * @brief Return SYSTEM clock frequency
1858 * @retval SYSTEM clock frequency (in Hz)
1859 */
RCC_GetSystemClockFreq(void)1860 static uint32_t RCC_GetSystemClockFreq(void)
1861 {
1862 uint32_t frequency = 0U;
1863 LL_PLL_ClocksTypeDef PLL_Clocks;
1864
1865 /* Get SYSCLK source -------------------------------------------------------*/
1866 switch (LL_RCC_GetSysClkSource())
1867 {
1868 /* No check on Ready: Won't be selected by hardware if not */
1869 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
1870 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1871 break;
1872
1873 case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
1874 frequency = CSI_VALUE;
1875 break;
1876
1877 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
1878 frequency = HSE_VALUE;
1879 break;
1880
1881 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
1882 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1883 frequency = PLL_Clocks.PLL_P_Frequency;
1884 break;
1885
1886 default:
1887 /* Nothing to do */
1888 break;
1889 }
1890
1891 return frequency;
1892 }
1893
1894 /**
1895 * @brief Return HCLK clock frequency
1896 * @param SYSCLK_Frequency SYSCLK clock frequency
1897 * @retval HCLK clock frequency (in Hz)
1898 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1899 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1900 {
1901 /* HCLK clock frequency */
1902 return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1903 }
1904
1905 /**
1906 * @brief Return PCLK1 clock frequency
1907 * @param HCLK_Frequency HCLK clock frequency
1908 * @retval PCLK1 clock frequency (in Hz)
1909 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1910 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1911 {
1912 /* PCLK1 clock frequency */
1913 return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1914 }
1915
1916 /**
1917 * @brief Return PCLK2 clock frequency
1918 * @param HCLK_Frequency HCLK clock frequency
1919 * @retval PCLK2 clock frequency (in Hz)
1920 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1921 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1922 {
1923 /* PCLK2 clock frequency */
1924 return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1925 }
1926
1927 /**
1928 * @brief Return PCLK4 clock frequency
1929 * @param HCLK_Frequency HCLK clock frequency
1930 * @retval PCLK4 clock frequency (in Hz)
1931 */
RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)1932 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
1933 {
1934 /* PCLK4 clock frequency */
1935 return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
1936 }
1937
1938 /**
1939 * @brief Return PCLK5 clock frequency
1940 * @param HCLK_Frequency HCLK clock frequency
1941 * @retval PCLK5 clock frequency (in Hz)
1942 */
RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency)1943 static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency)
1944 {
1945 /* PCLK5 clock frequency */
1946 return LL_RCC_CALC_PCLK5_FREQ(HCLK_Frequency, LL_RCC_GetAPB5Prescaler());
1947 }
1948
1949 /**
1950 * @}
1951 */
1952
1953 /**
1954 * @}
1955 */
1956
1957 #endif /* defined(RCC) */
1958
1959 /**
1960 * @}
1961 */
1962
1963 #endif /* USE_FULL_LL_DRIVER */
1964
