1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 #ifndef R_USB_DEVICE_CFG_H_
8 #define R_USB_DEVICE_CFG_H_
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 #define USBHS_PHY_CLOCK_SOURCE_IS_XTAL    (DT_ENUM_IDX_OR(DT_NODELABEL(usbhs_phy), phys_clock_src, 0))
14 
15 #define USBD_CFG_PARAM_CHECKING_ENABLE    (BSP_CFG_PARAM_CHECKING_ENABLE)
16 #define USBD_CFG_BUS_WAIT_TIME            (0x000FU) /* 17 access cycles */
17 
18 #if USBHS_PHY_CLOCK_SOURCE_IS_XTAL
19 #if BSP_CFG_XTAL_HZ == 12000000
20 #define USBD_CFG_PHYSET_CLKSEL            (0U)
21 #elif BSP_CFG_XTAL_HZ == 48000000
22 #define USBD_CFG_PHYSET_CLKSEL            (0x1U)
23 #elif BSP_CFG_XTAL_HZ == 20000000
24 #define USBD_CFG_PHYSET_CLKSEL            (0x2U)
25 #elif BSP_CFG_XTAL_HZ == 24000000
26 #define USBD_CFG_PHYSET_CLKSEL            (0x3U)
27 #else
28 #error "Available XTAL clocks are 12-20-24-48Mhz"
29 #endif
30 #else   /* Use 48Mhz UCK as clock source for PHY clock */
31 #define USBD_CFG_PHYSET_CLKSEL            (-1)
32 #endif
33 
34 #ifdef __cplusplus
35 }
36 #endif
37 #endif                                 /* R_USB_DEVICE_CFG_H_ */
38