1 /**************************************************************************//** 2 * @file usbd_reg.h 3 * @version V1.00 4 * @brief USBD register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __USBD_REG_H__ 10 #define __USBD_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- USB Device Controller -------------------------*/ 19 /** 20 @addtogroup USBD USB Device Controller(USBD) 21 Memory Mapped Structure for USBD Controller 22 @{ 23 */ 24 25 26 27 /** 28 * @brief USBD endpoints register 29 */ 30 typedef struct 31 { 32 /** 33 * @var USBD_EP_T::BUFSEG 34 * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0 Endpoint Buffer Segmentation Register 35 * --------------------------------------------------------------------------------------------------- 36 * |Bits |Field |Descriptions 37 * | :----: | :----: | :---- | 38 * |[8:3] |BUFSEG |Endpoint Buffer Segmentation 39 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 40 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 41 * | | |Where the USBD_SRAM address = USBD_BA+0x100h. 42 * | | |Refer to the section 6.32.5.7 for the endpoint SRAM structure and its description. 43 * @var USBD_EP_T::MXPLD 44 * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4 Endpoint Maximal Payload Register 45 * --------------------------------------------------------------------------------------------------- 46 * |Bits |Field |Descriptions 47 * | :----: | :----: | :---- | 48 * |[8:0] |MXPLD |Maximal Payload 49 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 50 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 51 * | | |(1) When the register is written by CPU, 52 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 53 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 54 * | | |(2) When the register is read by CPU, 55 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host. 56 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 57 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 58 * @var USBD_EP_T::CFG 59 * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8 Endpoint Configuration Register 60 * --------------------------------------------------------------------------------------------------- 61 * |Bits |Field |Descriptions 62 * | :----: | :----: | :---- | 63 * |[3:0] |EPNUM |Endpoint Number 64 * | | |These bits are used to define the endpoint number of the current endpoint. 65 * |[4] |ISOCH |Isochronous Endpoint 66 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 67 * | | |0 = No Isochronous endpoint. 68 * | | |1 = Isochronous endpoint. 69 * |[6:5] |STATE |Endpoint State 70 * | | |00 = Endpoint Disabled. 71 * | | |01 = Out endpoint. 72 * | | |10 = IN endpoint. 73 * | | |11 = Undefined. 74 * |[7] |DSQSYNC |Data Sequence Synchronization 75 * | | |0 = DATA0 PID. 76 * | | |1 = DATA1 PID. 77 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet. 78 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 79 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won’t be toggled in double buffer mode. 80 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 81 * | | |Note 2: It won’t be toggled by hardware when DBEN = 1. USB data toggle will be guaranteed by changing endpoint. 82 * |[9] |CSTALL |Clear STALL Response 83 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 84 * | | |1 = Clear the device to response STALL handshake in setup stage. 85 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 86 * | | |0 = Inactive in double buffer mode. 87 * | | |1 = Active in double buffer mode. 88 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 89 * |[11] |DBEN |Double Buffer Enable 90 * | | |0 = Single buffer mode. 91 * | | |1 = Double buffer mode. 92 * @var USBD_EP_T::CFGP 93 * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC Endpoint Set Stall and Clear In/Out Ready Control Register 94 * --------------------------------------------------------------------------------------------------- 95 * |Bits |Field |Descriptions 96 * | :----: | :----: | :---- | 97 * |[0] |CLRRDY |Clear Ready 98 * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data 99 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically cleared to 0. 100 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 101 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 102 * | | |This bit is written 1 only and is always 0 when it is read back. 103 * |[1] |SSTALL |Set STALL 104 * | | |0 = Disable the device to response STALL. 105 * | | |1 = Set the device to respond STALL automatically. 106 */ 107 __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */ 108 __IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */ 109 __IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */ 110 __IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */ 111 112 } USBD_EP_T; 113 114 typedef struct 115 { 116 117 118 /** 119 * @var USBD_T::INTEN 120 * Offset: 0x00 USB Device Interrupt Enable Register 121 * --------------------------------------------------------------------------------------------------- 122 * |Bits |Field |Descriptions 123 * | :----: | :----: | :---- | 124 * |[0] |BUSIEN |Bus Event Interrupt Enable Bit 125 * | | |0 = BUS event interrupt Disabled. 126 * | | |1 = BUS event interrupt Enabled. 127 * |[1] |USBIEN |USB Event Interrupt Enable Bit 128 * | | |0 = USB event interrupt Disabled. 129 * | | |1 = USB event interrupt Enabled. 130 * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit 131 * | | |0 = VBUS detection Interrupt Disabled. 132 * | | |1 = VBUS detection Interrupt Enabled. 133 * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit 134 * | | |0 = No-event-wake-up Interrupt Disabled. 135 * | | |1 = No-event-wake-up Interrupt Enabled. 136 * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit 137 * | | |0 = SOF Interrupt Disabled. 138 * | | |1 = SOF Interrupt Enabled. 139 * |[8] |WKEN |Wake-up Function Enable Bit 140 * | | |0 = USB wake-up function Disabled. 141 * | | |1 = USB wake-up function Enabled. 142 * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token 143 * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. 144 * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. 145 * @var USBD_T::INTSTS 146 * Offset: 0x04 USB Device Interrupt Event Status Register 147 * --------------------------------------------------------------------------------------------------- 148 * |Bits |Field |Descriptions 149 * | :----: | :----: | :---- | 150 * |[0] |BUSIF |BUS Interrupt Status 151 * | | |The BUS event means that there is one of the suspense or the resume function in the bus. 152 * | | |0 = No BUS event occurred. 153 * | | |1 = Bus event occurred. Check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USBD_INTSTS[0]. 154 * |[1] |USBIF |USB Event Interrupt Status 155 * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. 156 * | | |0 = No USB event occurred. 157 * | | |1 = USB event occurred. Check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). 158 * |[2] |VBDETIF |VBUS Detection Interrupt Status 159 * | | |0 = There is no attached/detached event in the USB. 160 * | | |1 = There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2]. 161 * |[3] |NEVWKIF |No-event-wake-up Interrupt Status 162 * | | |0 = NEVWK event did not occur. 163 * | | |1 = No-event-wake-up event occurred, cleared by writing 1 to USBD_INTSTS[3]. 164 * |[4] |SOFIF |Start of Frame Interrupt Status 165 * | | |0 = SOF event did not occur. 166 * | | |1 = SOF event occurred, cleared by writing 1 to USBD_INTSTS[4]. 167 * |[16] |EPEVT0 |Endpoint 0's USB Event Status 168 * | | |0 = No event occurred in endpoint 0. 169 * | | |1 = USB event occurred on Endpoint 0. Check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. 170 * |[17] |EPEVT1 |Endpoint 1's USB Event Status 171 * | | |0 = No event occurred in endpoint 1. 172 * | | |1 = USB event occurred on Endpoint 1. Check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. 173 * |[18] |EPEVT2 |Endpoint 2's USB Event Status 174 * | | |0 = No event occurred in endpoint 2. 175 * | | |1 = USB event occurred on Endpoint 2. Check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. 176 * |[19] |EPEVT3 |Endpoint 3's USB Event Status 177 * | | |0 = No event occurred in endpoint 3. 178 * | | |1 = USB event occurred on Endpoint 3. Check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. 179 * |[20] |EPEVT4 |Endpoint 4's USB Event Status 180 * | | |0 = No event occurred in endpoint 4. 181 * | | |1 = USB event occurred on Endpoint 4. Check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. 182 * |[21] |EPEVT5 |Endpoint 5's USB Event Status 183 * | | |0 = No event occurred in endpoint 5. 184 * | | |1 = USB event occurred on Endpoint 5. Check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. 185 * |[22] |EPEVT6 |Endpoint 6's USB Event Status 186 * | | |0 = No event occurred in endpoint 6. 187 * | | |1 = USB event occurred on Endpoint 6. Check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. 188 * |[23] |EPEVT7 |Endpoint 7's USB Event Status 189 * | | |0 = No event occurred in endpoint 7. 190 * | | |1 = USB event occurred on Endpoint 7. Check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. 191 * |[24] |EPEVT8 |Endpoint 8's USB Event Status 192 * | | |0 = No event occurred in endpoint 8. 193 * | | |1 = USB event occurred on Endpoint 8. Check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. 194 * |[25] |EPEVT9 |Endpoint 9's USB Event Status 195 * | | |0 = No event occurred in endpoint 9. 196 * | | |1 = USB event occurred on Endpoint 9. Check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. 197 * |[26] |EPEVT10 |Endpoint 10's USB Event Status 198 * | | |0 = No event occurred in endpoint 10. 199 * | | |1 = USB event occurred on Endpoint 10. Check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. 200 * |[27] |EPEVT11 |Endpoint 11's USB Event Status 201 * | | |0 = No event occurred in endpoint 11. 202 * | | |1 = USB event occurred on Endpoint 11. Check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. 203 * |[31] |SETUP |Setup Event Status 204 * | | |0 = No Setup event. 205 * | | |1 = Setup event occurred, cleared by writing 1 to USBD_INTSTS[31]. 206 * @var USBD_T::FADDR 207 * Offset: 0x08 USB Device Function Address Register 208 * --------------------------------------------------------------------------------------------------- 209 * |Bits |Field |Descriptions 210 * | :----: | :----: | :---- | 211 * |[6:0] |FADDR |USB Device Function Address 212 * @var USBD_T::EPSTS 213 * Offset: 0x0C USB Device Endpoint Status Register 214 * --------------------------------------------------------------------------------------------------- 215 * |Bits |Field |Descriptions 216 * | :----: | :----: | :---- | 217 * |[7] |OV |Overrun 218 * | | |It indicates that the received data is over the maximum payload number or not. 219 * | | |0 = No overrun. 220 * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 bytes. 221 * @var USBD_T::ATTR 222 * Offset: 0x10 USB Device Bus Status and Attribution Register 223 * --------------------------------------------------------------------------------------------------- 224 * |Bits |Field |Descriptions 225 * | :----: | :----: | :---- | 226 * |[0] |USBRST |USB Reset Status (Read Only) 227 * | | |0 = Bus no reset. 228 * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. 229 * |[1] |SUSPEND |Suspend Status (Read Only) 230 * | | |0 = Bus no suspend. 231 * | | |1 = Bus idle more than 3ms, either cable is plugged-out or host is sleeping. 232 * |[2] |RESUME |Resume Status (Read Only) 233 * | | |0 = No bus resume. 234 * | | |1 = Resume from suspend. 235 * |[3] |TOUT |Time-out Status (Read Only) 236 * | | |0 = No time-out. 237 * | | |1 = No Bus response more than 18 bits time. 238 * |[4] |PHYEN |PHY Transceiver Function Enable Bit 239 * | | |0 = PHY transceiver function Disabled. 240 * | | |1 = PHY transceiver function Enabled. 241 * |[5] |RWAKEUP |Remote Wake-up 242 * | | |0 = Release the USB bus from K state. 243 * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. 244 * |[7] |USBEN |USB Controller Enable Bit 245 * | | |0 = USB Controller Disabled. 246 * | | |1 = USB Controller Enabled. 247 * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit 248 * | | |0 = Pull-up resistor in USB_D+ bus Disabled. 249 * | | |1 = Pull-up resistor in USB_D+ bus Active. 250 * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection 251 * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. 252 * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. 253 * |[11] |LPMACK |LPM Token Acknowledge Enable Bit 254 * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. 255 * | | |0= The valid LPM Token will be NYET. 256 * | | |1= The valid LPM Token will be ACK. 257 * |[12] |L1SUSPEND |LPM L1 Suspend (Read Only) 258 * | | |0 = Bus no L1 state suspend. 259 * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. 260 * |[13] |L1RESUME |LPM L1 Resume (Read Only) 261 * | | |0 = Bus no LPM L1 state resume. 262 * | | |1 = LPM L1 state resume from LPM L1 state suspend. 263 * @var USBD_T::VBUSDET 264 * Offset: 0x14 USB Device VBUS Detection Register 265 * --------------------------------------------------------------------------------------------------- 266 * |Bits |Field |Descriptions 267 * | :----: | :----: | :---- | 268 * |[0] |VBUSDET |Device VBUS Detection 269 * | | |0 = Controller is not attached to the USB host. 270 * | | |1 = Controller is attached to the USB host. 271 * @var USBD_T::STBUFSEG 272 * Offset: 0x18 SETUP Token Buffer Segmentation Register 273 * --------------------------------------------------------------------------------------------------- 274 * |Bits |Field |Descriptions 275 * | :----: | :----: | :---- | 276 * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation 277 * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is 278 * | | |USBD_SRAM address + {STBUFSEG, 3'b000} 279 * | | |Where the USBD_SRAM address = USBD_BA+0x100h. 280 * | | |Note: It is used for SETUP token only. 281 * @var USBD_T::EPSTS0 282 * Offset: 0x20 USB Device Endpoint Status Register 0 283 * --------------------------------------------------------------------------------------------------- 284 * |Bits |Field |Descriptions 285 * | :----: | :----: | :---- | 286 * |[3:0] |EPSTS0 |Endpoint 0 Status 287 * | | |These bits are used to indicate the current status of this endpoint. 288 * | | |0000 = In ACK. 289 * | | |0001 = In NAK. 290 * | | |0010 = Out Packet Data0 ACK. 291 * | | |0110 = Out Packet Data1 ACK. 292 * | | |0111 = Isochronous transfer end. 293 * |[7:4] |EPSTS1 |Endpoint 1 Status 294 * | | |These bits are used to indicate the current status of this endpoint. 295 * | | |0000 = In ACK. 296 * | | |0001 = In NAK. 297 * | | |0010 = Out Packet Data0 ACK. 298 * | | |0110 = Out Packet Data1 ACK. 299 * | | |0111 = Isochronous transfer end. 300 * |[11:8] |EPSTS2 |Endpoint 2 Status 301 * | | |These bits are used to indicate the current status of this endpoint. 302 * | | |0000 = In ACK. 303 * | | |0001 = In NAK. 304 * | | |0010 = Out Packet Data0 ACK. 305 * | | |0110 = Out Packet Data1 ACK. 306 * | | |0111 = Isochronous transfer end. 307 * |[15:12] |EPSTS3 |Endpoint 3 Status 308 * | | |These bits are used to indicate the current status of this endpoint. 309 * | | |0000 = In ACK. 310 * | | |0001 = In NAK. 311 * | | |0010 = Out Packet Data0 ACK. 312 * | | |0110 = Out Packet Data1 ACK. 313 * | | |0111 = Isochronous transfer end. 314 * |[19:16] |EPSTS4 |Endpoint 4 Status 315 * | | |These bits are used to indicate the current status of this endpoint. 316 * | | |0000 = In ACK. 317 * | | |0001 = In NAK. 318 * | | |0010 = Out Packet Data0 ACK. 319 * | | |0110 = Out Packet Data1 ACK. 320 * | | |0111 = Isochronous transfer end. 321 * |[23:20] |EPSTS5 |Endpoint 5 Status 322 * | | |These bits are used to indicate the current status of this endpoint. 323 * | | |0000 = In ACK. 324 * | | |0001 = In NAK. 325 * | | |0010 = Out Packet Data0 ACK. 326 * | | |0110 = Out Packet Data1 ACK. 327 * | | |0111 = Isochronous transfer end. 328 * |[27:24] |EPSTS6 |Endpoint 6 Status 329 * | | |These bits are used to indicate the current status of this endpoint. 330 * | | |0000 = In ACK. 331 * | | |0001 = In NAK. 332 * | | |0010 = Out Packet Data0 ACK. 333 * | | |0110 = Out Packet Data1 ACK. 334 * | | |0111 = Isochronous transfer end. 335 * |[31:28] |EPSTS7 |Endpoint 7 Status 336 * | | |These bits are used to indicate the current status of this endpoint. 337 * | | |0000 = In ACK. 338 * | | |0001 = In NAK. 339 * | | |0010 = Out Packet Data0 ACK. 340 * | | |0110 = Out Packet Data1 ACK. 341 * | | |0111 = Isochronous transfer end. 342 * @var USBD_T::EPSTS1 343 * Offset: 0x24 USB Device Endpoint Status Register 1 344 * --------------------------------------------------------------------------------------------------- 345 * |Bits |Field |Descriptions 346 * | :----: | :----: | :---- | 347 * |[3:0] |EPSTS8 |Endpoint 8 Status 348 * | | |These bits are used to indicate the current status of this endpoint. 349 * | | |0000 = In ACK. 350 * | | |0001 = In NAK. 351 * | | |0010 = Out Packet Data0 ACK. 352 * | | |0110 = Out Packet Data1 ACK. 353 * | | |0111 = Isochronous transfer end. 354 * |[7:4] |EPSTS9 |Endpoint 9 Status 355 * | | |These bits are used to indicate the current status of this endpoint. 356 * | | |0000 = In ACK. 357 * | | |0001 = In NAK. 358 * | | |0010 = Out Packet Data0 ACK. 359 * | | |0110 = Out Packet Data1 ACK. 360 * | | |0111 = Isochronous transfer end. 361 * |[11:8] |EPSTS10 |Endpoint 10 Status 362 * | | |These bits are used to indicate the current status of this endpoint. 363 * | | |0000 = In ACK. 364 * | | |0001 = In NAK. 365 * | | |0010 = Out Packet Data0 ACK. 366 * | | |0110 = Out Packet Data1 ACK. 367 * | | |0111 = Isochronous transfer end. 368 * |[15:12] |EPSTS11 |Endpoint 11 Status 369 * | | |These bits are used to indicate the current status of this endpoint. 370 * | | |0000 = In ACK. 371 * | | |0001 = In NAK. 372 * | | |0010 = Out Packet Data0 ACK. 373 * | | |0110 = Out Packet Data1 ACK. 374 * | | |0111 = Isochronous transfer end. 375 * @var USBD_T::LPMATTR 376 * Offset: 0x88 USB LPM Attribution Register 377 * --------------------------------------------------------------------------------------------------- 378 * |Bits |Field |Descriptions 379 * | :----: | :----: | :---- | 380 * |[3:0] |LPMLINKSTS|LPM Link State 381 * | | |These bits contain the bLinkState received with last ACK LPM Token. 382 * | | |0000 = Reserve. 383 * | | |0001 = L1 (Sleep). 384 * | | |0010 - 1111 = Reserve. 385 * |[7:4] |LPMBESL |LPM Best Effort Service Latency 386 * | | |These bits contain the BESL value received with last ACK LPM Token. 387 * | | |0000 = 125us. 388 * | | |0001 = 150us. 389 * | | |0010 = 200us. 390 * | | |0011 = 300us. 391 * | | |0100 = 400us. 392 * | | |0101 = 500us. 393 * | | |0110 = 1000us. 394 * | | |0111 = 2000us. 395 * | | |1000 = 3000us. 396 * | | |1001 = 4000us. 397 * | | |1010 = 5000us. 398 * | | |1011 = 6000us. 399 * | | |1100 = 7000us. 400 * | | |1101 = 8000us. 401 * | | |1110 = 9000us. 402 * | | |1111 = 10000us. 403 * |[8] |LPMRWAKUP |LPM Remote Wakeup 404 * | | |This bit contains the bRemoteWake value received with last ACK LPM Token. 405 * @var USBD_T::FN 406 * Offset: 0x8C USB Frame Number Register 407 * --------------------------------------------------------------------------------------------------- 408 * |Bits |Field |Descriptions 409 * | :----: | :----: | :---- | 410 * |[10:0] |FN |Frame Number 411 * | | |These bits contain the 11-bits frame number in the last received SOF packet. 412 * @var USBD_T::SE0 413 * Offset: 0x90 USB Device Drive SE0 Control Register 414 * --------------------------------------------------------------------------------------------------- 415 * |Bits |Field |Descriptions 416 * | :----: | :----: | :---- | 417 * |[0] |SE0 |Drive Single Ended Zero in USB Bus 418 * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. 419 * | | |0 = Normal operation. 420 * | | |1 = Force USB PHY transceiver to drive SE0. 421 */ 422 __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ 423 __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ 424 __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ 425 __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ 426 __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ 427 __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ 428 __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ 429 __I uint32_t RESERVE0[1]; 430 __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ 431 __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ 432 __I uint32_t RESERVE1[24]; 433 __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ 434 __I uint32_t FN; /*!< [0x008c] USB Frame Number Register */ 435 __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ 436 __I uint32_t RESERVE2[283]; 437 USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ 438 439 } USBD_T; 440 441 /** 442 @addtogroup USBD_CONST USBD Bit Field Definition 443 Constant Definitions for USBD Controller 444 @{ 445 */ 446 447 #define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ 448 #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ 449 450 #define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ 451 #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ 452 453 #define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ 454 #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ 455 456 #define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ 457 #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ 458 459 #define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ 460 #define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ 461 462 #define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ 463 #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ 464 465 #define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ 466 #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ 467 468 #define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ 469 #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ 470 471 #define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ 472 #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ 473 474 #define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ 475 #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ 476 477 #define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ 478 #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ 479 480 #define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ 481 #define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ 482 483 #define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ 484 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ 485 486 #define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ 487 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ 488 489 #define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ 490 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ 491 492 #define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ 493 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ 494 495 #define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ 496 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ 497 498 #define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ 499 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ 500 501 #define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ 502 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ 503 504 #define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ 505 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ 506 507 #define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ 508 #define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ 509 510 #define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ 511 #define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ 512 513 #define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ 514 #define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ 515 516 #define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ 517 #define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ 518 519 #define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ 520 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ 521 522 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ 523 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ 524 525 #define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ 526 #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ 527 528 #define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ 529 #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ 530 531 #define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ 532 #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ 533 534 #define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ 535 #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ 536 537 #define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ 538 #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ 539 540 #define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ 541 #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ 542 543 #define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ 544 #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ 545 546 #define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ 547 #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ 548 549 #define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ 550 #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ 551 552 #define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ 553 #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ 554 555 #define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ 556 #define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ 557 558 #define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ 559 #define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ 560 561 #define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ 562 #define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ 563 564 #define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ 565 #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ 566 567 #define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ 568 #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ 569 570 #define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ 571 #define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ 572 573 #define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ 574 #define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ 575 576 #define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ 577 #define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ 578 579 #define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ 580 #define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ 581 582 #define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ 583 #define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ 584 585 #define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ 586 #define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ 587 588 #define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ 589 #define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ 590 591 #define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ 592 #define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ 593 594 #define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ 595 #define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ 596 597 #define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ 598 #define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ 599 600 #define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ 601 #define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ 602 603 #define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ 604 #define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ 605 606 #define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ 607 #define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ 608 609 #define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ 610 #define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ 611 612 #define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ 613 #define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ 614 615 #define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ 616 #define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ 617 618 #define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ 619 #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ 620 621 #define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ 622 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ 623 624 #define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ 625 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ 626 627 #define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ 628 #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ 629 630 #define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ 631 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ 632 633 #define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ 634 #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ 635 636 #define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ 637 #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ 638 639 #define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ 640 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ 641 642 #define USBD_CFG_DBTGACTIVE_Pos (10) /*!< USBD_EP_T::CFG: DBTGACTIVE Position */ 643 #define USBD_CFG_DBTGACTIVE_Msk (0x1ul << USBD_CFG_DBTGACTIVE_Pos) /*!< USBD_EP_T::CFG: DBTGACTIVE Mask */ 644 645 #define USBD_CFG_DBEN_Pos (11) /*!< USBD_EP_T::CFG: DBEN Position */ 646 #define USBD_CFG_DBEN_Msk (0x1ul << USBD_CFG_DBEN_Pos) /*!< USBD_EP_T::CFG: DBEN Mask */ 647 648 #define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ 649 #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ 650 651 #define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ 652 #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ 653 654 /**@}*/ /* USBD_CONST */ 655 /**@}*/ /* end of USBD register group */ 656 /**@}*/ /* end of REGISTER group */ 657 658 #endif /* __USBD_REG_H__ */ 659
