1 2 /******************************************************************************/ 3 /* Device Specific Peripheral registers structures */ 4 /******************************************************************************/ 5 6 /** @addtogroup REGISTER Control Register 7 8 @{ 9 10 */ 11 12 13 /*---------------------- USB Device Controller -------------------------*/ 14 /** 15 @addtogroup USBD USB Device Controller(USBD) 16 Memory Mapped Structure for USBD Controller 17 @{ */ 18 19 /** 20 * @brief USBD endpoints register 21 */ 22 typedef struct 23 { 24 /** 25 * @var USBD_EP_T::BUFSEG 26 * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0 Endpoint Buffer Segmentation Register 27 * --------------------------------------------------------------------------------------------------- 28 * |Bits |Field |Descriptions 29 * | :----: | :----: | :---- | 30 * |[8:3] |BUFSEG |Endpoint Buffer Segmentation 31 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 32 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 33 * | | |Where the USBD_SRAM address = USBD_BA+0x100h. 34 * | | |Refer to the section 6.32.5.7 for the endpoint SRAM structure and its description. 35 * @var USBD_EP_T::MXPLD 36 * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4 Endpoint Maximal Payload Register 37 * --------------------------------------------------------------------------------------------------- 38 * |Bits |Field |Descriptions 39 * | :----: | :----: | :---- | 40 * |[8:0] |MXPLD |Maximal Payload 41 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 42 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 43 * | | |(1) When the register is written by CPU, 44 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 45 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 46 * | | |(2) When the register is read by CPU, 47 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host. 48 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 49 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 50 * @var USBD_EP_T::CFG 51 * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8 Endpoint Configuration Register 52 * --------------------------------------------------------------------------------------------------- 53 * |Bits |Field |Descriptions 54 * | :----: | :----: | :---- | 55 * |[3:0] |EPNUM |Endpoint Number 56 * | | |These bits are used to define the endpoint number of the current endpoint. 57 * |[4] |ISOCH |Isochronous Endpoint 58 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 59 * | | |0 = No Isochronous endpoint. 60 * | | |1 = Isochronous endpoint. 61 * |[6:5] |STATE |Endpoint State 62 * | | |00 = Endpoint Disabled. 63 * | | |01 = Out endpoint. 64 * | | |10 = IN endpoint. 65 * | | |11 = Undefined. 66 * |[7] |DSQSYNC |Data Sequence Synchronization 67 * | | |0 = DATA0 PID. 68 * | | |1 = DATA1 PID. 69 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet. 70 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 71 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won?�t be toggled in double buffer mode. 72 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 73 * | | |Note 2: It won?�t be toggled by hardware when DBEN = 1. USB data toggle will be guaranteed by changing endpoint. 74 * |[9] |CSTALL |Clear STALL Response 75 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 76 * | | |1 = Clear the device to response STALL handshake in setup stage. 77 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 78 * | | |0 = Inactive in double buffer mode. 79 * | | |1 = Active in double buffer mode. 80 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 81 * |[11] |DBEN |Double Buffer Enable 82 * | | |0 = Single buffer mode. 83 * | | |1 = Double buffer mode. 84 * @var USBD_EP_T::CFGP 85 * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC Endpoint Set Stall and Clear In/Out Ready Control Register 86 * --------------------------------------------------------------------------------------------------- 87 * |Bits |Field |Descriptions 88 * | :----: | :----: | :---- | 89 * |[0] |CLRRDY |Clear Ready 90 * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data 91 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically cleared to 0. 92 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 93 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 94 * | | |This bit is written 1 only and is always 0 when it is read back. 95 * |[1] |SSTALL |Set STALL 96 * | | |0 = Disable the device to response STALL. 97 * | | |1 = Set the device to respond STALL automatically. 98 */ 99 __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */ 100 __IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */ 101 __IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */ 102 __IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */ 103 104 } USBD_EP_T; 105 typedef struct 106 { 107 108 109 /** 110 * @var USBD_T::INTEN 111 * Offset: 0x00 USB Device Interrupt Enable Register 112 * --------------------------------------------------------------------------------------------------- 113 * |Bits |Field |Descriptions 114 * | :----: | :----: | :---- | 115 * |[0] |BUSIEN |Bus Event Interrupt Enable Bit 116 * | | |0 = BUS event interrupt Disabled. 117 * | | |1 = BUS event interrupt Enabled. 118 * |[1] |USBIEN |USB Event Interrupt Enable Bit 119 * | | |0 = USB event interrupt Disabled. 120 * | | |1 = USB event interrupt Enabled. 121 * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit 122 * | | |0 = VBUS detection Interrupt Disabled. 123 * | | |1 = VBUS detection Interrupt Enabled. 124 * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit 125 * | | |0 = No-event-wake-up Interrupt Disabled. 126 * | | |1 = No-event-wake-up Interrupt Enabled. 127 * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit 128 * | | |0 = SOF Interrupt Disabled. 129 * | | |1 = SOF Interrupt Enabled. 130 * |[8] |WKEN |Wake-up Function Enable Bit 131 * | | |0 = USB wake-up function Disabled. 132 * | | |1 = USB wake-up function Enabled. 133 * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token 134 * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. 135 * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. 136 * @var USBD_T::INTSTS 137 * Offset: 0x04 USB Device Interrupt Event Status Register 138 * --------------------------------------------------------------------------------------------------- 139 * |Bits |Field |Descriptions 140 * | :----: | :----: | :---- | 141 * |[0] |BUSIF |BUS Interrupt Status 142 * | | |The BUS event means that there is one of the suspense or the resume function in the bus. 143 * | | |0 = No BUS event occurred. 144 * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USBD_INTSTS[0]. 145 * |[1] |USBIF |USB Event Interrupt Status 146 * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. 147 * | | |0 = No USB event occurred. 148 * | | |1 = USB event occurred 149 * | | |Check EPSTS0~25 in USBD_EPSTS0~3 to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or USBD_INTSTS[27:16] or USBD_EPINTSTS[24:0] and SETUP (USBD_INTSTS[31]). 150 * |[2] |VBDETIF |VBUS Detection Interrupt Status 151 * | | |0 = There is not attached/detached event in the USB. 152 * | | |1 = There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2]. 153 * |[3] |NEVWKIF |No-event-wake-up Interrupt Status 154 * | | |0 = NEVWK event did not occur. 155 * | | |1 = No-event-wake-up event occurred, cleared by writing 1 to USBD_INTSTS[3]. 156 * |[4] |SOFIF |Start of Frame Interrupt Status 157 * | | |0 = SOF event did not occur. 158 * | | |1 = SOF event occurred, cleared by writing 1 to USBD_INTSTS[4]. 159 * |[16] |EPEVT0 |Endpoint 0's USB Event Status 160 * | | |0 = No event occurred in endpoint 0. 161 * | | |1 = USB event occurred on Endpoint 0 162 * | | |Check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[16] or USBD_EPINTSTS[0] or USBD_INTSTS[1]. 163 * |[17] |EPEVT1 |Endpoint 1's USB Event Status 164 * | | |0 = No event occurred in endpoint 1. 165 * | | |1 = USB event occurred on Endpoint 1 166 * | | |Check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[17] or USBD_EPINTSTS[1] or USBD_INTSTS[1]. 167 * |[18] |EPEVT2 |Endpoint 2's USB Event Status 168 * | | |0 = No event occurred in endpoint 2. 169 * | | |1 = USB event occurred on Endpoint 2 170 * | | |Check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[18] or USBD_EPINTSTS[2] or USBD_INTSTS[1]. 171 * |[19] |EPEVT3 |Endpoint 3's USB Event Status 172 * | | |0 = No event occurred in endpoint 3. 173 * | | |1 = USB event occurred on Endpoint 3 174 * | | |Check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[19] or USBD_EPINTSTS[3] or USBD_INTSTS[1]. 175 * |[20] |EPEVT4 |Endpoint 4's USB Event Status 176 * | | |0 = No event occurred in endpoint 4. 177 * | | |1 = USB event occurred on Endpoint 4 178 * | | |Check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[20] or USBD_EPINTSTS[4] or USBD_INTSTS[1]. 179 * |[21] |EPEVT5 |Endpoint 5's USB Event Status 180 * | | |0 = No event occurred in endpoint 5. 181 * | | |1 = USB event occurred on Endpoint 5 182 * | | |Check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[21] or USBD_EPINTSTS[5] or USBD_INTSTS[1]. 183 * |[22] |EPEVT6 |Endpoint 6's USB Event Status 184 * | | |0 = No event occurred in endpoint 6. 185 * | | |1 = USB event occurred on Endpoint 6 186 * | | |Check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_EPINTSTS[6] or USBD_INTSTS[1]. 187 * |[23] |EPEVT7 |Endpoint 7's USB Event Status 188 * | | |0 = No event occurred in endpoint 7. 189 * | | |1 = USB event occurred on Endpoint 7 190 * | | |Check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[23] or USBD_EPINTSTS[7] or USBD_INTSTS[1]. 191 * |[24] |EPEVT8 |Endpoint 8's USB Event Status 192 * | | |0 = No event occurred in endpoint 8. 193 * | | |1 = USB event occurred on Endpoint 8 194 * | | |Check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[24] or USBD_EPINTSTS[8] or USBD_INTSTS[1]. 195 * |[25] |EPEVT9 |Endpoint 9's USB Event Status 196 * | | |0 = No event occurred in endpoint 9. 197 * | | |1 = USB event occurred on Endpoint 9 198 * | | |Check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[25] or USBD_EPINTSTS[9] or USBD_INTSTS[1]. 199 * |[26] |EPEVT10 |Endpoint 10's USB Event Status 200 * | | |0 = No event occurred in endpoint 10. 201 * | | |1 = USB event occurred on Endpoint 10 202 * | | |Check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[26] or USBD_EPINTSTS[10] or USBD_INTSTS[1]. 203 * |[27] |EPEVT11 |Endpoint 11's USB Event Status 204 * | | |0 = No event occurred in endpoint 11. 205 * | | |1 = USB event occurred on Endpoint 11 206 * | | |Check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[27] or USBD_EPINTSTS[11] or USBD_INTSTS[1]. 207 * |[31] |SETUP |Setup Event Status 208 * | | |0 = No Setup event. 209 * | | |1 = Setup event occurred, cleared by writing 1 to USBD_INTSTS[31]. 210 * @var USBD_T::FADDR 211 * Offset: 0x08 USB Device Function Address Register 212 * --------------------------------------------------------------------------------------------------- 213 * |Bits |Field |Descriptions 214 * | :----: | :----: | :---- | 215 * |[6:0] |FADDR |USB device function address 216 * @var USBD_T::EPSTS 217 * Offset: 0x0C USB Device Endpoint Status Register 218 * --------------------------------------------------------------------------------------------------- 219 * |Bits |Field |Descriptions 220 * | :----: | :----: | :---- | 221 * |[7] |OV |Overrun 222 * | | |It indicates that the received data is over the maximum payload number or not. 223 * | | |0 = No overrun. 224 * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 bytes. 225 * @var USBD_T::ATTR 226 * Offset: 0x10 USB Device Bus Status and Attribution Register 227 * --------------------------------------------------------------------------------------------------- 228 * |Bits |Field |Descriptions 229 * | :----: | :----: | :---- | 230 * |[0] |USBRST |USB Reset Status (Read Only) 231 * | | |0 = Bus no reset. 232 * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. 233 * |[1] |SUSPEND |Suspend Status (Read Only) 234 * | | |0 = Bus no suspend. 235 * | | |1 = Bus idle more than 3ms, either cable is plugged-out or host is sleeping. 236 * |[2] |RESUME |Resume Status (Read Only) 237 * | | |0 = No bus resume. 238 * | | |1 = Resume from suspend. 239 * |[3] |TOUT |Time-out Status (Read Only) 240 * | | |0 = No time-out. 241 * | | |1 = No Bus response more than 18 bits time. 242 * |[4] |PHYEN |PHY Transceiver Function Enable Bit 243 * | | |0 = PHY transceiver function Disabled. 244 * | | |1 = PHY transceiver function Enabled. 245 * |[5] |RWAKEUP |Remote Wake-up 246 * | | |0 = Release the USB bus from K state. 247 * | | |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up. 248 * |[7] |USBEN |USB Controller Enable Bit 249 * | | |0 = USB Controller Disabled. 250 * | | |1 = USB Controller Enabled. 251 * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit 252 * | | |0 = Pull-up resistor in USB_D+ bus Disabled. 253 * | | |1 = Pull-up resistor in USB_D+ bus Active. 254 * |[9] |PWRDN |Power-down PHY Transceiver, Low Active 255 * | | |0 = Power-down related circuit of PHY transceiver. 256 * | | |1 = Turn-on related circuit of PHY transceiver. 257 * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection 258 * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. 259 * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. 260 * |[11] |LPMACK |LPM Token Acknowledge Enable Bit 261 * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. 262 * | | |0= The valid LPM Token will be NYET. 263 * | | |1= The valid LPM Token will be ACK. 264 * |[12] |L1SUSPEND |LPM L1 Suspend (Read Only) 265 * | | |0 = Bus no L1 state suspend. 266 * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged 267 * |[13] |L1RESUME |LPM L1 Resume (Read Only) 268 * | | |0 = Bus no LPM L1 state resume. 269 * | | |1 = LPM L1 state resume from LPM L1 state suspend. 270 * @var USBD_T::VBUSDET 271 * Offset: 0x14 USB Device VBUS Detection Register 272 * --------------------------------------------------------------------------------------------------- 273 * |Bits |Field |Descriptions 274 * | :----: | :----: | :---- | 275 * |[0] |VBUSDET |Device VBUS Detection 276 * | | |0 = Controller is not attached to the USB host. 277 * | | |1 = Controller is attached to the USB host. 278 * @var USBD_T::STBUFSEG 279 * Offset: 0x18 SETUP Token Buffer Segmentation Register 280 * --------------------------------------------------------------------------------------------------- 281 * |Bits |Field |Descriptions 282 * | :----: | :----: | :---- | 283 * |[10:3] |STBUFSEG |SETUP Token Buffer Segmentation 284 * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address 285 * | | |The effective starting address is 286 * | | |USBD_SRAM address + {STBUFSEG, 3'b000} 287 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 288 * | | |Note: It is used for SETUP token only. 289 * @var USBD_T::EPSTS0 290 * Offset: 0x20 USB Device Endpoint Status Register 0 291 * --------------------------------------------------------------------------------------------------- 292 * |Bits |Field |Descriptions 293 * | :----: | :----: | :---- | 294 * |[03:00] |EPSTS0 |Endpoint 0 Status 295 * | | |These bits are used to indicate the current status of this endpoint 296 * | | |0000 = In ACK. 297 * | | |0001 = In NAK. 298 * | | |0010 = Out Packet Data0 ACK. 299 * | | |0011 = Setup ACK. 300 * | | |0110 = Out Packet Data1 ACK. 301 * | | |0111 = Isochronous transfer end. 302 * |[07:04] |EPSTS1 |Endpoint 1 Status 303 * | | |These bits are used to indicate the current status of this endpoint 304 * | | |0000 = In ACK. 305 * | | |0001 = In NAK. 306 * | | |0010 = Out Packet Data0 ACK. 307 * | | |0011 = Setup ACK. 308 * | | |0110 = Out Packet Data1 ACK. 309 * | | |0111 = Isochronous transfer end. 310 * |[11:08] |EPSTS2 |Endpoint 2 Status 311 * | | |These bits are used to indicate the current status of this endpoint 312 * | | |0000 = In ACK. 313 * | | |0001 = In NAK. 314 * | | |0010 = Out Packet Data0 ACK. 315 * | | |0011 = Setup ACK. 316 * | | |0110 = Out Packet Data1 ACK. 317 * | | |0111 = Isochronous transfer end. 318 * |[15:12] |EPSTS3 |Endpoint 3 Status 319 * | | |These bits are used to indicate the current status of this endpoint 320 * | | |0000 = In ACK. 321 * | | |0001 = In NAK. 322 * | | |0010 = Out Packet Data0 ACK. 323 * | | |0011 = Setup ACK. 324 * | | |0110 = Out Packet Data1 ACK. 325 * | | |0111 = Isochronous transfer end. 326 * |[19:16] |EPSTS4 |Endpoint 4 Status 327 * | | |These bits are used to indicate the current status of this endpoint 328 * | | |0000 = In ACK. 329 * | | |0001 = In NAK. 330 * | | |0010 = Out Packet Data0 ACK. 331 * | | |0011 = Setup ACK. 332 * | | |0110 = Out Packet Data1 ACK. 333 * | | |0111 = Isochronous transfer end. 334 * |[23:20] |EPSTS5 |Endpoint 5 Status 335 * | | |These bits are used to indicate the current status of this endpoint 336 * | | |0000 = In ACK. 337 * | | |0001 = In NAK. 338 * | | |0010 = Out Packet Data0 ACK. 339 * | | |0011 = Setup ACK. 340 * | | |0110 = Out Packet Data1 ACK. 341 * | | |0111 = Isochronous transfer end. 342 * |[27:24] |EPSTS6 |Endpoint 6 Status 343 * | | |These bits are used to indicate the current status of this endpoint 344 * | | |0000 = In ACK. 345 * | | |0001 = In NAK. 346 * | | |0010 = Out Packet Data0 ACK. 347 * | | |0011 = Setup ACK. 348 * | | |0110 = Out Packet Data1 ACK. 349 * | | |0111 = Isochronous transfer end. 350 * |[31:28] |EPSTS7 |Endpoint 7 Status 351 * | | |These bits are used to indicate the current status of this endpoint 352 * | | |0000 = In ACK. 353 * | | |0001 = In NAK. 354 * | | |0010 = Out Packet Data0 ACK. 355 * | | |0011 = Setup ACK. 356 * | | |0110 = Out Packet Data1 ACK. 357 * | | |0111 = Isochronous transfer end. 358 * @var USBD_T::EPSTS1 359 * Offset: 0x24 USB Device Endpoint Status Register 1 360 * --------------------------------------------------------------------------------------------------- 361 * |Bits |Field |Descriptions 362 * | :----: | :----: | :---- | 363 * |[3:0] |EPSTS8 |Endpoint 8 Status 364 * | | |These bits are used to indicate the current status of this endpoint 365 * | | |0000 = In ACK. 366 * | | |0001 = In NAK. 367 * | | |0010 = Out Packet Data0 ACK. 368 * | | |0011 = Setup ACK. 369 * | | |0110 = Out Packet Data1 ACK. 370 * | | |0111 = Isochronous transfer end. 371 * |[7:4] |EPSTS9 |Endpoint 9 Status 372 * | | |These bits are used to indicate the current status of this endpoint 373 * | | |0000 = In ACK. 374 * | | |0001 = In NAK. 375 * | | |0010 = Out Packet Data0 ACK. 376 * | | |0011 = Setup ACK. 377 * | | |0110 = Out Packet Data1 ACK. 378 * | | |0111 = Isochronous transfer end. 379 * |[11:8] |EPSTS10 |Endpoint 10 Status 380 * | | |These bits are used to indicate the current status of this endpoint 381 * | | |0000 = In ACK. 382 * | | |0001 = In NAK. 383 * | | |0010 = Out Packet Data0 ACK. 384 * | | |0011 = Setup ACK. 385 * | | |0110 = Out Packet Data1 ACK. 386 * | | |0111 = Isochronous transfer end. 387 * |[15:12] |EPSTS11 |Endpoint 11 Status 388 * | | |These bits are used to indicate the current status of this endpoint 389 * | | |0000 = In ACK. 390 * | | |0001 = In NAK. 391 * | | |0010 = Out Packet Data0 ACK. 392 * | | |0011 = Setup ACK. 393 * | | |0110 = Out Packet Data1 ACK. 394 * | | |0111 = Isochronous transfer end. 395 * @var USBD_T::EPSTS2 396 * Offset: 0x28 USB Device Endpoint Status Register 2 397 * --------------------------------------------------------------------------------------------------- 398 * |Bits |Field |Descriptions 399 * | :----: | :----: | :---- | 400 * |[3:0] |EPSTS16 |Endpoint 16 Status 401 * | | |These bits are used to indicate the current status of this endpoint. 402 * | | |0000 = In ACK. 403 * | | |0001 = In NAK. 404 * | | |0010 = Out Packet Data0 ACK. 405 * | | |0110 = Out Packet Data1 ACK. 406 * | | |0111 = Isochronous transfer end. 407 * |[7:4] |EPSTS17 |Endpoint 17 Status 408 * | | |These bits are used to indicate the current status of this endpoint. 409 * | | |0000 = In ACK. 410 * | | |0001 = In NAK. 411 * | | |0010 = Out Packet Data0 ACK. 412 * | | |0110 = Out Packet Data1 ACK. 413 * | | |0111 = Isochronous transfer end. 414 * |[11:8] |EPSTS18 |Endpoint 18 Status 415 * | | |These bits are used to indicate the current status of this endpoint. 416 * | | |0000 = In ACK. 417 * | | |0001 = In NAK. 418 * | | |0010 = Out Packet Data0 ACK. 419 * | | |0110 = Out Packet Data1 ACK. 420 * | | |0111 = Isochronous transfer end. 421 * @var USBD_T::EPINTSTS 422 * Offset: 0x30 USB Device Endpoint Interrupt Event Status Register 423 * --------------------------------------------------------------------------------------------------- 424 * |Bits |Field |Descriptions 425 * | :----: | :----: | :---- | 426 * |[0] |EPEVT0 |Endpoint 0's USB Event Status 427 * | | |0 = No event occurred in endpoint 0. 428 * | | |1 = USB event occurred on Endpoint 0 429 * | | |Check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[0] or USBD_INTSTS[16] or USBD_INTSTS[1]. 430 * |[1] |EPEVT1 |Endpoint 1's USB Event Status 431 * | | |0 = No event occurred in endpoint 1. 432 * | | |1 = USB event occurred on Endpoint 1 433 * | | |Check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[1] or USBD_INTSTS[17] or USBD_INTSTS[1]. 434 * |[2] |EPEVT2 |Endpoint 2's USB Event Status 435 * | | |0 = No event occurred in endpoint 2. 436 * | | |1 = USB event occurred on Endpoint 2 437 * | | |Check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[2] or USBD_EPINTSTS[2] or USBD_INTSTS[18] or USBD_INTSTS[1]. 438 * |[3] |EPEVT3 |Endpoint 3's USB Event Status 439 * | | |0 = No event occurred in endpoint 3. 440 * | | |1 = USB event occurred on Endpoint 3 441 * | | |Check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[3] or USBD_INTSTS[19] or USBD_INTSTS[1]. 442 * |[4] |EPEVT4 |Endpoint 4's USB Event Status 443 * | | |0 = No event occurred in endpoint 4. 444 * | | |1 = USB event occurred on Endpoint 4 445 * | | |Check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[4] or USBD_INTSTS[20] or USBD_INTSTS[1]. 446 * |[5] |EPEVT5 |Endpoint 5's USB Event Status 447 * | | |0 = No event occurred in endpoint 5. 448 * | | |1 = USB event occurred on Endpoint 5 449 * | | |Check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[5] or USBD_INTSTS[21] or USBD_INTSTS[1]. 450 * |[6] |EPEVT6 |Endpoint 6's USB Event Status 451 * | | |0 = No event occurred in endpoint 6. 452 * | | |1 = USB event occurred on Endpoint 6 453 * | | |Check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[6] or USBD_INTSTS[22] or USBD_INTSTS[1]. 454 * |[7] |EPEVT7 |Endpoint 7's USB Event Status 455 * | | |0 = No event occurred in endpoint 7. 456 * | | |1 = USB event occurred on Endpoint 7 457 * | | |Check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[7] or USBD_INTSTS[23] or USBD_INTSTS[1]. 458 * |[8] |EPEVT8 |Endpoint 8's USB Event Status 459 * | | |0 = No event occurred in endpoint 8. 460 * | | |1 = USB event occurred on Endpoint 8 461 * | | |Check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[8] or USBD_INTSTS[24] or USBD_INTSTS[1]. 462 * |[9] |EPEVT9 |Endpoint 9's USB Event Status 463 * | | |0 = No event occurred in endpoint 9. 464 * | | |1 = USB event occurred on Endpoint 9 465 * | | |Check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[9] or USBD_INTSTS[25] or USBD_INTSTS[1]. 466 * |[10] |EPEVT10 |Endpoint 10's USB Event Status 467 * | | |0 = No event occurred in endpoint 10. 468 * | | |1 = USB event occurred on Endpoint 10 469 * | | |Check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[10] or USBD_INTSTS[26] or USBD_INTSTS[1]. 470 * |[11] |EPEVT11 |Endpoint 11's USB Event Status 471 * | | |0 = No event occurred in endpoint 11. 472 * | | |1 = USB event occurred on Endpoint 11 473 * | | |Check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[11] or USBD_INTSTS[27] or USBD_INTSTS[1]. 474 * |[12] |EPEVT12 |Endpoint 12's USB Event Status 475 * | | |0 = No event occurred in endpoint 12. 476 * | | |1 = USB event occurred on Endpoint 12 477 * | | |Check USBD_EPSTS1[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[12] or USBD_INTSTS[1]. 478 * |[13] |EPEVT13 |Endpoint 13's USB Event Status 479 * | | |0 = No event occurred in endpoint 13. 480 * | | |1 = USB event occurred on Endpoint 13 481 * | | |Check USBD_EPSTS1[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[13] or USBD_INTSTS[1]. 482 * |[14] |EPEVT14 |Endpoint 14's USB Event Status 483 * | | |0 = No event occurred in endpoint 14. 484 * | | |1 = USB event occurred on Endpoint 14 485 * | | |Check USBD_EPSTS1[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[14] or USBD_INTSTS[1]. 486 * |[15] |EPEVT15 |Endpoint 15's USB Event Status 487 * | | |0 = No event occurred in endpoint 15. 488 * | | |1 = USB event occurred on Endpoint 15 489 * | | |Check USBD_EPSTS1[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[15] or USBD_INTSTS[1]. 490 * |[16] |EPEVT16 |Endpoint 16's USB Event Status 491 * | | |0 = No event occurred in endpoint 16. 492 * | | |1 = USB event occurred on Endpoint 16 493 * | | |Check USBD_EPSTS2[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[16] or USBD_INTSTS[1]. 494 * |[17] |EPEVT17 |Endpoint 17's USB Event Status 495 * | | |0 = No event occurred in endpoint 17. 496 * | | |1 = USB event occurred on Endpoint 17 497 * | | |Check USBD_EPSTS2[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[17] or USBD_INTSTS[1]. 498 * |[18] |EPEVT18 |Endpoint 18's USB Event Status 499 * | | |0 = No event occurred in endpoint 18. 500 * | | |1 = USB event occurred on Endpoint 18 501 * | | |Check USBD_EPSTS2[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_EPINTSTS[18] or USBD_INTSTS[1]. 502 * @var USBD_T::LPMATTR 503 * Offset: 0x88 USB LPM Attribution Register 504 * --------------------------------------------------------------------------------------------------- 505 * |Bits |Field |Descriptions 506 * | :----: | :----: | :---- | 507 * |[3:0] |LPMLINKSTS|LPM Link State 508 * | | |These bits contain the bLinkState received with last ACK LPM Token 509 * |[7:4] |LPMBESL |LPM Best Effort Service Latency 510 * | | |These bits contain the BESL value received with last ACK LPM Token 511 * |[8] |LPMRWAKUP |LPM Remote Wakeup 512 * | | |This bit contains the bRemoteWake value received with last ACK LPM Token 513 * @var USBD_T::FN 514 * Offset: 0x8C USB Frame Number Register 515 * --------------------------------------------------------------------------------------------------- 516 * |Bits |Field |Descriptions 517 * | :----: | :----: | :---- | 518 * |[10:0] |FN |Frame Number 519 * | | |These bits contain the 11-bits frame number in the last received SOF packet. 520 * @var USBD_T::SE0 521 * Offset: 0x90 USB Device Drive SE0 Control Register 522 * --------------------------------------------------------------------------------------------------- 523 * |Bits |Field |Descriptions 524 * | :----: | :----: | :---- | 525 * |[0] |SE0 |Drive Single Ended Zero in USB Bus 526 * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. 527 * | | |0 = Normal operation. 528 * | | |1 = Force USB PHY transceiver to drive SE0. 529 * @var USBD_T::BUFSEG0 530 * Offset: 0x500 Endpoint 0 Buffer Segmentation Register 531 * --------------------------------------------------------------------------------------------------- 532 * |Bits |Field |Descriptions 533 * | :----: | :----: | :---- | 534 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 535 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 536 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 537 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 538 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 539 * @var USBD_T::MXPLD0 540 * Offset: 0x504 Endpoint 0 Maximal Payload Register 541 * --------------------------------------------------------------------------------------------------- 542 * |Bits |Field |Descriptions 543 * | :----: | :----: | :---- | 544 * |[10:0] |MXPLD |Maximal Payload 545 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 546 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 547 * | | |(1) When the register is written by CPU, 548 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 549 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 550 * | | |(2) When the register is read by CPU, 551 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 552 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 553 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 554 * @var USBD_T::CFG0 555 * Offset: 0x508 Endpoint 0 Configuration Register 556 * --------------------------------------------------------------------------------------------------- 557 * |Bits |Field |Descriptions 558 * | :----: | :----: | :---- | 559 * |[3:0] |EPNUM |Endpoint Number 560 * | | |These bits are used to define the endpoint number of the current endpoint. 561 * |[4] |ISOCH |Isochronous Endpoint 562 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 563 * | | |0 = No Isochronous endpoint. 564 * | | |1 = Isochronous endpoint. 565 * |[6:5] |STATE |Endpoint State 566 * | | |00 = Endpoint is Disabled. 567 * | | |01 = Out endpoint. 568 * | | |10 = IN endpoint. 569 * | | |11 = Undefined. 570 * |[7] |DSQSYNC |Data Sequence Synchronization 571 * | | |0 = DATA0 PID. 572 * | | |1 = DATA1 PID. 573 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 574 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 575 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 576 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 577 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 578 * | | |USB data toggle will be guaranteed by changing endpoint. 579 * |[9] |CSTALL |Clear STALL Response 580 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 581 * | | |1 = Clear the device to response STALL handshake in setup stage. 582 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 583 * | | |0 = Inactive in double buffer mode. 584 * | | |1 = Active in double buffer mode. 585 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 586 * |[11] |DBEN |Double Buffer Enable Bit 587 * | | |0 = Single buffer mode. 588 * | | |1 = Double buffer mode. 589 * @var USBD_T::CFGP0 590 * Offset: 0x50C Endpoint 0 Set Stall and Clear In/Out Ready Control Register 591 * --------------------------------------------------------------------------------------------------- 592 * |Bits |Field |Descriptions 593 * | :----: | :----: | :---- | 594 * |[0] |CLRRDY |Clear Ready Bit 595 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 596 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 597 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 598 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 599 * | | |This bit is written 1 only and is always 0 when it is read back. 600 * |[1] |SSTALL |Set STALL Bit 601 * | | |0 = Disable the device to response STALL. 602 * | | |1 = Set the device to respond STALL automatically. 603 * @var USBD_T::BUFSEG1 604 * Offset: 0x510 Endpoint 1 Buffer Segmentation Register 605 * --------------------------------------------------------------------------------------------------- 606 * |Bits |Field |Descriptions 607 * | :----: | :----: | :---- | 608 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 609 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 610 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 611 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 612 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 613 * @var USBD_T::MXPLD1 614 * Offset: 0x514 Endpoint 1 Maximal Payload Register 615 * --------------------------------------------------------------------------------------------------- 616 * |Bits |Field |Descriptions 617 * | :----: | :----: | :---- | 618 * |[10:0] |MXPLD |Maximal Payload 619 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 620 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 621 * | | |(1) When the register is written by CPU, 622 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 623 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 624 * | | |(2) When the register is read by CPU, 625 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 626 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 627 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 628 * @var USBD_T::CFG1 629 * Offset: 0x518 Endpoint 1 Configuration Register 630 * --------------------------------------------------------------------------------------------------- 631 * |Bits |Field |Descriptions 632 * | :----: | :----: | :---- | 633 * |[3:0] |EPNUM |Endpoint Number 634 * | | |These bits are used to define the endpoint number of the current endpoint. 635 * |[4] |ISOCH |Isochronous Endpoint 636 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 637 * | | |0 = No Isochronous endpoint. 638 * | | |1 = Isochronous endpoint. 639 * |[6:5] |STATE |Endpoint State 640 * | | |00 = Endpoint is Disabled. 641 * | | |01 = Out endpoint. 642 * | | |10 = IN endpoint. 643 * | | |11 = Undefined. 644 * |[7] |DSQSYNC |Data Sequence Synchronization 645 * | | |0 = DATA0 PID. 646 * | | |1 = DATA1 PID. 647 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 648 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 649 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 650 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 651 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 652 * | | |USB data toggle will be guaranteed by changing endpoint. 653 * |[9] |CSTALL |Clear STALL Response 654 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 655 * | | |1 = Clear the device to response STALL handshake in setup stage. 656 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 657 * | | |0 = Inactive in double buffer mode. 658 * | | |1 = Active in double buffer mode. 659 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 660 * |[11] |DBEN |Double Buffer Enable Bit 661 * | | |0 = Single buffer mode. 662 * | | |1 = Double buffer mode. 663 * @var USBD_T::CFGP1 664 * Offset: 0x51C Endpoint 1 Set Stall and Clear In/Out Ready Control Register 665 * --------------------------------------------------------------------------------------------------- 666 * |Bits |Field |Descriptions 667 * | :----: | :----: | :---- | 668 * |[0] |CLRRDY |Clear Ready Bit 669 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 670 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 671 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 672 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 673 * | | |This bit is written 1 only and is always 0 when it is read back. 674 * |[1] |SSTALL |Set STALL Bit 675 * | | |0 = Disable the device to response STALL. 676 * | | |1 = Set the device to respond STALL automatically. 677 * @var USBD_T::BUFSEG2 678 * Offset: 0x520 Endpoint 2 Buffer Segmentation Register 679 * --------------------------------------------------------------------------------------------------- 680 * |Bits |Field |Descriptions 681 * | :----: | :----: | :---- | 682 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 683 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 684 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 685 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 686 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 687 * @var USBD_T::MXPLD2 688 * Offset: 0x524 Endpoint 2 Maximal Payload Register 689 * --------------------------------------------------------------------------------------------------- 690 * |Bits |Field |Descriptions 691 * | :----: | :----: | :---- | 692 * |[10:0] |MXPLD |Maximal Payload 693 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 694 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 695 * | | |(1) When the register is written by CPU, 696 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 697 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 698 * | | |(2) When the register is read by CPU, 699 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 700 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 701 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 702 * @var USBD_T::CFG2 703 * Offset: 0x528 Endpoint 2 Configuration Register 704 * --------------------------------------------------------------------------------------------------- 705 * |Bits |Field |Descriptions 706 * | :----: | :----: | :---- | 707 * |[3:0] |EPNUM |Endpoint Number 708 * | | |These bits are used to define the endpoint number of the current endpoint. 709 * |[4] |ISOCH |Isochronous Endpoint 710 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 711 * | | |0 = No Isochronous endpoint. 712 * | | |1 = Isochronous endpoint. 713 * |[6:5] |STATE |Endpoint State 714 * | | |00 = Endpoint is Disabled. 715 * | | |01 = Out endpoint. 716 * | | |10 = IN endpoint. 717 * | | |11 = Undefined. 718 * |[7] |DSQSYNC |Data Sequence Synchronization 719 * | | |0 = DATA0 PID. 720 * | | |1 = DATA1 PID. 721 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 722 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 723 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 724 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 725 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 726 * | | |USB data toggle will be guaranteed by changing endpoint. 727 * |[9] |CSTALL |Clear STALL Response 728 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 729 * | | |1 = Clear the device to response STALL handshake in setup stage. 730 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 731 * | | |0 = Inactive in double buffer mode. 732 * | | |1 = Active in double buffer mode. 733 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 734 * |[11] |DBEN |Double Buffer Enable Bit 735 * | | |0 = Single buffer mode. 736 * | | |1 = Double buffer mode. 737 * @var USBD_T::CFGP2 738 * Offset: 0x52C Endpoint 2 Set Stall and Clear In/Out Ready Control Register 739 * --------------------------------------------------------------------------------------------------- 740 * |Bits |Field |Descriptions 741 * | :----: | :----: | :---- | 742 * |[0] |CLRRDY |Clear Ready Bit 743 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 744 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 745 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 746 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 747 * | | |This bit is written 1 only and is always 0 when it is read back. 748 * |[1] |SSTALL |Set STALL Bit 749 * | | |0 = Disable the device to response STALL. 750 * | | |1 = Set the device to respond STALL automatically. 751 * @var USBD_T::BUFSEG3 752 * Offset: 0x530 Endpoint 3 Buffer Segmentation Register 753 * --------------------------------------------------------------------------------------------------- 754 * |Bits |Field |Descriptions 755 * | :----: | :----: | :---- | 756 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 757 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 758 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 759 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 760 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 761 * @var USBD_T::MXPLD3 762 * Offset: 0x534 Endpoint 3 Maximal Payload Register 763 * --------------------------------------------------------------------------------------------------- 764 * |Bits |Field |Descriptions 765 * | :----: | :----: | :---- | 766 * |[10:0] |MXPLD |Maximal Payload 767 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 768 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 769 * | | |(1) When the register is written by CPU, 770 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 771 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 772 * | | |(2) When the register is read by CPU, 773 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 774 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 775 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 776 * @var USBD_T::CFG3 777 * Offset: 0x538 Endpoint 3 Configuration Register 778 * --------------------------------------------------------------------------------------------------- 779 * |Bits |Field |Descriptions 780 * | :----: | :----: | :---- | 781 * |[3:0] |EPNUM |Endpoint Number 782 * | | |These bits are used to define the endpoint number of the current endpoint. 783 * |[4] |ISOCH |Isochronous Endpoint 784 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 785 * | | |0 = No Isochronous endpoint. 786 * | | |1 = Isochronous endpoint. 787 * |[6:5] |STATE |Endpoint State 788 * | | |00 = Endpoint is Disabled. 789 * | | |01 = Out endpoint. 790 * | | |10 = IN endpoint. 791 * | | |11 = Undefined. 792 * |[7] |DSQSYNC |Data Sequence Synchronization 793 * | | |0 = DATA0 PID. 794 * | | |1 = DATA1 PID. 795 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 796 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 797 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 798 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 799 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 800 * | | |USB data toggle will be guaranteed by changing endpoint. 801 * |[9] |CSTALL |Clear STALL Response 802 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 803 * | | |1 = Clear the device to response STALL handshake in setup stage. 804 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 805 * | | |0 = Inactive in double buffer mode. 806 * | | |1 = Active in double buffer mode. 807 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 808 * |[11] |DBEN |Double Buffer Enable Bit 809 * | | |0 = Single buffer mode. 810 * | | |1 = Double buffer mode. 811 * @var USBD_T::CFGP3 812 * Offset: 0x53C Endpoint 3 Set Stall and Clear In/Out Ready Control Register 813 * --------------------------------------------------------------------------------------------------- 814 * |Bits |Field |Descriptions 815 * | :----: | :----: | :---- | 816 * |[0] |CLRRDY |Clear Ready Bit 817 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 818 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 819 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 820 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 821 * | | |This bit is written 1 only and is always 0 when it is read back. 822 * |[1] |SSTALL |Set STALL Bit 823 * | | |0 = Disable the device to response STALL. 824 * | | |1 = Set the device to respond STALL automatically. 825 * @var USBD_T::BUFSEG4 826 * Offset: 0x540 Endpoint 4 Buffer Segmentation Register 827 * --------------------------------------------------------------------------------------------------- 828 * |Bits |Field |Descriptions 829 * | :----: | :----: | :---- | 830 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 831 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 832 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 833 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 834 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 835 * @var USBD_T::MXPLD4 836 * Offset: 0x544 Endpoint 4 Maximal Payload Register 837 * --------------------------------------------------------------------------------------------------- 838 * |Bits |Field |Descriptions 839 * | :----: | :----: | :---- | 840 * |[10:0] |MXPLD |Maximal Payload 841 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 842 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 843 * | | |(1) When the register is written by CPU, 844 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 845 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 846 * | | |(2) When the register is read by CPU, 847 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 848 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 849 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 850 * @var USBD_T::CFG4 851 * Offset: 0x548 Endpoint 4 Configuration Register 852 * --------------------------------------------------------------------------------------------------- 853 * |Bits |Field |Descriptions 854 * | :----: | :----: | :---- | 855 * |[3:0] |EPNUM |Endpoint Number 856 * | | |These bits are used to define the endpoint number of the current endpoint. 857 * |[4] |ISOCH |Isochronous Endpoint 858 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 859 * | | |0 = No Isochronous endpoint. 860 * | | |1 = Isochronous endpoint. 861 * |[6:5] |STATE |Endpoint State 862 * | | |00 = Endpoint is Disabled. 863 * | | |01 = Out endpoint. 864 * | | |10 = IN endpoint. 865 * | | |11 = Undefined. 866 * |[7] |DSQSYNC |Data Sequence Synchronization 867 * | | |0 = DATA0 PID. 868 * | | |1 = DATA1 PID. 869 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 870 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 871 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 872 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 873 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 874 * | | |USB data toggle will be guaranteed by changing endpoint. 875 * |[9] |CSTALL |Clear STALL Response 876 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 877 * | | |1 = Clear the device to response STALL handshake in setup stage. 878 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 879 * | | |0 = Inactive in double buffer mode. 880 * | | |1 = Active in double buffer mode. 881 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 882 * |[11] |DBEN |Double Buffer Enable Bit 883 * | | |0 = Single buffer mode. 884 * | | |1 = Double buffer mode. 885 * @var USBD_T::CFGP4 886 * Offset: 0x54C Endpoint 4 Set Stall and Clear In/Out Ready Control Register 887 * --------------------------------------------------------------------------------------------------- 888 * |Bits |Field |Descriptions 889 * | :----: | :----: | :---- | 890 * |[0] |CLRRDY |Clear Ready Bit 891 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 892 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 893 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 894 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 895 * | | |This bit is written 1 only and is always 0 when it is read back. 896 * |[1] |SSTALL |Set STALL Bit 897 * | | |0 = Disable the device to response STALL. 898 * | | |1 = Set the device to respond STALL automatically. 899 * @var USBD_T::BUFSEG5 900 * Offset: 0x550 Endpoint 5 Buffer Segmentation Register 901 * --------------------------------------------------------------------------------------------------- 902 * |Bits |Field |Descriptions 903 * | :----: | :----: | :---- | 904 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 905 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 906 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 907 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 908 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 909 * @var USBD_T::MXPLD5 910 * Offset: 0x554 Endpoint 5 Maximal Payload Register 911 * --------------------------------------------------------------------------------------------------- 912 * |Bits |Field |Descriptions 913 * | :----: | :----: | :---- | 914 * |[10:0] |MXPLD |Maximal Payload 915 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 916 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 917 * | | |(1) When the register is written by CPU, 918 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 919 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 920 * | | |(2) When the register is read by CPU, 921 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 922 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 923 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 924 * @var USBD_T::CFG5 925 * Offset: 0x558 Endpoint 5 Configuration Register 926 * --------------------------------------------------------------------------------------------------- 927 * |Bits |Field |Descriptions 928 * | :----: | :----: | :---- | 929 * |[3:0] |EPNUM |Endpoint Number 930 * | | |These bits are used to define the endpoint number of the current endpoint. 931 * |[4] |ISOCH |Isochronous Endpoint 932 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 933 * | | |0 = No Isochronous endpoint. 934 * | | |1 = Isochronous endpoint. 935 * |[6:5] |STATE |Endpoint State 936 * | | |00 = Endpoint is Disabled. 937 * | | |01 = Out endpoint. 938 * | | |10 = IN endpoint. 939 * | | |11 = Undefined. 940 * |[7] |DSQSYNC |Data Sequence Synchronization 941 * | | |0 = DATA0 PID. 942 * | | |1 = DATA1 PID. 943 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 944 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 945 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 946 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 947 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 948 * | | |USB data toggle will be guaranteed by changing endpoint. 949 * |[9] |CSTALL |Clear STALL Response 950 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 951 * | | |1 = Clear the device to response STALL handshake in setup stage. 952 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 953 * | | |0 = Inactive in double buffer mode. 954 * | | |1 = Active in double buffer mode. 955 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 956 * |[11] |DBEN |Double Buffer Enable Bit 957 * | | |0 = Single buffer mode. 958 * | | |1 = Double buffer mode. 959 * @var USBD_T::CFGP5 960 * Offset: 0x55C Endpoint 5 Set Stall and Clear In/Out Ready Control Register 961 * --------------------------------------------------------------------------------------------------- 962 * |Bits |Field |Descriptions 963 * | :----: | :----: | :---- | 964 * |[0] |CLRRDY |Clear Ready Bit 965 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 966 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 967 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 968 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 969 * | | |This bit is written 1 only and is always 0 when it is read back. 970 * |[1] |SSTALL |Set STALL Bit 971 * | | |0 = Disable the device to response STALL. 972 * | | |1 = Set the device to respond STALL automatically. 973 * @var USBD_T::BUFSEG6 974 * Offset: 0x560 Endpoint 6 Buffer Segmentation Register 975 * --------------------------------------------------------------------------------------------------- 976 * |Bits |Field |Descriptions 977 * | :----: | :----: | :---- | 978 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 979 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 980 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 981 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 982 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 983 * @var USBD_T::MXPLD6 984 * Offset: 0x564 Endpoint 6 Maximal Payload Register 985 * --------------------------------------------------------------------------------------------------- 986 * |Bits |Field |Descriptions 987 * | :----: | :----: | :---- | 988 * |[10:0] |MXPLD |Maximal Payload 989 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 990 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 991 * | | |(1) When the register is written by CPU, 992 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 993 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 994 * | | |(2) When the register is read by CPU, 995 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 996 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 997 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 998 * @var USBD_T::CFG6 999 * Offset: 0x568 Endpoint 6 Configuration Register 1000 * --------------------------------------------------------------------------------------------------- 1001 * |Bits |Field |Descriptions 1002 * | :----: | :----: | :---- | 1003 * |[3:0] |EPNUM |Endpoint Number 1004 * | | |These bits are used to define the endpoint number of the current endpoint. 1005 * |[4] |ISOCH |Isochronous Endpoint 1006 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1007 * | | |0 = No Isochronous endpoint. 1008 * | | |1 = Isochronous endpoint. 1009 * |[6:5] |STATE |Endpoint State 1010 * | | |00 = Endpoint is Disabled. 1011 * | | |01 = Out endpoint. 1012 * | | |10 = IN endpoint. 1013 * | | |11 = Undefined. 1014 * |[7] |DSQSYNC |Data Sequence Synchronization 1015 * | | |0 = DATA0 PID. 1016 * | | |1 = DATA1 PID. 1017 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1018 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1019 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1020 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1021 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1022 * | | |USB data toggle will be guaranteed by changing endpoint. 1023 * |[9] |CSTALL |Clear STALL Response 1024 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1025 * | | |1 = Clear the device to response STALL handshake in setup stage. 1026 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1027 * | | |0 = Inactive in double buffer mode. 1028 * | | |1 = Active in double buffer mode. 1029 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1030 * |[11] |DBEN |Double Buffer Enable Bit 1031 * | | |0 = Single buffer mode. 1032 * | | |1 = Double buffer mode. 1033 * @var USBD_T::CFGP6 1034 * Offset: 0x56C Endpoint 6 Set Stall and Clear In/Out Ready Control Register 1035 * --------------------------------------------------------------------------------------------------- 1036 * |Bits |Field |Descriptions 1037 * | :----: | :----: | :---- | 1038 * |[0] |CLRRDY |Clear Ready Bit 1039 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1040 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1041 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1042 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1043 * | | |This bit is written 1 only and is always 0 when it is read back. 1044 * |[1] |SSTALL |Set STALL Bit 1045 * | | |0 = Disable the device to response STALL. 1046 * | | |1 = Set the device to respond STALL automatically. 1047 * @var USBD_T::BUFSEG7 1048 * Offset: 0x570 Endpoint 7 Buffer Segmentation Register 1049 * --------------------------------------------------------------------------------------------------- 1050 * |Bits |Field |Descriptions 1051 * | :----: | :----: | :---- | 1052 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1053 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1054 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1055 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1056 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1057 * @var USBD_T::MXPLD7 1058 * Offset: 0x574 Endpoint 7 Maximal Payload Register 1059 * --------------------------------------------------------------------------------------------------- 1060 * |Bits |Field |Descriptions 1061 * | :----: | :----: | :---- | 1062 * |[10:0] |MXPLD |Maximal Payload 1063 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1064 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1065 * | | |(1) When the register is written by CPU, 1066 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1067 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1068 * | | |(2) When the register is read by CPU, 1069 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1070 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1071 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1072 * @var USBD_T::CFG7 1073 * Offset: 0x578 Endpoint 7 Configuration Register 1074 * --------------------------------------------------------------------------------------------------- 1075 * |Bits |Field |Descriptions 1076 * | :----: | :----: | :---- | 1077 * |[3:0] |EPNUM |Endpoint Number 1078 * | | |These bits are used to define the endpoint number of the current endpoint. 1079 * |[4] |ISOCH |Isochronous Endpoint 1080 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1081 * | | |0 = No Isochronous endpoint. 1082 * | | |1 = Isochronous endpoint. 1083 * |[6:5] |STATE |Endpoint State 1084 * | | |00 = Endpoint is Disabled. 1085 * | | |01 = Out endpoint. 1086 * | | |10 = IN endpoint. 1087 * | | |11 = Undefined. 1088 * |[7] |DSQSYNC |Data Sequence Synchronization 1089 * | | |0 = DATA0 PID. 1090 * | | |1 = DATA1 PID. 1091 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1092 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1093 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1094 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1095 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1096 * | | |USB data toggle will be guaranteed by changing endpoint. 1097 * |[9] |CSTALL |Clear STALL Response 1098 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1099 * | | |1 = Clear the device to response STALL handshake in setup stage. 1100 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1101 * | | |0 = Inactive in double buffer mode. 1102 * | | |1 = Active in double buffer mode. 1103 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1104 * |[11] |DBEN |Double Buffer Enable Bit 1105 * | | |0 = Single buffer mode. 1106 * | | |1 = Double buffer mode. 1107 * @var USBD_T::CFGP7 1108 * Offset: 0x57C Endpoint 7 Set Stall and Clear In/Out Ready Control Register 1109 * --------------------------------------------------------------------------------------------------- 1110 * |Bits |Field |Descriptions 1111 * | :----: | :----: | :---- | 1112 * |[0] |CLRRDY |Clear Ready Bit 1113 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1114 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1115 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1116 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1117 * | | |This bit is written 1 only and is always 0 when it is read back. 1118 * |[1] |SSTALL |Set STALL Bit 1119 * | | |0 = Disable the device to response STALL. 1120 * | | |1 = Set the device to respond STALL automatically. 1121 * @var USBD_T::BUFSEG8 1122 * Offset: 0x580 Endpoint 8 Buffer Segmentation Register 1123 * --------------------------------------------------------------------------------------------------- 1124 * |Bits |Field |Descriptions 1125 * | :----: | :----: | :---- | 1126 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1127 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1128 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1129 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1130 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1131 * @var USBD_T::MXPLD8 1132 * Offset: 0x584 Endpoint 8 Maximal Payload Register 1133 * --------------------------------------------------------------------------------------------------- 1134 * |Bits |Field |Descriptions 1135 * | :----: | :----: | :---- | 1136 * |[10:0] |MXPLD |Maximal Payload 1137 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1138 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1139 * | | |(1) When the register is written by CPU, 1140 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1141 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1142 * | | |(2) When the register is read by CPU, 1143 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1144 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1145 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1146 * @var USBD_T::CFG8 1147 * Offset: 0x588 Endpoint 8 Configuration Register 1148 * --------------------------------------------------------------------------------------------------- 1149 * |Bits |Field |Descriptions 1150 * | :----: | :----: | :---- | 1151 * |[3:0] |EPNUM |Endpoint Number 1152 * | | |These bits are used to define the endpoint number of the current endpoint. 1153 * |[4] |ISOCH |Isochronous Endpoint 1154 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1155 * | | |0 = No Isochronous endpoint. 1156 * | | |1 = Isochronous endpoint. 1157 * |[6:5] |STATE |Endpoint State 1158 * | | |00 = Endpoint is Disabled. 1159 * | | |01 = Out endpoint. 1160 * | | |10 = IN endpoint. 1161 * | | |11 = Undefined. 1162 * |[7] |DSQSYNC |Data Sequence Synchronization 1163 * | | |0 = DATA0 PID. 1164 * | | |1 = DATA1 PID. 1165 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1166 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1167 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1168 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1169 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1170 * | | |USB data toggle will be guaranteed by changing endpoint. 1171 * |[9] |CSTALL |Clear STALL Response 1172 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1173 * | | |1 = Clear the device to response STALL handshake in setup stage. 1174 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1175 * | | |0 = Inactive in double buffer mode. 1176 * | | |1 = Active in double buffer mode. 1177 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1178 * |[11] |DBEN |Double Buffer Enable Bit 1179 * | | |0 = Single buffer mode. 1180 * | | |1 = Double buffer mode. 1181 * @var USBD_T::CFGP8 1182 * Offset: 0x58C Endpoint 8 Set Stall and Clear In/Out Ready Control Register 1183 * --------------------------------------------------------------------------------------------------- 1184 * |Bits |Field |Descriptions 1185 * | :----: | :----: | :---- | 1186 * |[0] |CLRRDY |Clear Ready Bit 1187 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1188 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1189 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1190 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1191 * | | |This bit is written 1 only and is always 0 when it is read back. 1192 * |[1] |SSTALL |Set STALL Bit 1193 * | | |0 = Disable the device to response STALL. 1194 * | | |1 = Set the device to respond STALL automatically. 1195 * @var USBD_T::BUFSEG9 1196 * Offset: 0x590 Endpoint 9 Buffer Segmentation Register 1197 * --------------------------------------------------------------------------------------------------- 1198 * |Bits |Field |Descriptions 1199 * | :----: | :----: | :---- | 1200 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1201 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1202 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1203 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1204 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1205 * @var USBD_T::MXPLD9 1206 * Offset: 0x594 Endpoint 9 Maximal Payload Register 1207 * --------------------------------------------------------------------------------------------------- 1208 * |Bits |Field |Descriptions 1209 * | :----: | :----: | :---- | 1210 * |[10:0] |MXPLD |Maximal Payload 1211 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1212 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1213 * | | |(1) When the register is written by CPU, 1214 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1215 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1216 * | | |(2) When the register is read by CPU, 1217 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1218 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1219 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1220 * @var USBD_T::CFG9 1221 * Offset: 0x598 Endpoint 9 Configuration Register 1222 * --------------------------------------------------------------------------------------------------- 1223 * |Bits |Field |Descriptions 1224 * | :----: | :----: | :---- | 1225 * |[3:0] |EPNUM |Endpoint Number 1226 * | | |These bits are used to define the endpoint number of the current endpoint. 1227 * |[4] |ISOCH |Isochronous Endpoint 1228 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1229 * | | |0 = No Isochronous endpoint. 1230 * | | |1 = Isochronous endpoint. 1231 * |[6:5] |STATE |Endpoint State 1232 * | | |00 = Endpoint is Disabled. 1233 * | | |01 = Out endpoint. 1234 * | | |10 = IN endpoint. 1235 * | | |11 = Undefined. 1236 * |[7] |DSQSYNC |Data Sequence Synchronization 1237 * | | |0 = DATA0 PID. 1238 * | | |1 = DATA1 PID. 1239 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1240 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1241 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1242 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1243 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1244 * | | |USB data toggle will be guaranteed by changing endpoint. 1245 * |[9] |CSTALL |Clear STALL Response 1246 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1247 * | | |1 = Clear the device to response STALL handshake in setup stage. 1248 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1249 * | | |0 = Inactive in double buffer mode. 1250 * | | |1 = Active in double buffer mode. 1251 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1252 * |[11] |DBEN |Double Buffer Enable Bit 1253 * | | |0 = Single buffer mode. 1254 * | | |1 = Double buffer mode. 1255 * @var USBD_T::CFGP9 1256 * Offset: 0x59C Endpoint 9 Set Stall and Clear In/Out Ready Control Register 1257 * --------------------------------------------------------------------------------------------------- 1258 * |Bits |Field |Descriptions 1259 * | :----: | :----: | :---- | 1260 * |[0] |CLRRDY |Clear Ready Bit 1261 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1262 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1263 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1264 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1265 * | | |This bit is written 1 only and is always 0 when it is read back. 1266 * |[1] |SSTALL |Set STALL Bit 1267 * | | |0 = Disable the device to response STALL. 1268 * | | |1 = Set the device to respond STALL automatically. 1269 * @var USBD_T::BUFSEG10 1270 * Offset: 0x5A0 Endpoint 10 Buffer Segmentation Register 1271 * --------------------------------------------------------------------------------------------------- 1272 * |Bits |Field |Descriptions 1273 * | :----: | :----: | :---- | 1274 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1275 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1276 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1277 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1278 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1279 * @var USBD_T::MXPLD10 1280 * Offset: 0x5A4 Endpoint 10 Maximal Payload Register 1281 * --------------------------------------------------------------------------------------------------- 1282 * |Bits |Field |Descriptions 1283 * | :----: | :----: | :---- | 1284 * |[10:0] |MXPLD |Maximal Payload 1285 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1286 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1287 * | | |(1) When the register is written by CPU, 1288 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1289 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1290 * | | |(2) When the register is read by CPU, 1291 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1292 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1293 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1294 * @var USBD_T::CFG10 1295 * Offset: 0x5A8 Endpoint 10 Configuration Register 1296 * --------------------------------------------------------------------------------------------------- 1297 * |Bits |Field |Descriptions 1298 * | :----: | :----: | :---- | 1299 * |[3:0] |EPNUM |Endpoint Number 1300 * | | |These bits are used to define the endpoint number of the current endpoint. 1301 * |[4] |ISOCH |Isochronous Endpoint 1302 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1303 * | | |0 = No Isochronous endpoint. 1304 * | | |1 = Isochronous endpoint. 1305 * |[6:5] |STATE |Endpoint State 1306 * | | |00 = Endpoint is Disabled. 1307 * | | |01 = Out endpoint. 1308 * | | |10 = IN endpoint. 1309 * | | |11 = Undefined. 1310 * |[7] |DSQSYNC |Data Sequence Synchronization 1311 * | | |0 = DATA0 PID. 1312 * | | |1 = DATA1 PID. 1313 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1314 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1315 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1316 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1317 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1318 * | | |USB data toggle will be guaranteed by changing endpoint. 1319 * |[9] |CSTALL |Clear STALL Response 1320 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1321 * | | |1 = Clear the device to response STALL handshake in setup stage. 1322 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1323 * | | |0 = Inactive in double buffer mode. 1324 * | | |1 = Active in double buffer mode. 1325 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1326 * |[11] |DBEN |Double Buffer Enable Bit 1327 * | | |0 = Single buffer mode. 1328 * | | |1 = Double buffer mode. 1329 * @var USBD_T::CFGP10 1330 * Offset: 0x5AC Endpoint 10 Set Stall and Clear In/Out Ready Control Register 1331 * --------------------------------------------------------------------------------------------------- 1332 * |Bits |Field |Descriptions 1333 * | :----: | :----: | :---- | 1334 * |[0] |CLRRDY |Clear Ready Bit 1335 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1336 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1337 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1338 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1339 * | | |This bit is written 1 only and is always 0 when it is read back. 1340 * |[1] |SSTALL |Set STALL Bit 1341 * | | |0 = Disable the device to response STALL. 1342 * | | |1 = Set the device to respond STALL automatically. 1343 * @var USBD_T::BUFSEG11 1344 * Offset: 0x5B0 Endpoint 11 Buffer Segmentation Register 1345 * --------------------------------------------------------------------------------------------------- 1346 * |Bits |Field |Descriptions 1347 * | :----: | :----: | :---- | 1348 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1349 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1350 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1351 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1352 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1353 * @var USBD_T::MXPLD11 1354 * Offset: 0x5B4 Endpoint 11 Maximal Payload Register 1355 * --------------------------------------------------------------------------------------------------- 1356 * |Bits |Field |Descriptions 1357 * | :----: | :----: | :---- | 1358 * |[10:0] |MXPLD |Maximal Payload 1359 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1360 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1361 * | | |(1) When the register is written by CPU, 1362 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1363 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1364 * | | |(2) When the register is read by CPU, 1365 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1366 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1367 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1368 * @var USBD_T::CFG11 1369 * Offset: 0x5B8 Endpoint 11 Configuration Register 1370 * --------------------------------------------------------------------------------------------------- 1371 * |Bits |Field |Descriptions 1372 * | :----: | :----: | :---- | 1373 * |[3:0] |EPNUM |Endpoint Number 1374 * | | |These bits are used to define the endpoint number of the current endpoint. 1375 * |[4] |ISOCH |Isochronous Endpoint 1376 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1377 * | | |0 = No Isochronous endpoint. 1378 * | | |1 = Isochronous endpoint. 1379 * |[6:5] |STATE |Endpoint State 1380 * | | |00 = Endpoint is Disabled. 1381 * | | |01 = Out endpoint. 1382 * | | |10 = IN endpoint. 1383 * | | |11 = Undefined. 1384 * |[7] |DSQSYNC |Data Sequence Synchronization 1385 * | | |0 = DATA0 PID. 1386 * | | |1 = DATA1 PID. 1387 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1388 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1389 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1390 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1391 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1392 * | | |USB data toggle will be guaranteed by changing endpoint. 1393 * |[9] |CSTALL |Clear STALL Response 1394 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1395 * | | |1 = Clear the device to response STALL handshake in setup stage. 1396 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1397 * | | |0 = Inactive in double buffer mode. 1398 * | | |1 = Active in double buffer mode. 1399 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1400 * |[11] |DBEN |Double Buffer Enable Bit 1401 * | | |0 = Single buffer mode. 1402 * | | |1 = Double buffer mode. 1403 * @var USBD_T::CFGP11 1404 * Offset: 0x5BC Endpoint 11 Set Stall and Clear In/Out Ready Control Register 1405 * --------------------------------------------------------------------------------------------------- 1406 * |Bits |Field |Descriptions 1407 * | :----: | :----: | :---- | 1408 * |[0] |CLRRDY |Clear Ready Bit 1409 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1410 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1411 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1412 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1413 * | | |This bit is written 1 only and is always 0 when it is read back. 1414 * |[1] |SSTALL |Set STALL Bit 1415 * | | |0 = Disable the device to response STALL. 1416 * | | |1 = Set the device to respond STALL automatically. 1417 * @var USBD_T::BUFSEG12 1418 * Offset: 0x5C0 Endpoint 12 Buffer Segmentation Register 1419 * --------------------------------------------------------------------------------------------------- 1420 * |Bits |Field |Descriptions 1421 * | :----: | :----: | :---- | 1422 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1423 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1424 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1425 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1426 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1427 * @var USBD_T::MXPLD12 1428 * Offset: 0x5C4 Endpoint 12 Maximal Payload Register 1429 * --------------------------------------------------------------------------------------------------- 1430 * |Bits |Field |Descriptions 1431 * | :----: | :----: | :---- | 1432 * |[10:0] |MXPLD |Maximal Payload 1433 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1434 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1435 * | | |(1) When the register is written by CPU, 1436 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1437 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1438 * | | |(2) When the register is read by CPU, 1439 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1440 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1441 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1442 * @var USBD_T::CFG12 1443 * Offset: 0x5C8 Endpoint 12 Configuration Register 1444 * --------------------------------------------------------------------------------------------------- 1445 * |Bits |Field |Descriptions 1446 * | :----: | :----: | :---- | 1447 * |[3:0] |EPNUM |Endpoint Number 1448 * | | |These bits are used to define the endpoint number of the current endpoint. 1449 * |[4] |ISOCH |Isochronous Endpoint 1450 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1451 * | | |0 = No Isochronous endpoint. 1452 * | | |1 = Isochronous endpoint. 1453 * |[6:5] |STATE |Endpoint State 1454 * | | |00 = Endpoint is Disabled. 1455 * | | |01 = Out endpoint. 1456 * | | |10 = IN endpoint. 1457 * | | |11 = Undefined. 1458 * |[7] |DSQSYNC |Data Sequence Synchronization 1459 * | | |0 = DATA0 PID. 1460 * | | |1 = DATA1 PID. 1461 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1462 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1463 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1464 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1465 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1466 * | | |USB data toggle will be guaranteed by changing endpoint. 1467 * |[9] |CSTALL |Clear STALL Response 1468 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1469 * | | |1 = Clear the device to response STALL handshake in setup stage. 1470 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1471 * | | |0 = Inactive in double buffer mode. 1472 * | | |1 = Active in double buffer mode. 1473 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1474 * |[11] |DBEN |Double Buffer Enable Bit 1475 * | | |0 = Single buffer mode. 1476 * | | |1 = Double buffer mode. 1477 * @var USBD_T::CFGP12 1478 * Offset: 0x5CC Endpoint 12 Set Stall and Clear In/Out Ready Control Register 1479 * --------------------------------------------------------------------------------------------------- 1480 * |Bits |Field |Descriptions 1481 * | :----: | :----: | :---- | 1482 * |[0] |CLRRDY |Clear Ready Bit 1483 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1484 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1485 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1486 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1487 * | | |This bit is written 1 only and is always 0 when it is read back. 1488 * |[1] |SSTALL |Set STALL Bit 1489 * | | |0 = Disable the device to response STALL. 1490 * | | |1 = Set the device to respond STALL automatically. 1491 * @var USBD_T::BUFSEG13 1492 * Offset: 0x5D0 Endpoint 13 Buffer Segmentation Register 1493 * --------------------------------------------------------------------------------------------------- 1494 * |Bits |Field |Descriptions 1495 * | :----: | :----: | :---- | 1496 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1497 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1498 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1499 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1500 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1501 * @var USBD_T::MXPLD13 1502 * Offset: 0x5D4 Endpoint 13 Maximal Payload Register 1503 * --------------------------------------------------------------------------------------------------- 1504 * |Bits |Field |Descriptions 1505 * | :----: | :----: | :---- | 1506 * |[10:0] |MXPLD |Maximal Payload 1507 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1508 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1509 * | | |(1) When the register is written by CPU, 1510 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1511 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1512 * | | |(2) When the register is read by CPU, 1513 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1514 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1515 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1516 * @var USBD_T::CFG13 1517 * Offset: 0x5D8 Endpoint 13 Configuration Register 1518 * --------------------------------------------------------------------------------------------------- 1519 * |Bits |Field |Descriptions 1520 * | :----: | :----: | :---- | 1521 * |[3:0] |EPNUM |Endpoint Number 1522 * | | |These bits are used to define the endpoint number of the current endpoint. 1523 * |[4] |ISOCH |Isochronous Endpoint 1524 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1525 * | | |0 = No Isochronous endpoint. 1526 * | | |1 = Isochronous endpoint. 1527 * |[6:5] |STATE |Endpoint State 1528 * | | |00 = Endpoint is Disabled. 1529 * | | |01 = Out endpoint. 1530 * | | |10 = IN endpoint. 1531 * | | |11 = Undefined. 1532 * |[7] |DSQSYNC |Data Sequence Synchronization 1533 * | | |0 = DATA0 PID. 1534 * | | |1 = DATA1 PID. 1535 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1536 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1537 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1538 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1539 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1540 * | | |USB data toggle will be guaranteed by changing endpoint. 1541 * |[9] |CSTALL |Clear STALL Response 1542 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1543 * | | |1 = Clear the device to response STALL handshake in setup stage. 1544 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1545 * | | |0 = Inactive in double buffer mode. 1546 * | | |1 = Active in double buffer mode. 1547 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1548 * |[11] |DBEN |Double Buffer Enable Bit 1549 * | | |0 = Single buffer mode. 1550 * | | |1 = Double buffer mode. 1551 * @var USBD_T::CFGP13 1552 * Offset: 0x5DC Endpoint 13 Set Stall and Clear In/Out Ready Control Register 1553 * --------------------------------------------------------------------------------------------------- 1554 * |Bits |Field |Descriptions 1555 * | :----: | :----: | :---- | 1556 * |[0] |CLRRDY |Clear Ready Bit 1557 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1558 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1559 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1560 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1561 * | | |This bit is written 1 only and is always 0 when it is read back. 1562 * |[1] |SSTALL |Set STALL Bit 1563 * | | |0 = Disable the device to response STALL. 1564 * | | |1 = Set the device to respond STALL automatically. 1565 * @var USBD_T::BUFSEG14 1566 * Offset: 0x5E0 Endpoint 14 Buffer Segmentation Register 1567 * --------------------------------------------------------------------------------------------------- 1568 * |Bits |Field |Descriptions 1569 * | :----: | :----: | :---- | 1570 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1571 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1572 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1573 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1574 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1575 * @var USBD_T::MXPLD14 1576 * Offset: 0x5E4 Endpoint 14 Maximal Payload Register 1577 * --------------------------------------------------------------------------------------------------- 1578 * |Bits |Field |Descriptions 1579 * | :----: | :----: | :---- | 1580 * |[10:0] |MXPLD |Maximal Payload 1581 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1582 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1583 * | | |(1) When the register is written by CPU, 1584 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1585 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1586 * | | |(2) When the register is read by CPU, 1587 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1588 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1589 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1590 * @var USBD_T::CFG14 1591 * Offset: 0x5E8 Endpoint 14 Configuration Register 1592 * --------------------------------------------------------------------------------------------------- 1593 * |Bits |Field |Descriptions 1594 * | :----: | :----: | :---- | 1595 * |[3:0] |EPNUM |Endpoint Number 1596 * | | |These bits are used to define the endpoint number of the current endpoint. 1597 * |[4] |ISOCH |Isochronous Endpoint 1598 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1599 * | | |0 = No Isochronous endpoint. 1600 * | | |1 = Isochronous endpoint. 1601 * |[6:5] |STATE |Endpoint State 1602 * | | |00 = Endpoint is Disabled. 1603 * | | |01 = Out endpoint. 1604 * | | |10 = IN endpoint. 1605 * | | |11 = Undefined. 1606 * |[7] |DSQSYNC |Data Sequence Synchronization 1607 * | | |0 = DATA0 PID. 1608 * | | |1 = DATA1 PID. 1609 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1610 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1611 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1612 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1613 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1614 * | | |USB data toggle will be guaranteed by changing endpoint. 1615 * |[9] |CSTALL |Clear STALL Response 1616 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1617 * | | |1 = Clear the device to response STALL handshake in setup stage. 1618 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1619 * | | |0 = Inactive in double buffer mode. 1620 * | | |1 = Active in double buffer mode. 1621 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1622 * |[11] |DBEN |Double Buffer Enable Bit 1623 * | | |0 = Single buffer mode. 1624 * | | |1 = Double buffer mode. 1625 * @var USBD_T::CFGP14 1626 * Offset: 0x5EC Endpoint 14 Set Stall and Clear In/Out Ready Control Register 1627 * --------------------------------------------------------------------------------------------------- 1628 * |Bits |Field |Descriptions 1629 * | :----: | :----: | :---- | 1630 * |[0] |CLRRDY |Clear Ready Bit 1631 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1632 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1633 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1634 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1635 * | | |This bit is written 1 only and is always 0 when it is read back. 1636 * |[1] |SSTALL |Set STALL Bit 1637 * | | |0 = Disable the device to response STALL. 1638 * | | |1 = Set the device to respond STALL automatically. 1639 * @var USBD_T::BUFSEG15 1640 * Offset: 0x5F0 Endpoint 15 Buffer Segmentation Register 1641 * --------------------------------------------------------------------------------------------------- 1642 * |Bits |Field |Descriptions 1643 * | :----: | :----: | :---- | 1644 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1645 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1646 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1647 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1648 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1649 * @var USBD_T::MXPLD15 1650 * Offset: 0x5F4 Endpoint 15 Maximal Payload Register 1651 * --------------------------------------------------------------------------------------------------- 1652 * |Bits |Field |Descriptions 1653 * | :----: | :----: | :---- | 1654 * |[10:0] |MXPLD |Maximal Payload 1655 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1656 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1657 * | | |(1) When the register is written by CPU, 1658 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1659 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1660 * | | |(2) When the register is read by CPU, 1661 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1662 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1663 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1664 * @var USBD_T::CFG15 1665 * Offset: 0x5F8 Endpoint 15 Configuration Register 1666 * --------------------------------------------------------------------------------------------------- 1667 * |Bits |Field |Descriptions 1668 * | :----: | :----: | :---- | 1669 * |[3:0] |EPNUM |Endpoint Number 1670 * | | |These bits are used to define the endpoint number of the current endpoint. 1671 * |[4] |ISOCH |Isochronous Endpoint 1672 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1673 * | | |0 = No Isochronous endpoint. 1674 * | | |1 = Isochronous endpoint. 1675 * |[6:5] |STATE |Endpoint State 1676 * | | |00 = Endpoint is Disabled. 1677 * | | |01 = Out endpoint. 1678 * | | |10 = IN endpoint. 1679 * | | |11 = Undefined. 1680 * |[7] |DSQSYNC |Data Sequence Synchronization 1681 * | | |0 = DATA0 PID. 1682 * | | |1 = DATA1 PID. 1683 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1684 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1685 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1686 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1687 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1688 * | | |USB data toggle will be guaranteed by changing endpoint. 1689 * |[9] |CSTALL |Clear STALL Response 1690 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1691 * | | |1 = Clear the device to response STALL handshake in setup stage. 1692 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1693 * | | |0 = Inactive in double buffer mode. 1694 * | | |1 = Active in double buffer mode. 1695 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1696 * |[11] |DBEN |Double Buffer Enable Bit 1697 * | | |0 = Single buffer mode. 1698 * | | |1 = Double buffer mode. 1699 * @var USBD_T::CFGP15 1700 * Offset: 0x5FC Endpoint 15 Set Stall and Clear In/Out Ready Control Register 1701 * --------------------------------------------------------------------------------------------------- 1702 * |Bits |Field |Descriptions 1703 * | :----: | :----: | :---- | 1704 * |[0] |CLRRDY |Clear Ready Bit 1705 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1706 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1707 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1708 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1709 * | | |This bit is written 1 only and is always 0 when it is read back. 1710 * |[1] |SSTALL |Set STALL Bit 1711 * | | |0 = Disable the device to response STALL. 1712 * | | |1 = Set the device to respond STALL automatically. 1713 * @var USBD_T::BUFSEG16 1714 * Offset: 0x600 Endpoint 16 Buffer Segmentation Register 1715 * --------------------------------------------------------------------------------------------------- 1716 * |Bits |Field |Descriptions 1717 * | :----: | :----: | :---- | 1718 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1719 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1720 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1721 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1722 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1723 * @var USBD_T::MXPLD16 1724 * Offset: 0x604 Endpoint 16 Maximal Payload Register 1725 * --------------------------------------------------------------------------------------------------- 1726 * |Bits |Field |Descriptions 1727 * | :----: | :----: | :---- | 1728 * |[10:0] |MXPLD |Maximal Payload 1729 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1730 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1731 * | | |(1) When the register is written by CPU, 1732 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1733 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1734 * | | |(2) When the register is read by CPU, 1735 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1736 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1737 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1738 * @var USBD_T::CFG16 1739 * Offset: 0x608 Endpoint 16 Configuration Register 1740 * --------------------------------------------------------------------------------------------------- 1741 * |Bits |Field |Descriptions 1742 * | :----: | :----: | :---- | 1743 * |[3:0] |EPNUM |Endpoint Number 1744 * | | |These bits are used to define the endpoint number of the current endpoint. 1745 * |[4] |ISOCH |Isochronous Endpoint 1746 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1747 * | | |0 = No Isochronous endpoint. 1748 * | | |1 = Isochronous endpoint. 1749 * |[6:5] |STATE |Endpoint State 1750 * | | |00 = Endpoint is Disabled. 1751 * | | |01 = Out endpoint. 1752 * | | |10 = IN endpoint. 1753 * | | |11 = Undefined. 1754 * |[7] |DSQSYNC |Data Sequence Synchronization 1755 * | | |0 = DATA0 PID. 1756 * | | |1 = DATA1 PID. 1757 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1758 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1759 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1760 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1761 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1762 * | | |USB data toggle will be guaranteed by changing endpoint. 1763 * |[9] |CSTALL |Clear STALL Response 1764 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1765 * | | |1 = Clear the device to response STALL handshake in setup stage. 1766 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1767 * | | |0 = Inactive in double buffer mode. 1768 * | | |1 = Active in double buffer mode. 1769 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1770 * |[11] |DBEN |Double Buffer Enable Bit 1771 * | | |0 = Single buffer mode. 1772 * | | |1 = Double buffer mode. 1773 * @var USBD_T::CFGP16 1774 * Offset: 0x60C Endpoint 16 Set Stall and Clear In/Out Ready Control Register 1775 * --------------------------------------------------------------------------------------------------- 1776 * |Bits |Field |Descriptions 1777 * | :----: | :----: | :---- | 1778 * |[0] |CLRRDY |Clear Ready Bit 1779 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1780 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1781 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1782 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1783 * | | |This bit is written 1 only and is always 0 when it is read back. 1784 * |[1] |SSTALL |Set STALL Bit 1785 * | | |0 = Disable the device to response STALL. 1786 * | | |1 = Set the device to respond STALL automatically. 1787 * @var USBD_T::BUFSEG17 1788 * Offset: 0x610 Endpoint 17 Buffer Segmentation Register 1789 * --------------------------------------------------------------------------------------------------- 1790 * |Bits |Field |Descriptions 1791 * | :----: | :----: | :---- | 1792 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1793 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1794 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1795 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1796 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1797 * @var USBD_T::MXPLD17 1798 * Offset: 0x614 Endpoint 17 Maximal Payload Register 1799 * --------------------------------------------------------------------------------------------------- 1800 * |Bits |Field |Descriptions 1801 * | :----: | :----: | :---- | 1802 * |[10:0] |MXPLD |Maximal Payload 1803 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1804 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1805 * | | |(1) When the register is written by CPU, 1806 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1807 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1808 * | | |(2) When the register is read by CPU, 1809 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1810 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1811 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1812 * @var USBD_T::CFG17 1813 * Offset: 0x618 Endpoint 17 Configuration Register 1814 * --------------------------------------------------------------------------------------------------- 1815 * |Bits |Field |Descriptions 1816 * | :----: | :----: | :---- | 1817 * |[3:0] |EPNUM |Endpoint Number 1818 * | | |These bits are used to define the endpoint number of the current endpoint. 1819 * |[4] |ISOCH |Isochronous Endpoint 1820 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1821 * | | |0 = No Isochronous endpoint. 1822 * | | |1 = Isochronous endpoint. 1823 * |[6:5] |STATE |Endpoint State 1824 * | | |00 = Endpoint is Disabled. 1825 * | | |01 = Out endpoint. 1826 * | | |10 = IN endpoint. 1827 * | | |11 = Undefined. 1828 * |[7] |DSQSYNC |Data Sequence Synchronization 1829 * | | |0 = DATA0 PID. 1830 * | | |1 = DATA1 PID. 1831 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1832 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1833 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won''t be toggled in double buffer mode. 1834 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1835 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1836 * | | |USB data toggle will be guaranteed by changing endpoint. 1837 * |[9] |CSTALL |Clear STALL Response 1838 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1839 * | | |1 = Clear the device to response STALL handshake in setup stage. 1840 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1841 * | | |0 = Inactive in double buffer mode. 1842 * | | |1 = Active in double buffer mode. 1843 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1844 * |[11] |DBEN |Double Buffer Enable Bit 1845 * | | |0 = Single buffer mode. 1846 * | | |1 = Double buffer mode. 1847 * @var USBD_T::CFGP17 1848 * Offset: 0x61C Endpoint 17 Set Stall and Clear In/Out Ready Control Register 1849 * --------------------------------------------------------------------------------------------------- 1850 * |Bits |Field |Descriptions 1851 * | :----: | :----: | :---- | 1852 * |[0] |CLRRDY |Clear Ready Bit 1853 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1854 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1855 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1856 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1857 * | | |This bit is written 1 only and is always 0 when it is read back. 1858 * |[1] |SSTALL |Set STALL Bit 1859 * | | |0 = Disable the device to response STALL. 1860 * | | |1 = Set the device to respond STALL automatically. 1861 * @var USBD_T::BUFSEG18 1862 * Offset: 0x620 Endpoint 18 Buffer Segmentation Register 1863 * --------------------------------------------------------------------------------------------------- 1864 * |Bits |Field |Descriptions 1865 * | :----: | :----: | :---- | 1866 * |[10:3] |BUFSEG |Endpoint Buffer Segmentation 1867 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 1868 * | | |USBD_SRAM address + {BUFSEG, 3'b000} 1869 * | | |Where the USBD_SRAM address = USBD_BA+0x800h. 1870 * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. 1871 * @var USBD_T::MXPLD18 1872 * Offset: 0x624 Endpoint 18 Maximal Payload Register 1873 * --------------------------------------------------------------------------------------------------- 1874 * |Bits |Field |Descriptions 1875 * | :----: | :----: | :---- | 1876 * |[10:0] |MXPLD |Maximal Payload 1877 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 1878 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 1879 * | | |(1) When the register is written by CPU, 1880 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 1881 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 1882 * | | |(2) When the register is read by CPU, 1883 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 1884 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 1885 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 1886 * @var USBD_T::CFG18 1887 * Offset: 0x628 Endpoint 18 Configuration Register 1888 * --------------------------------------------------------------------------------------------------- 1889 * |Bits |Field |Descriptions 1890 * | :----: | :----: | :---- | 1891 * |[3:0] |EPNUM |Endpoint Number 1892 * | | |These bits are used to define the endpoint number of the current endpoint. 1893 * |[4] |ISOCH |Isochronous Endpoint 1894 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1895 * | | |0 = No Isochronous endpoint. 1896 * | | |1 = Isochronous endpoint. 1897 * |[6:5] |STATE |Endpoint State 1898 * | | |00 = Endpoint is Disabled. 1899 * | | |01 = Out endpoint. 1900 * | | |10 = IN endpoint. 1901 * | | |11 = Undefined. 1902 * |[7] |DSQSYNC |Data Sequence Synchronization 1903 * | | |0 = DATA0 PID. 1904 * | | |1 = DATA1 PID. 1905 * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet 1906 * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. 1907 * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won't be toggled in double buffer mode. 1908 * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. 1909 * | | |Note 2: It won't be toggled by hardware when DBEN = 1 1910 * | | |USB data toggle will be guaranteed by changing endpoint. 1911 * |[9] |CSTALL |Clear STALL Response 1912 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 1913 * | | |1 = Clear the device to response STALL handshake in setup stage. 1914 * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit 1915 * | | |0 = Inactive in double buffer mode. 1916 * | | |1 = Active in double buffer mode. 1917 * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. 1918 * |[11] |DBEN |Double Buffer Enable Bit 1919 * | | |0 = Single buffer mode. 1920 * | | |1 = Double buffer mode. 1921 * @var USBD_T::CFGP18 1922 * Offset: 0x62C Endpoint 18 Set Stall and Clear In/Out Ready Control Register 1923 * --------------------------------------------------------------------------------------------------- 1924 * |Bits |Field |Descriptions 1925 * | :----: | :----: | :---- | 1926 * |[0] |CLRRDY |Clear Ready Bit 1927 * | | |When the USBD_MXPLD0~18 register is set by user, it means that the endpoint is ready to transmit or receive data 1928 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically clear to 0. 1929 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 1930 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 1931 * | | |This bit is written 1 only and is always 0 when it is read back. 1932 * |[1] |SSTALL |Set STALL Bit 1933 * | | |0 = Disable the device to response STALL. 1934 * | | |1 = Set the device to respond STALL automatically. 1935 */ 1936 __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ 1937 __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ 1938 __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ 1939 __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ 1940 __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ 1941 __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ 1942 __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ 1943 __I uint32_t RESERVE0[1]; 1944 __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ 1945 __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ 1946 __I uint32_t EPSTS2; /*!< [0x0028] USB Device Endpoint Status Register 2 */ 1947 __I uint32_t EPSTS3; /*!< [0x002c] USB Device Endpoint Status Register 3 */ 1948 __IO uint32_t EPINTSTS; /*!< [0x0030] USB Device Endpoint Interrupt Event Status Register */ 1949 __I uint32_t RESERVE1[21]; 1950 __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ 1951 __I uint32_t FN; /*!< [0x008c] USB Frame Number Register */ 1952 __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ 1953 __I uint32_t RESERVE2[283]; 1954 USBD_EP_T EP[19]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ 1955 1956 } USBD_T; 1957 1958 /** 1959 @addtogroup USBD_CONST USBD Bit Field Definition 1960 Constant Definitions for USBD Controller 1961 @{ */ 1962 1963 #define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ 1964 #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ 1965 1966 #define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ 1967 #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ 1968 1969 #define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ 1970 #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ 1971 1972 #define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ 1973 #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ 1974 1975 #define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ 1976 #define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ 1977 1978 #define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ 1979 #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ 1980 1981 #define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ 1982 #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ 1983 1984 #define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ 1985 #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ 1986 1987 #define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ 1988 #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ 1989 1990 #define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ 1991 #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ 1992 1993 #define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ 1994 #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ 1995 1996 #define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ 1997 #define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ 1998 1999 #define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ 2000 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ 2001 2002 #define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ 2003 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ 2004 2005 #define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ 2006 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ 2007 2008 #define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ 2009 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ 2010 2011 #define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ 2012 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ 2013 2014 #define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ 2015 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ 2016 2017 #define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ 2018 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ 2019 2020 #define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ 2021 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ 2022 2023 #define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ 2024 #define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ 2025 2026 #define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ 2027 #define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ 2028 2029 #define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ 2030 #define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ 2031 2032 #define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ 2033 #define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ 2034 2035 #define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ 2036 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ 2037 2038 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ 2039 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ 2040 2041 #define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ 2042 #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ 2043 2044 #define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ 2045 #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ 2046 2047 #define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ 2048 #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ 2049 2050 #define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ 2051 #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ 2052 2053 #define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ 2054 #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ 2055 2056 #define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ 2057 #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ 2058 2059 #define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ 2060 #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ 2061 2062 #define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ 2063 #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ 2064 2065 #define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ 2066 #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ 2067 2068 #define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */ 2069 #define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */ 2070 2071 #define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ 2072 #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ 2073 2074 #define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ 2075 #define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ 2076 2077 #define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ 2078 #define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ 2079 2080 #define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ 2081 #define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ 2082 2083 #define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ 2084 #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ 2085 2086 #define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ 2087 #define USBD_STBUFSEG_STBUFSEG_Msk (0xfful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ 2088 #define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ 2089 #define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ 2090 2091 #define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ 2092 #define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ 2093 2094 #define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ 2095 #define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ 2096 2097 #define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ 2098 #define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ 2099 2100 #define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ 2101 #define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ 2102 2103 #define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ 2104 #define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ 2105 2106 #define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ 2107 #define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ 2108 2109 #define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ 2110 #define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ 2111 2112 #define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ 2113 #define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ 2114 2115 #define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ 2116 #define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ 2117 2118 #define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ 2119 #define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ 2120 2121 #define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ 2122 #define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ 2123 2124 #define USBD_EPSTS1_EPSTS12_Pos (16) /*!< USBD_T::EPSTS1: EPSTS12 Position */ 2125 #define USBD_EPSTS1_EPSTS12_Msk (0xful << USBD_EPSTS1_EPSTS12_Pos) /*!< USBD_T::EPSTS1: EPSTS12 Mask */ 2126 2127 #define USBD_EPSTS1_EPSTS13_Pos (20) /*!< USBD_T::EPSTS1: EPSTS13 Position */ 2128 #define USBD_EPSTS1_EPSTS13_Msk (0xful << USBD_EPSTS1_EPSTS13_Pos) /*!< USBD_T::EPSTS1: EPSTS13 Mask */ 2129 2130 #define USBD_EPSTS1_EPSTS14_Pos (24) /*!< USBD_T::EPSTS1: EPSTS14 Position */ 2131 #define USBD_EPSTS1_EPSTS14_Msk (0xful << USBD_EPSTS1_EPSTS14_Pos) /*!< USBD_T::EPSTS1: EPSTS14 Mask */ 2132 2133 #define USBD_EPSTS1_EPSTS15_Pos (28) /*!< USBD_T::EPSTS1: EPSTS15 Position */ 2134 #define USBD_EPSTS1_EPSTS15_Msk (0xful << USBD_EPSTS1_EPSTS15_Pos) /*!< USBD_T::EPSTS1: EPSTS15 Mask */ 2135 2136 #define USBD_EPSTS2_EPSTS16_Pos (0) /*!< USBD_T::EPSTS2: EPSTS16 Position */ 2137 #define USBD_EPSTS2_EPSTS16_Msk (0xful << USBD_EPSTS2_EPSTS16_Pos) /*!< USBD_T::EPSTS2: EPSTS16 Mask */ 2138 2139 #define USBD_EPSTS2_EPSTS17_Pos (4) /*!< USBD_T::EPSTS2: EPSTS17 Position */ 2140 #define USBD_EPSTS2_EPSTS17_Msk (0xful << USBD_EPSTS2_EPSTS17_Pos) /*!< USBD_T::EPSTS2: EPSTS17 Mask */ 2141 2142 #define USBD_EPSTS2_EPSTS18_Pos (8) /*!< USBD_T::EPSTS2: EPSTS18 Position */ 2143 #define USBD_EPSTS2_EPSTS18_Msk (0xful << USBD_EPSTS2_EPSTS18_Pos) /*!< USBD_T::EPSTS2: EPSTS18 Mask */ 2144 2145 #define USBD_EPINTSTS_EPEVT0_Pos (0) /*!< USBD_T::EPINTSTS: EPEVT0 Position */ 2146 #define USBD_EPINTSTS_EPEVT0_Msk (0x1ul << USBD_EPINTSTS_EPEVT0_Pos) /*!< USBD_T::EPINTSTS: EPEVT0 Mask */ 2147 2148 #define USBD_EPINTSTS_EPEVT1_Pos (1) /*!< USBD_T::EPINTSTS: EPEVT1 Position */ 2149 #define USBD_EPINTSTS_EPEVT1_Msk (0x1ul << USBD_EPINTSTS_EPEVT1_Pos) /*!< USBD_T::EPINTSTS: EPEVT1 Mask */ 2150 2151 #define USBD_EPINTSTS_EPEVT2_Pos (2) /*!< USBD_T::EPINTSTS: EPEVT2 Position */ 2152 #define USBD_EPINTSTS_EPEVT2_Msk (0x1ul << USBD_EPINTSTS_EPEVT2_Pos) /*!< USBD_T::EPINTSTS: EPEVT2 Mask */ 2153 2154 #define USBD_EPINTSTS_EPEVT3_Pos (3) /*!< USBD_T::EPINTSTS: EPEVT3 Position */ 2155 #define USBD_EPINTSTS_EPEVT3_Msk (0x1ul << USBD_EPINTSTS_EPEVT3_Pos) /*!< USBD_T::EPINTSTS: EPEVT3 Mask */ 2156 2157 #define USBD_EPINTSTS_EPEVT4_Pos (4) /*!< USBD_T::EPINTSTS: EPEVT4 Position */ 2158 #define USBD_EPINTSTS_EPEVT4_Msk (0x1ul << USBD_EPINTSTS_EPEVT4_Pos) /*!< USBD_T::EPINTSTS: EPEVT4 Mask */ 2159 2160 #define USBD_EPINTSTS_EPEVT5_Pos (5) /*!< USBD_T::EPINTSTS: EPEVT5 Position */ 2161 #define USBD_EPINTSTS_EPEVT5_Msk (0x1ul << USBD_EPINTSTS_EPEVT5_Pos) /*!< USBD_T::EPINTSTS: EPEVT5 Mask */ 2162 2163 #define USBD_EPINTSTS_EPEVT6_Pos (6) /*!< USBD_T::EPINTSTS: EPEVT6 Position */ 2164 #define USBD_EPINTSTS_EPEVT6_Msk (0x1ul << USBD_EPINTSTS_EPEVT6_Pos) /*!< USBD_T::EPINTSTS: EPEVT6 Mask */ 2165 2166 #define USBD_EPINTSTS_EPEVT7_Pos (7) /*!< USBD_T::EPINTSTS: EPEVT7 Position */ 2167 #define USBD_EPINTSTS_EPEVT7_Msk (0x1ul << USBD_EPINTSTS_EPEVT7_Pos) /*!< USBD_T::EPINTSTS: EPEVT7 Mask */ 2168 2169 #define USBD_EPINTSTS_EPEVT8_Pos (8) /*!< USBD_T::EPINTSTS: EPEVT8 Position */ 2170 #define USBD_EPINTSTS_EPEVT8_Msk (0x1ul << USBD_EPINTSTS_EPEVT8_Pos) /*!< USBD_T::EPINTSTS: EPEVT8 Mask */ 2171 2172 #define USBD_EPINTSTS_EPEVT9_Pos (9) /*!< USBD_T::EPINTSTS: EPEVT9 Position */ 2173 #define USBD_EPINTSTS_EPEVT9_Msk (0x1ul << USBD_EPINTSTS_EPEVT9_Pos) /*!< USBD_T::EPINTSTS: EPEVT9 Mask */ 2174 2175 #define USBD_EPINTSTS_EPEVT10_Pos (10) /*!< USBD_T::EPINTSTS: EPEVT10 Position */ 2176 #define USBD_EPINTSTS_EPEVT10_Msk (0x1ul << USBD_EPINTSTS_EPEVT10_Pos) /*!< USBD_T::EPINTSTS: EPEVT10 Mask */ 2177 2178 #define USBD_EPINTSTS_EPEVT11_Pos (11) /*!< USBD_T::EPINTSTS: EPEVT11 Position */ 2179 #define USBD_EPINTSTS_EPEVT11_Msk (0x1ul << USBD_EPINTSTS_EPEVT11_Pos) /*!< USBD_T::EPINTSTS: EPEVT11 Mask */ 2180 2181 #define USBD_EPINTSTS_EPEVT12_Pos (12) /*!< USBD_T::EPINTSTS: EPEVT12 Position */ 2182 #define USBD_EPINTSTS_EPEVT12_Msk (0x1ul << USBD_EPINTSTS_EPEVT12_Pos) /*!< USBD_T::EPINTSTS: EPEVT12 Mask */ 2183 2184 #define USBD_EPINTSTS_EPEVT13_Pos (13) /*!< USBD_T::EPINTSTS: EPEVT13 Position */ 2185 #define USBD_EPINTSTS_EPEVT13_Msk (0x1ul << USBD_EPINTSTS_EPEVT13_Pos) /*!< USBD_T::EPINTSTS: EPEVT13 Mask */ 2186 2187 #define USBD_EPINTSTS_EPEVT14_Pos (14) /*!< USBD_T::EPINTSTS: EPEVT14 Position */ 2188 #define USBD_EPINTSTS_EPEVT14_Msk (0x1ul << USBD_EPINTSTS_EPEVT14_Pos) /*!< USBD_T::EPINTSTS: EPEVT14 Mask */ 2189 2190 #define USBD_EPINTSTS_EPEVT15_Pos (15) /*!< USBD_T::EPINTSTS: EPEVT15 Position */ 2191 #define USBD_EPINTSTS_EPEVT15_Msk (0x1ul << USBD_EPINTSTS_EPEVT15_Pos) /*!< USBD_T::EPINTSTS: EPEVT15 Mask */ 2192 2193 #define USBD_EPINTSTS_EPEVT16_Pos (16) /*!< USBD_T::EPINTSTS: EPEVT16 Position */ 2194 #define USBD_EPINTSTS_EPEVT16_Msk (0x1ul << USBD_EPINTSTS_EPEVT16_Pos) /*!< USBD_T::EPINTSTS: EPEVT16 Mask */ 2195 2196 #define USBD_EPINTSTS_EPEVT17_Pos (17) /*!< USBD_T::EPINTSTS: EPEVT17 Position */ 2197 #define USBD_EPINTSTS_EPEVT17_Msk (0x1ul << USBD_EPINTSTS_EPEVT17_Pos) /*!< USBD_T::EPINTSTS: EPEVT17 Mask */ 2198 2199 #define USBD_EPINTSTS_EPEVT18_Pos (18) /*!< USBD_T::EPINTSTS: EPEVT18 Position */ 2200 #define USBD_EPINTSTS_EPEVT18_Msk (0x1ul << USBD_EPINTSTS_EPEVT18_Pos) /*!< USBD_T::EPINTSTS: EPEVT18 Mask */ 2201 2202 #define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ 2203 #define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ 2204 2205 #define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ 2206 #define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ 2207 2208 #define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ 2209 #define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ 2210 2211 #define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ 2212 #define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ 2213 2214 #define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ 2215 #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ 2216 2217 #define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ 2218 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ 2219 2220 #define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ 2221 2222 2223 #define USBD_BUFSEG0_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG0: BUFSEG Position */ 2224 #define USBD_BUFSEG0_BUFSEG_Msk (0xfful << USBD_BUFSEG0_BUFSEG_Pos) /*!< USBD_T::BUFSEG0: BUFSEG Mask */ 2225 2226 #define USBD_MXPLD0_MXPLD_Pos (0) /*!< USBD_T::MXPLD0: MXPLD Position */ 2227 #define USBD_MXPLD0_MXPLD_Msk (0x7fful << USBD_MXPLD0_MXPLD_Pos) /*!< USBD_T::MXPLD0: MXPLD Mask */ 2228 2229 #define USBD_CFG0_EPNUM_Pos (0) /*!< USBD_T::CFG0: EPNUM Position */ 2230 #define USBD_CFG0_EPNUM_Msk (0xful << USBD_CFG0_EPNUM_Pos) /*!< USBD_T::CFG0: EPNUM Mask */ 2231 2232 #define USBD_CFG0_ISOCH_Pos (4) /*!< USBD_T::CFG0: ISOCH Position */ 2233 #define USBD_CFG0_ISOCH_Msk (0x1ul << USBD_CFG0_ISOCH_Pos) /*!< USBD_T::CFG0: ISOCH Mask */ 2234 2235 #define USBD_CFG0_STATE_Pos (5) /*!< USBD_T::CFG0: STATE Position */ 2236 #define USBD_CFG0_STATE_Msk (0x3ul << USBD_CFG0_STATE_Pos) /*!< USBD_T::CFG0: STATE Mask */ 2237 2238 #define USBD_CFG0_DSQSYNC_Pos (7) /*!< USBD_T::CFG0: DSQSYNC Position */ 2239 #define USBD_CFG0_DSQSYNC_Msk (0x1ul << USBD_CFG0_DSQSYNC_Pos) /*!< USBD_T::CFG0: DSQSYNC Mask */ 2240 2241 #define USBD_CFG0_CSTALL_Pos (9) /*!< USBD_T::CFG0: CSTALL Position */ 2242 #define USBD_CFG0_CSTALL_Msk (0x1ul << USBD_CFG0_CSTALL_Pos) /*!< USBD_T::CFG0: CSTALL Mask */ 2243 2244 #define USBD_CFG0_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG0: DBTGACTIVE Position */ 2245 #define USBD_CFG0_DBTGACTIVE_Msk (0x1ul << USBD_CFG0_DBTGACTIVE_Pos) /*!< USBD_T::CFG0: DBTGACTIVE Mask */ 2246 2247 #define USBD_CFG0_DBEN_Pos (11) /*!< USBD_T::CFG0: DBEN Position */ 2248 #define USBD_CFG0_DBEN_Msk (0x1ul << USBD_CFG0_DBEN_Pos) /*!< USBD_T::CFG0: DBEN Mask */ 2249 2250 #define USBD_CFGP0_CLRRDY_Pos (0) /*!< USBD_T::CFGP0: CLRRDY Position */ 2251 #define USBD_CFGP0_CLRRDY_Msk (0x1ul << USBD_CFGP0_CLRRDY_Pos) /*!< USBD_T::CFGP0: CLRRDY Mask */ 2252 2253 #define USBD_CFGP0_SSTALL_Pos (1) /*!< USBD_T::CFGP0: SSTALL Position */ 2254 #define USBD_CFGP0_SSTALL_Msk (0x1ul << USBD_CFGP0_SSTALL_Pos) /*!< USBD_T::CFGP0: SSTALL Mask */ 2255 2256 #define USBD_BUFSEG1_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG1: BUFSEG Position */ 2257 #define USBD_BUFSEG1_BUFSEG_Msk (0xfful << USBD_BUFSEG1_BUFSEG_Pos) /*!< USBD_T::BUFSEG1: BUFSEG Mask */ 2258 2259 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ 2260 2261 #define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ 2262 #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ 2263 2264 #define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ 2265 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ 2266 2267 #define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ 2268 #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ 2269 2270 #define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ 2271 #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ 2272 2273 #define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ 2274 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ 2275 2276 #define USBD_CFG_DBTGACTIVE_Pos (10) /*!< USBD_EP_T::CFG: DBTGACTIVE Position */ 2277 #define USBD_CFG_DBTGACTIVE_Msk (0x1ul << USBD_CFG_DBTGACTIVE_Pos) /*!< USBD_EP_T::CFG: DBTGACTIVE Mask */ 2278 2279 #define USBD_CFG_DBEN_Pos (11) /*!< USBD_EP_T::CFG: DBEN Position */ 2280 #define USBD_CFG_DBEN_Msk (0x1ul << USBD_CFG_DBEN_Pos) /*!< USBD_EP_T::CFG: DBEN Mask */ 2281 2282 #define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ 2283 #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ 2284 2285 #define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ 2286 #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ 2287 2288 2289 #define USBD_MXPLD1_MXPLD_Pos (0) /*!< USBD_T::MXPLD1: MXPLD Position */ 2290 #define USBD_MXPLD1_MXPLD_Msk (0x7fful << USBD_MXPLD1_MXPLD_Pos) /*!< USBD_T::MXPLD1: MXPLD Mask */ 2291 2292 #define USBD_CFG1_EPNUM_Pos (0) /*!< USBD_T::CFG1: EPNUM Position */ 2293 #define USBD_CFG1_EPNUM_Msk (0xful << USBD_CFG1_EPNUM_Pos) /*!< USBD_T::CFG1: EPNUM Mask */ 2294 2295 #define USBD_CFG1_ISOCH_Pos (4) /*!< USBD_T::CFG1: ISOCH Position */ 2296 #define USBD_CFG1_ISOCH_Msk (0x1ul << USBD_CFG1_ISOCH_Pos) /*!< USBD_T::CFG1: ISOCH Mask */ 2297 2298 #define USBD_CFG1_STATE_Pos (5) /*!< USBD_T::CFG1: STATE Position */ 2299 #define USBD_CFG1_STATE_Msk (0x3ul << USBD_CFG1_STATE_Pos) /*!< USBD_T::CFG1: STATE Mask */ 2300 2301 #define USBD_CFG1_DSQSYNC_Pos (7) /*!< USBD_T::CFG1: DSQSYNC Position */ 2302 #define USBD_CFG1_DSQSYNC_Msk (0x1ul << USBD_CFG1_DSQSYNC_Pos) /*!< USBD_T::CFG1: DSQSYNC Mask */ 2303 2304 #define USBD_CFG1_CSTALL_Pos (9) /*!< USBD_T::CFG1: CSTALL Position */ 2305 #define USBD_CFG1_CSTALL_Msk (0x1ul << USBD_CFG1_CSTALL_Pos) /*!< USBD_T::CFG1: CSTALL Mask */ 2306 2307 #define USBD_CFG1_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG1: DBTGACTIVE Position */ 2308 #define USBD_CFG1_DBTGACTIVE_Msk (0x1ul << USBD_CFG1_DBTGACTIVE_Pos) /*!< USBD_T::CFG1: DBTGACTIVE Mask */ 2309 2310 #define USBD_CFG1_DBEN_Pos (11) /*!< USBD_T::CFG1: DBEN Position */ 2311 #define USBD_CFG1_DBEN_Msk (0x1ul << USBD_CFG1_DBEN_Pos) /*!< USBD_T::CFG1: DBEN Mask */ 2312 2313 #define USBD_CFGP1_CLRRDY_Pos (0) /*!< USBD_T::CFGP1: CLRRDY Position */ 2314 #define USBD_CFGP1_CLRRDY_Msk (0x1ul << USBD_CFGP1_CLRRDY_Pos) /*!< USBD_T::CFGP1: CLRRDY Mask */ 2315 2316 #define USBD_CFGP1_SSTALL_Pos (1) /*!< USBD_T::CFGP1: SSTALL Position */ 2317 #define USBD_CFGP1_SSTALL_Msk (0x1ul << USBD_CFGP1_SSTALL_Pos) /*!< USBD_T::CFGP1: SSTALL Mask */ 2318 2319 #define USBD_BUFSEG2_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG2: BUFSEG Position */ 2320 #define USBD_BUFSEG2_BUFSEG_Msk (0xfful << USBD_BUFSEG2_BUFSEG_Pos) /*!< USBD_T::BUFSEG2: BUFSEG Mask */ 2321 2322 #define USBD_MXPLD2_MXPLD_Pos (0) /*!< USBD_T::MXPLD2: MXPLD Position */ 2323 #define USBD_MXPLD2_MXPLD_Msk (0x7fful << USBD_MXPLD2_MXPLD_Pos) /*!< USBD_T::MXPLD2: MXPLD Mask */ 2324 2325 #define USBD_CFG2_EPNUM_Pos (0) /*!< USBD_T::CFG2: EPNUM Position */ 2326 #define USBD_CFG2_EPNUM_Msk (0xful << USBD_CFG2_EPNUM_Pos) /*!< USBD_T::CFG2: EPNUM Mask */ 2327 2328 #define USBD_CFG2_ISOCH_Pos (4) /*!< USBD_T::CFG2: ISOCH Position */ 2329 #define USBD_CFG2_ISOCH_Msk (0x1ul << USBD_CFG2_ISOCH_Pos) /*!< USBD_T::CFG2: ISOCH Mask */ 2330 2331 #define USBD_CFG2_STATE_Pos (5) /*!< USBD_T::CFG2: STATE Position */ 2332 #define USBD_CFG2_STATE_Msk (0x3ul << USBD_CFG2_STATE_Pos) /*!< USBD_T::CFG2: STATE Mask */ 2333 2334 #define USBD_CFG2_DSQSYNC_Pos (7) /*!< USBD_T::CFG2: DSQSYNC Position */ 2335 #define USBD_CFG2_DSQSYNC_Msk (0x1ul << USBD_CFG2_DSQSYNC_Pos) /*!< USBD_T::CFG2: DSQSYNC Mask */ 2336 2337 #define USBD_CFG2_CSTALL_Pos (9) /*!< USBD_T::CFG2: CSTALL Position */ 2338 #define USBD_CFG2_CSTALL_Msk (0x1ul << USBD_CFG2_CSTALL_Pos) /*!< USBD_T::CFG2: CSTALL Mask */ 2339 2340 #define USBD_CFG2_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG2: DBTGACTIVE Position */ 2341 #define USBD_CFG2_DBTGACTIVE_Msk (0x1ul << USBD_CFG2_DBTGACTIVE_Pos) /*!< USBD_T::CFG2: DBTGACTIVE Mask */ 2342 2343 #define USBD_CFG2_DBEN_Pos (11) /*!< USBD_T::CFG2: DBEN Position */ 2344 #define USBD_CFG2_DBEN_Msk (0x1ul << USBD_CFG2_DBEN_Pos) /*!< USBD_T::CFG2: DBEN Mask */ 2345 2346 #define USBD_CFGP2_CLRRDY_Pos (0) /*!< USBD_T::CFGP2: CLRRDY Position */ 2347 #define USBD_CFGP2_CLRRDY_Msk (0x1ul << USBD_CFGP2_CLRRDY_Pos) /*!< USBD_T::CFGP2: CLRRDY Mask */ 2348 2349 #define USBD_CFGP2_SSTALL_Pos (1) /*!< USBD_T::CFGP2: SSTALL Position */ 2350 #define USBD_CFGP2_SSTALL_Msk (0x1ul << USBD_CFGP2_SSTALL_Pos) /*!< USBD_T::CFGP2: SSTALL Mask */ 2351 2352 #define USBD_BUFSEG3_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG3: BUFSEG Position */ 2353 #define USBD_BUFSEG3_BUFSEG_Msk (0xfful << USBD_BUFSEG3_BUFSEG_Pos) /*!< USBD_T::BUFSEG3: BUFSEG Mask */ 2354 2355 #define USBD_MXPLD3_MXPLD_Pos (0) /*!< USBD_T::MXPLD3: MXPLD Position */ 2356 #define USBD_MXPLD3_MXPLD_Msk (0x7fful << USBD_MXPLD3_MXPLD_Pos) /*!< USBD_T::MXPLD3: MXPLD Mask */ 2357 2358 #define USBD_CFG3_EPNUM_Pos (0) /*!< USBD_T::CFG3: EPNUM Position */ 2359 #define USBD_CFG3_EPNUM_Msk (0xful << USBD_CFG3_EPNUM_Pos) /*!< USBD_T::CFG3: EPNUM Mask */ 2360 2361 #define USBD_CFG3_ISOCH_Pos (4) /*!< USBD_T::CFG3: ISOCH Position */ 2362 #define USBD_CFG3_ISOCH_Msk (0x1ul << USBD_CFG3_ISOCH_Pos) /*!< USBD_T::CFG3: ISOCH Mask */ 2363 2364 #define USBD_CFG3_STATE_Pos (5) /*!< USBD_T::CFG3: STATE Position */ 2365 #define USBD_CFG3_STATE_Msk (0x3ul << USBD_CFG3_STATE_Pos) /*!< USBD_T::CFG3: STATE Mask */ 2366 2367 #define USBD_CFG3_DSQSYNC_Pos (7) /*!< USBD_T::CFG3: DSQSYNC Position */ 2368 #define USBD_CFG3_DSQSYNC_Msk (0x1ul << USBD_CFG3_DSQSYNC_Pos) /*!< USBD_T::CFG3: DSQSYNC Mask */ 2369 2370 #define USBD_CFG3_CSTALL_Pos (9) /*!< USBD_T::CFG3: CSTALL Position */ 2371 #define USBD_CFG3_CSTALL_Msk (0x1ul << USBD_CFG3_CSTALL_Pos) /*!< USBD_T::CFG3: CSTALL Mask */ 2372 2373 #define USBD_CFG3_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG3: DBTGACTIVE Position */ 2374 #define USBD_CFG3_DBTGACTIVE_Msk (0x1ul << USBD_CFG3_DBTGACTIVE_Pos) /*!< USBD_T::CFG3: DBTGACTIVE Mask */ 2375 2376 #define USBD_CFG3_DBEN_Pos (11) /*!< USBD_T::CFG3: DBEN Position */ 2377 #define USBD_CFG3_DBEN_Msk (0x1ul << USBD_CFG3_DBEN_Pos) /*!< USBD_T::CFG3: DBEN Mask */ 2378 2379 #define USBD_CFGP3_CLRRDY_Pos (0) /*!< USBD_T::CFGP3: CLRRDY Position */ 2380 #define USBD_CFGP3_CLRRDY_Msk (0x1ul << USBD_CFGP3_CLRRDY_Pos) /*!< USBD_T::CFGP3: CLRRDY Mask */ 2381 2382 #define USBD_CFGP3_SSTALL_Pos (1) /*!< USBD_T::CFGP3: SSTALL Position */ 2383 #define USBD_CFGP3_SSTALL_Msk (0x1ul << USBD_CFGP3_SSTALL_Pos) /*!< USBD_T::CFGP3: SSTALL Mask */ 2384 2385 #define USBD_BUFSEG4_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG4: BUFSEG Position */ 2386 #define USBD_BUFSEG4_BUFSEG_Msk (0xfful << USBD_BUFSEG4_BUFSEG_Pos) /*!< USBD_T::BUFSEG4: BUFSEG Mask */ 2387 2388 #define USBD_MXPLD4_MXPLD_Pos (0) /*!< USBD_T::MXPLD4: MXPLD Position */ 2389 #define USBD_MXPLD4_MXPLD_Msk (0x7fful << USBD_MXPLD4_MXPLD_Pos) /*!< USBD_T::MXPLD4: MXPLD Mask */ 2390 2391 #define USBD_CFG4_EPNUM_Pos (0) /*!< USBD_T::CFG4: EPNUM Position */ 2392 #define USBD_CFG4_EPNUM_Msk (0xful << USBD_CFG4_EPNUM_Pos) /*!< USBD_T::CFG4: EPNUM Mask */ 2393 2394 #define USBD_CFG4_ISOCH_Pos (4) /*!< USBD_T::CFG4: ISOCH Position */ 2395 #define USBD_CFG4_ISOCH_Msk (0x1ul << USBD_CFG4_ISOCH_Pos) /*!< USBD_T::CFG4: ISOCH Mask */ 2396 2397 #define USBD_CFG4_STATE_Pos (5) /*!< USBD_T::CFG4: STATE Position */ 2398 #define USBD_CFG4_STATE_Msk (0x3ul << USBD_CFG4_STATE_Pos) /*!< USBD_T::CFG4: STATE Mask */ 2399 2400 #define USBD_CFG4_DSQSYNC_Pos (7) /*!< USBD_T::CFG4: DSQSYNC Position */ 2401 #define USBD_CFG4_DSQSYNC_Msk (0x1ul << USBD_CFG4_DSQSYNC_Pos) /*!< USBD_T::CFG4: DSQSYNC Mask */ 2402 2403 #define USBD_CFG4_CSTALL_Pos (9) /*!< USBD_T::CFG4: CSTALL Position */ 2404 #define USBD_CFG4_CSTALL_Msk (0x1ul << USBD_CFG4_CSTALL_Pos) /*!< USBD_T::CFG4: CSTALL Mask */ 2405 2406 #define USBD_CFG4_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG4: DBTGACTIVE Position */ 2407 #define USBD_CFG4_DBTGACTIVE_Msk (0x1ul << USBD_CFG4_DBTGACTIVE_Pos) /*!< USBD_T::CFG4: DBTGACTIVE Mask */ 2408 2409 #define USBD_CFG4_DBEN_Pos (11) /*!< USBD_T::CFG4: DBEN Position */ 2410 #define USBD_CFG4_DBEN_Msk (0x1ul << USBD_CFG4_DBEN_Pos) /*!< USBD_T::CFG4: DBEN Mask */ 2411 2412 #define USBD_CFGP4_CLRRDY_Pos (0) /*!< USBD_T::CFGP4: CLRRDY Position */ 2413 #define USBD_CFGP4_CLRRDY_Msk (0x1ul << USBD_CFGP4_CLRRDY_Pos) /*!< USBD_T::CFGP4: CLRRDY Mask */ 2414 2415 #define USBD_CFGP4_SSTALL_Pos (1) /*!< USBD_T::CFGP4: SSTALL Position */ 2416 #define USBD_CFGP4_SSTALL_Msk (0x1ul << USBD_CFGP4_SSTALL_Pos) /*!< USBD_T::CFGP4: SSTALL Mask */ 2417 2418 #define USBD_BUFSEG5_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG5: BUFSEG Position */ 2419 #define USBD_BUFSEG5_BUFSEG_Msk (0xfful << USBD_BUFSEG5_BUFSEG_Pos) /*!< USBD_T::BUFSEG5: BUFSEG Mask */ 2420 2421 #define USBD_MXPLD5_MXPLD_Pos (0) /*!< USBD_T::MXPLD5: MXPLD Position */ 2422 #define USBD_MXPLD5_MXPLD_Msk (0x7fful << USBD_MXPLD5_MXPLD_Pos) /*!< USBD_T::MXPLD5: MXPLD Mask */ 2423 2424 #define USBD_CFG5_EPNUM_Pos (0) /*!< USBD_T::CFG5: EPNUM Position */ 2425 #define USBD_CFG5_EPNUM_Msk (0xful << USBD_CFG5_EPNUM_Pos) /*!< USBD_T::CFG5: EPNUM Mask */ 2426 2427 #define USBD_CFG5_ISOCH_Pos (4) /*!< USBD_T::CFG5: ISOCH Position */ 2428 #define USBD_CFG5_ISOCH_Msk (0x1ul << USBD_CFG5_ISOCH_Pos) /*!< USBD_T::CFG5: ISOCH Mask */ 2429 2430 #define USBD_CFG5_STATE_Pos (5) /*!< USBD_T::CFG5: STATE Position */ 2431 #define USBD_CFG5_STATE_Msk (0x3ul << USBD_CFG5_STATE_Pos) /*!< USBD_T::CFG5: STATE Mask */ 2432 2433 #define USBD_CFG5_DSQSYNC_Pos (7) /*!< USBD_T::CFG5: DSQSYNC Position */ 2434 #define USBD_CFG5_DSQSYNC_Msk (0x1ul << USBD_CFG5_DSQSYNC_Pos) /*!< USBD_T::CFG5: DSQSYNC Mask */ 2435 2436 #define USBD_CFG5_CSTALL_Pos (9) /*!< USBD_T::CFG5: CSTALL Position */ 2437 #define USBD_CFG5_CSTALL_Msk (0x1ul << USBD_CFG5_CSTALL_Pos) /*!< USBD_T::CFG5: CSTALL Mask */ 2438 2439 #define USBD_CFG5_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG5: DBTGACTIVE Position */ 2440 #define USBD_CFG5_DBTGACTIVE_Msk (0x1ul << USBD_CFG5_DBTGACTIVE_Pos) /*!< USBD_T::CFG5: DBTGACTIVE Mask */ 2441 2442 #define USBD_CFG5_DBEN_Pos (11) /*!< USBD_T::CFG5: DBEN Position */ 2443 #define USBD_CFG5_DBEN_Msk (0x1ul << USBD_CFG5_DBEN_Pos) /*!< USBD_T::CFG5: DBEN Mask */ 2444 2445 #define USBD_CFGP5_CLRRDY_Pos (0) /*!< USBD_T::CFGP5: CLRRDY Position */ 2446 #define USBD_CFGP5_CLRRDY_Msk (0x1ul << USBD_CFGP5_CLRRDY_Pos) /*!< USBD_T::CFGP5: CLRRDY Mask */ 2447 2448 #define USBD_CFGP5_SSTALL_Pos (1) /*!< USBD_T::CFGP5: SSTALL Position */ 2449 #define USBD_CFGP5_SSTALL_Msk (0x1ul << USBD_CFGP5_SSTALL_Pos) /*!< USBD_T::CFGP5: SSTALL Mask */ 2450 2451 #define USBD_BUFSEG6_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG6: BUFSEG Position */ 2452 #define USBD_BUFSEG6_BUFSEG_Msk (0xfful << USBD_BUFSEG6_BUFSEG_Pos) /*!< USBD_T::BUFSEG6: BUFSEG Mask */ 2453 2454 #define USBD_MXPLD6_MXPLD_Pos (0) /*!< USBD_T::MXPLD6: MXPLD Position */ 2455 #define USBD_MXPLD6_MXPLD_Msk (0x7fful << USBD_MXPLD6_MXPLD_Pos) /*!< USBD_T::MXPLD6: MXPLD Mask */ 2456 2457 #define USBD_CFG6_EPNUM_Pos (0) /*!< USBD_T::CFG6: EPNUM Position */ 2458 #define USBD_CFG6_EPNUM_Msk (0xful << USBD_CFG6_EPNUM_Pos) /*!< USBD_T::CFG6: EPNUM Mask */ 2459 2460 #define USBD_CFG6_ISOCH_Pos (4) /*!< USBD_T::CFG6: ISOCH Position */ 2461 #define USBD_CFG6_ISOCH_Msk (0x1ul << USBD_CFG6_ISOCH_Pos) /*!< USBD_T::CFG6: ISOCH Mask */ 2462 2463 #define USBD_CFG6_STATE_Pos (5) /*!< USBD_T::CFG6: STATE Position */ 2464 #define USBD_CFG6_STATE_Msk (0x3ul << USBD_CFG6_STATE_Pos) /*!< USBD_T::CFG6: STATE Mask */ 2465 2466 #define USBD_CFG6_DSQSYNC_Pos (7) /*!< USBD_T::CFG6: DSQSYNC Position */ 2467 #define USBD_CFG6_DSQSYNC_Msk (0x1ul << USBD_CFG6_DSQSYNC_Pos) /*!< USBD_T::CFG6: DSQSYNC Mask */ 2468 2469 #define USBD_CFG6_CSTALL_Pos (9) /*!< USBD_T::CFG6: CSTALL Position */ 2470 #define USBD_CFG6_CSTALL_Msk (0x1ul << USBD_CFG6_CSTALL_Pos) /*!< USBD_T::CFG6: CSTALL Mask */ 2471 2472 #define USBD_CFG6_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG6: DBTGACTIVE Position */ 2473 #define USBD_CFG6_DBTGACTIVE_Msk (0x1ul << USBD_CFG6_DBTGACTIVE_Pos) /*!< USBD_T::CFG6: DBTGACTIVE Mask */ 2474 2475 #define USBD_CFG6_DBEN_Pos (11) /*!< USBD_T::CFG6: DBEN Position */ 2476 #define USBD_CFG6_DBEN_Msk (0x1ul << USBD_CFG6_DBEN_Pos) /*!< USBD_T::CFG6: DBEN Mask */ 2477 2478 #define USBD_CFGP6_CLRRDY_Pos (0) /*!< USBD_T::CFGP6: CLRRDY Position */ 2479 #define USBD_CFGP6_CLRRDY_Msk (0x1ul << USBD_CFGP6_CLRRDY_Pos) /*!< USBD_T::CFGP6: CLRRDY Mask */ 2480 2481 #define USBD_CFGP6_SSTALL_Pos (1) /*!< USBD_T::CFGP6: SSTALL Position */ 2482 #define USBD_CFGP6_SSTALL_Msk (0x1ul << USBD_CFGP6_SSTALL_Pos) /*!< USBD_T::CFGP6: SSTALL Mask */ 2483 2484 #define USBD_BUFSEG7_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG7: BUFSEG Position */ 2485 #define USBD_BUFSEG7_BUFSEG_Msk (0xfful << USBD_BUFSEG7_BUFSEG_Pos) /*!< USBD_T::BUFSEG7: BUFSEG Mask */ 2486 2487 #define USBD_MXPLD7_MXPLD_Pos (0) /*!< USBD_T::MXPLD7: MXPLD Position */ 2488 #define USBD_MXPLD7_MXPLD_Msk (0x7fful << USBD_MXPLD7_MXPLD_Pos) /*!< USBD_T::MXPLD7: MXPLD Mask */ 2489 2490 #define USBD_CFG7_EPNUM_Pos (0) /*!< USBD_T::CFG7: EPNUM Position */ 2491 #define USBD_CFG7_EPNUM_Msk (0xful << USBD_CFG7_EPNUM_Pos) /*!< USBD_T::CFG7: EPNUM Mask */ 2492 2493 #define USBD_CFG7_ISOCH_Pos (4) /*!< USBD_T::CFG7: ISOCH Position */ 2494 #define USBD_CFG7_ISOCH_Msk (0x1ul << USBD_CFG7_ISOCH_Pos) /*!< USBD_T::CFG7: ISOCH Mask */ 2495 2496 #define USBD_CFG7_STATE_Pos (5) /*!< USBD_T::CFG7: STATE Position */ 2497 #define USBD_CFG7_STATE_Msk (0x3ul << USBD_CFG7_STATE_Pos) /*!< USBD_T::CFG7: STATE Mask */ 2498 2499 #define USBD_CFG7_DSQSYNC_Pos (7) /*!< USBD_T::CFG7: DSQSYNC Position */ 2500 #define USBD_CFG7_DSQSYNC_Msk (0x1ul << USBD_CFG7_DSQSYNC_Pos) /*!< USBD_T::CFG7: DSQSYNC Mask */ 2501 2502 #define USBD_CFG7_CSTALL_Pos (9) /*!< USBD_T::CFG7: CSTALL Position */ 2503 #define USBD_CFG7_CSTALL_Msk (0x1ul << USBD_CFG7_CSTALL_Pos) /*!< USBD_T::CFG7: CSTALL Mask */ 2504 2505 #define USBD_CFG7_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG7: DBTGACTIVE Position */ 2506 #define USBD_CFG7_DBTGACTIVE_Msk (0x1ul << USBD_CFG7_DBTGACTIVE_Pos) /*!< USBD_T::CFG7: DBTGACTIVE Mask */ 2507 2508 #define USBD_CFG7_DBEN_Pos (11) /*!< USBD_T::CFG7: DBEN Position */ 2509 #define USBD_CFG7_DBEN_Msk (0x1ul << USBD_CFG7_DBEN_Pos) /*!< USBD_T::CFG7: DBEN Mask */ 2510 2511 #define USBD_CFGP7_CLRRDY_Pos (0) /*!< USBD_T::CFGP7: CLRRDY Position */ 2512 #define USBD_CFGP7_CLRRDY_Msk (0x1ul << USBD_CFGP7_CLRRDY_Pos) /*!< USBD_T::CFGP7: CLRRDY Mask */ 2513 2514 #define USBD_CFGP7_SSTALL_Pos (1) /*!< USBD_T::CFGP7: SSTALL Position */ 2515 #define USBD_CFGP7_SSTALL_Msk (0x1ul << USBD_CFGP7_SSTALL_Pos) /*!< USBD_T::CFGP7: SSTALL Mask */ 2516 2517 #define USBD_BUFSEG8_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG8: BUFSEG Position */ 2518 #define USBD_BUFSEG8_BUFSEG_Msk (0xfful << USBD_BUFSEG8_BUFSEG_Pos) /*!< USBD_T::BUFSEG8: BUFSEG Mask */ 2519 2520 #define USBD_MXPLD8_MXPLD_Pos (0) /*!< USBD_T::MXPLD8: MXPLD Position */ 2521 #define USBD_MXPLD8_MXPLD_Msk (0x7fful << USBD_MXPLD8_MXPLD_Pos) /*!< USBD_T::MXPLD8: MXPLD Mask */ 2522 2523 #define USBD_CFG8_EPNUM_Pos (0) /*!< USBD_T::CFG8: EPNUM Position */ 2524 #define USBD_CFG8_EPNUM_Msk (0xful << USBD_CFG8_EPNUM_Pos) /*!< USBD_T::CFG8: EPNUM Mask */ 2525 2526 #define USBD_CFG8_ISOCH_Pos (4) /*!< USBD_T::CFG8: ISOCH Position */ 2527 #define USBD_CFG8_ISOCH_Msk (0x1ul << USBD_CFG8_ISOCH_Pos) /*!< USBD_T::CFG8: ISOCH Mask */ 2528 2529 #define USBD_CFG8_STATE_Pos (5) /*!< USBD_T::CFG8: STATE Position */ 2530 #define USBD_CFG8_STATE_Msk (0x3ul << USBD_CFG8_STATE_Pos) /*!< USBD_T::CFG8: STATE Mask */ 2531 2532 #define USBD_CFG8_DSQSYNC_Pos (7) /*!< USBD_T::CFG8: DSQSYNC Position */ 2533 #define USBD_CFG8_DSQSYNC_Msk (0x1ul << USBD_CFG8_DSQSYNC_Pos) /*!< USBD_T::CFG8: DSQSYNC Mask */ 2534 2535 #define USBD_CFG8_CSTALL_Pos (9) /*!< USBD_T::CFG8: CSTALL Position */ 2536 #define USBD_CFG8_CSTALL_Msk (0x1ul << USBD_CFG8_CSTALL_Pos) /*!< USBD_T::CFG8: CSTALL Mask */ 2537 2538 #define USBD_CFG8_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG8: DBTGACTIVE Position */ 2539 #define USBD_CFG8_DBTGACTIVE_Msk (0x1ul << USBD_CFG8_DBTGACTIVE_Pos) /*!< USBD_T::CFG8: DBTGACTIVE Mask */ 2540 2541 #define USBD_CFG8_DBEN_Pos (11) /*!< USBD_T::CFG8: DBEN Position */ 2542 #define USBD_CFG8_DBEN_Msk (0x1ul << USBD_CFG8_DBEN_Pos) /*!< USBD_T::CFG8: DBEN Mask */ 2543 2544 #define USBD_CFGP8_CLRRDY_Pos (0) /*!< USBD_T::CFGP8: CLRRDY Position */ 2545 #define USBD_CFGP8_CLRRDY_Msk (0x1ul << USBD_CFGP8_CLRRDY_Pos) /*!< USBD_T::CFGP8: CLRRDY Mask */ 2546 2547 #define USBD_CFGP8_SSTALL_Pos (1) /*!< USBD_T::CFGP8: SSTALL Position */ 2548 #define USBD_CFGP8_SSTALL_Msk (0x1ul << USBD_CFGP8_SSTALL_Pos) /*!< USBD_T::CFGP8: SSTALL Mask */ 2549 2550 #define USBD_BUFSEG9_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG9: BUFSEG Position */ 2551 #define USBD_BUFSEG9_BUFSEG_Msk (0xfful << USBD_BUFSEG9_BUFSEG_Pos) /*!< USBD_T::BUFSEG9: BUFSEG Mask */ 2552 2553 #define USBD_MXPLD9_MXPLD_Pos (0) /*!< USBD_T::MXPLD9: MXPLD Position */ 2554 #define USBD_MXPLD9_MXPLD_Msk (0x7fful << USBD_MXPLD9_MXPLD_Pos) /*!< USBD_T::MXPLD9: MXPLD Mask */ 2555 2556 #define USBD_CFG9_EPNUM_Pos (0) /*!< USBD_T::CFG9: EPNUM Position */ 2557 #define USBD_CFG9_EPNUM_Msk (0xful << USBD_CFG9_EPNUM_Pos) /*!< USBD_T::CFG9: EPNUM Mask */ 2558 2559 #define USBD_CFG9_ISOCH_Pos (4) /*!< USBD_T::CFG9: ISOCH Position */ 2560 #define USBD_CFG9_ISOCH_Msk (0x1ul << USBD_CFG9_ISOCH_Pos) /*!< USBD_T::CFG9: ISOCH Mask */ 2561 2562 #define USBD_CFG9_STATE_Pos (5) /*!< USBD_T::CFG9: STATE Position */ 2563 #define USBD_CFG9_STATE_Msk (0x3ul << USBD_CFG9_STATE_Pos) /*!< USBD_T::CFG9: STATE Mask */ 2564 2565 #define USBD_CFG9_DSQSYNC_Pos (7) /*!< USBD_T::CFG9: DSQSYNC Position */ 2566 #define USBD_CFG9_DSQSYNC_Msk (0x1ul << USBD_CFG9_DSQSYNC_Pos) /*!< USBD_T::CFG9: DSQSYNC Mask */ 2567 2568 #define USBD_CFG9_CSTALL_Pos (9) /*!< USBD_T::CFG9: CSTALL Position */ 2569 #define USBD_CFG9_CSTALL_Msk (0x1ul << USBD_CFG9_CSTALL_Pos) /*!< USBD_T::CFG9: CSTALL Mask */ 2570 2571 #define USBD_CFG9_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG9: DBTGACTIVE Position */ 2572 #define USBD_CFG9_DBTGACTIVE_Msk (0x1ul << USBD_CFG9_DBTGACTIVE_Pos) /*!< USBD_T::CFG9: DBTGACTIVE Mask */ 2573 2574 #define USBD_CFG9_DBEN_Pos (11) /*!< USBD_T::CFG9: DBEN Position */ 2575 #define USBD_CFG9_DBEN_Msk (0x1ul << USBD_CFG9_DBEN_Pos) /*!< USBD_T::CFG9: DBEN Mask */ 2576 2577 #define USBD_CFGP9_CLRRDY_Pos (0) /*!< USBD_T::CFGP9: CLRRDY Position */ 2578 #define USBD_CFGP9_CLRRDY_Msk (0x1ul << USBD_CFGP9_CLRRDY_Pos) /*!< USBD_T::CFGP9: CLRRDY Mask */ 2579 2580 #define USBD_CFGP9_SSTALL_Pos (1) /*!< USBD_T::CFGP9: SSTALL Position */ 2581 #define USBD_CFGP9_SSTALL_Msk (0x1ul << USBD_CFGP9_SSTALL_Pos) /*!< USBD_T::CFGP9: SSTALL Mask */ 2582 2583 #define USBD_BUFSEG10_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG10: BUFSEG Position */ 2584 #define USBD_BUFSEG10_BUFSEG_Msk (0xfful << USBD_BUFSEG10_BUFSEG_Pos) /*!< USBD_T::BUFSEG10: BUFSEG Mask */ 2585 2586 #define USBD_MXPLD10_MXPLD_Pos (0) /*!< USBD_T::MXPLD10: MXPLD Position */ 2587 #define USBD_MXPLD10_MXPLD_Msk (0x7fful << USBD_MXPLD10_MXPLD_Pos) /*!< USBD_T::MXPLD10: MXPLD Mask */ 2588 2589 #define USBD_CFG10_EPNUM_Pos (0) /*!< USBD_T::CFG10: EPNUM Position */ 2590 #define USBD_CFG10_EPNUM_Msk (0xful << USBD_CFG10_EPNUM_Pos) /*!< USBD_T::CFG10: EPNUM Mask */ 2591 2592 #define USBD_CFG10_ISOCH_Pos (4) /*!< USBD_T::CFG10: ISOCH Position */ 2593 #define USBD_CFG10_ISOCH_Msk (0x1ul << USBD_CFG10_ISOCH_Pos) /*!< USBD_T::CFG10: ISOCH Mask */ 2594 2595 #define USBD_CFG10_STATE_Pos (5) /*!< USBD_T::CFG10: STATE Position */ 2596 #define USBD_CFG10_STATE_Msk (0x3ul << USBD_CFG10_STATE_Pos) /*!< USBD_T::CFG10: STATE Mask */ 2597 2598 #define USBD_CFG10_DSQSYNC_Pos (7) /*!< USBD_T::CFG10: DSQSYNC Position */ 2599 #define USBD_CFG10_DSQSYNC_Msk (0x1ul << USBD_CFG10_DSQSYNC_Pos) /*!< USBD_T::CFG10: DSQSYNC Mask */ 2600 2601 #define USBD_CFG10_CSTALL_Pos (9) /*!< USBD_T::CFG10: CSTALL Position */ 2602 #define USBD_CFG10_CSTALL_Msk (0x1ul << USBD_CFG10_CSTALL_Pos) /*!< USBD_T::CFG10: CSTALL Mask */ 2603 2604 #define USBD_CFG10_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG10: DBTGACTIVE Position */ 2605 #define USBD_CFG10_DBTGACTIVE_Msk (0x1ul << USBD_CFG10_DBTGACTIVE_Pos) /*!< USBD_T::CFG10: DBTGACTIVE Mask */ 2606 2607 #define USBD_CFG10_DBEN_Pos (11) /*!< USBD_T::CFG10: DBEN Position */ 2608 #define USBD_CFG10_DBEN_Msk (0x1ul << USBD_CFG10_DBEN_Pos) /*!< USBD_T::CFG10: DBEN Mask */ 2609 2610 #define USBD_CFGP10_CLRRDY_Pos (0) /*!< USBD_T::CFGP10: CLRRDY Position */ 2611 #define USBD_CFGP10_CLRRDY_Msk (0x1ul << USBD_CFGP10_CLRRDY_Pos) /*!< USBD_T::CFGP10: CLRRDY Mask */ 2612 2613 #define USBD_CFGP10_SSTALL_Pos (1) /*!< USBD_T::CFGP10: SSTALL Position */ 2614 #define USBD_CFGP10_SSTALL_Msk (0x1ul << USBD_CFGP10_SSTALL_Pos) /*!< USBD_T::CFGP10: SSTALL Mask */ 2615 2616 #define USBD_BUFSEG11_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG11: BUFSEG Position */ 2617 #define USBD_BUFSEG11_BUFSEG_Msk (0xfful << USBD_BUFSEG11_BUFSEG_Pos) /*!< USBD_T::BUFSEG11: BUFSEG Mask */ 2618 2619 #define USBD_MXPLD11_MXPLD_Pos (0) /*!< USBD_T::MXPLD11: MXPLD Position */ 2620 #define USBD_MXPLD11_MXPLD_Msk (0x7fful << USBD_MXPLD11_MXPLD_Pos) /*!< USBD_T::MXPLD11: MXPLD Mask */ 2621 2622 #define USBD_CFG11_EPNUM_Pos (0) /*!< USBD_T::CFG11: EPNUM Position */ 2623 #define USBD_CFG11_EPNUM_Msk (0xful << USBD_CFG11_EPNUM_Pos) /*!< USBD_T::CFG11: EPNUM Mask */ 2624 2625 #define USBD_CFG11_ISOCH_Pos (4) /*!< USBD_T::CFG11: ISOCH Position */ 2626 #define USBD_CFG11_ISOCH_Msk (0x1ul << USBD_CFG11_ISOCH_Pos) /*!< USBD_T::CFG11: ISOCH Mask */ 2627 2628 #define USBD_CFG11_STATE_Pos (5) /*!< USBD_T::CFG11: STATE Position */ 2629 #define USBD_CFG11_STATE_Msk (0x3ul << USBD_CFG11_STATE_Pos) /*!< USBD_T::CFG11: STATE Mask */ 2630 2631 #define USBD_CFG11_DSQSYNC_Pos (7) /*!< USBD_T::CFG11: DSQSYNC Position */ 2632 #define USBD_CFG11_DSQSYNC_Msk (0x1ul << USBD_CFG11_DSQSYNC_Pos) /*!< USBD_T::CFG11: DSQSYNC Mask */ 2633 2634 #define USBD_CFG11_CSTALL_Pos (9) /*!< USBD_T::CFG11: CSTALL Position */ 2635 #define USBD_CFG11_CSTALL_Msk (0x1ul << USBD_CFG11_CSTALL_Pos) /*!< USBD_T::CFG11: CSTALL Mask */ 2636 2637 #define USBD_CFG11_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG11: DBTGACTIVE Position */ 2638 #define USBD_CFG11_DBTGACTIVE_Msk (0x1ul << USBD_CFG11_DBTGACTIVE_Pos) /*!< USBD_T::CFG11: DBTGACTIVE Mask */ 2639 2640 #define USBD_CFG11_DBEN_Pos (11) /*!< USBD_T::CFG11: DBEN Position */ 2641 #define USBD_CFG11_DBEN_Msk (0x1ul << USBD_CFG11_DBEN_Pos) /*!< USBD_T::CFG11: DBEN Mask */ 2642 2643 #define USBD_CFGP11_CLRRDY_Pos (0) /*!< USBD_T::CFGP11: CLRRDY Position */ 2644 #define USBD_CFGP11_CLRRDY_Msk (0x1ul << USBD_CFGP11_CLRRDY_Pos) /*!< USBD_T::CFGP11: CLRRDY Mask */ 2645 2646 #define USBD_CFGP11_SSTALL_Pos (1) /*!< USBD_T::CFGP11: SSTALL Position */ 2647 #define USBD_CFGP11_SSTALL_Msk (0x1ul << USBD_CFGP11_SSTALL_Pos) /*!< USBD_T::CFGP11: SSTALL Mask */ 2648 2649 #define USBD_BUFSEG12_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG12: BUFSEG Position */ 2650 #define USBD_BUFSEG12_BUFSEG_Msk (0xfful << USBD_BUFSEG12_BUFSEG_Pos) /*!< USBD_T::BUFSEG12: BUFSEG Mask */ 2651 2652 #define USBD_MXPLD12_MXPLD_Pos (0) /*!< USBD_T::MXPLD12: MXPLD Position */ 2653 #define USBD_MXPLD12_MXPLD_Msk (0x7fful << USBD_MXPLD12_MXPLD_Pos) /*!< USBD_T::MXPLD12: MXPLD Mask */ 2654 2655 #define USBD_CFG12_EPNUM_Pos (0) /*!< USBD_T::CFG12: EPNUM Position */ 2656 #define USBD_CFG12_EPNUM_Msk (0xful << USBD_CFG12_EPNUM_Pos) /*!< USBD_T::CFG12: EPNUM Mask */ 2657 2658 #define USBD_CFG12_ISOCH_Pos (4) /*!< USBD_T::CFG12: ISOCH Position */ 2659 #define USBD_CFG12_ISOCH_Msk (0x1ul << USBD_CFG12_ISOCH_Pos) /*!< USBD_T::CFG12: ISOCH Mask */ 2660 2661 #define USBD_CFG12_STATE_Pos (5) /*!< USBD_T::CFG12: STATE Position */ 2662 #define USBD_CFG12_STATE_Msk (0x3ul << USBD_CFG12_STATE_Pos) /*!< USBD_T::CFG12: STATE Mask */ 2663 2664 #define USBD_CFG12_DSQSYNC_Pos (7) /*!< USBD_T::CFG12: DSQSYNC Position */ 2665 #define USBD_CFG12_DSQSYNC_Msk (0x1ul << USBD_CFG12_DSQSYNC_Pos) /*!< USBD_T::CFG12: DSQSYNC Mask */ 2666 2667 #define USBD_CFG12_CSTALL_Pos (9) /*!< USBD_T::CFG12: CSTALL Position */ 2668 #define USBD_CFG12_CSTALL_Msk (0x1ul << USBD_CFG12_CSTALL_Pos) /*!< USBD_T::CFG12: CSTALL Mask */ 2669 2670 #define USBD_CFG12_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG12: DBTGACTIVE Position */ 2671 #define USBD_CFG12_DBTGACTIVE_Msk (0x1ul << USBD_CFG12_DBTGACTIVE_Pos) /*!< USBD_T::CFG12: DBTGACTIVE Mask */ 2672 2673 #define USBD_CFG12_DBEN_Pos (11) /*!< USBD_T::CFG12: DBEN Position */ 2674 #define USBD_CFG12_DBEN_Msk (0x1ul << USBD_CFG12_DBEN_Pos) /*!< USBD_T::CFG12: DBEN Mask */ 2675 2676 #define USBD_CFGP12_CLRRDY_Pos (0) /*!< USBD_T::CFGP12: CLRRDY Position */ 2677 #define USBD_CFGP12_CLRRDY_Msk (0x1ul << USBD_CFGP12_CLRRDY_Pos) /*!< USBD_T::CFGP12: CLRRDY Mask */ 2678 2679 #define USBD_CFGP12_SSTALL_Pos (1) /*!< USBD_T::CFGP12: SSTALL Position */ 2680 #define USBD_CFGP12_SSTALL_Msk (0x1ul << USBD_CFGP12_SSTALL_Pos) /*!< USBD_T::CFGP12: SSTALL Mask */ 2681 2682 #define USBD_BUFSEG13_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG13: BUFSEG Position */ 2683 #define USBD_BUFSEG13_BUFSEG_Msk (0xfful << USBD_BUFSEG13_BUFSEG_Pos) /*!< USBD_T::BUFSEG13: BUFSEG Mask */ 2684 2685 #define USBD_MXPLD13_MXPLD_Pos (0) /*!< USBD_T::MXPLD13: MXPLD Position */ 2686 #define USBD_MXPLD13_MXPLD_Msk (0x7fful << USBD_MXPLD13_MXPLD_Pos) /*!< USBD_T::MXPLD13: MXPLD Mask */ 2687 2688 #define USBD_CFG13_EPNUM_Pos (0) /*!< USBD_T::CFG13: EPNUM Position */ 2689 #define USBD_CFG13_EPNUM_Msk (0xful << USBD_CFG13_EPNUM_Pos) /*!< USBD_T::CFG13: EPNUM Mask */ 2690 2691 #define USBD_CFG13_ISOCH_Pos (4) /*!< USBD_T::CFG13: ISOCH Position */ 2692 #define USBD_CFG13_ISOCH_Msk (0x1ul << USBD_CFG13_ISOCH_Pos) /*!< USBD_T::CFG13: ISOCH Mask */ 2693 2694 #define USBD_CFG13_STATE_Pos (5) /*!< USBD_T::CFG13: STATE Position */ 2695 #define USBD_CFG13_STATE_Msk (0x3ul << USBD_CFG13_STATE_Pos) /*!< USBD_T::CFG13: STATE Mask */ 2696 2697 #define USBD_CFG13_DSQSYNC_Pos (7) /*!< USBD_T::CFG13: DSQSYNC Position */ 2698 #define USBD_CFG13_DSQSYNC_Msk (0x1ul << USBD_CFG13_DSQSYNC_Pos) /*!< USBD_T::CFG13: DSQSYNC Mask */ 2699 2700 #define USBD_CFG13_CSTALL_Pos (9) /*!< USBD_T::CFG13: CSTALL Position */ 2701 #define USBD_CFG13_CSTALL_Msk (0x1ul << USBD_CFG13_CSTALL_Pos) /*!< USBD_T::CFG13: CSTALL Mask */ 2702 2703 #define USBD_CFG13_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG13: DBTGACTIVE Position */ 2704 #define USBD_CFG13_DBTGACTIVE_Msk (0x1ul << USBD_CFG13_DBTGACTIVE_Pos) /*!< USBD_T::CFG13: DBTGACTIVE Mask */ 2705 2706 #define USBD_CFG13_DBEN_Pos (11) /*!< USBD_T::CFG13: DBEN Position */ 2707 #define USBD_CFG13_DBEN_Msk (0x1ul << USBD_CFG13_DBEN_Pos) /*!< USBD_T::CFG13: DBEN Mask */ 2708 2709 #define USBD_CFGP13_CLRRDY_Pos (0) /*!< USBD_T::CFGP13: CLRRDY Position */ 2710 #define USBD_CFGP13_CLRRDY_Msk (0x1ul << USBD_CFGP13_CLRRDY_Pos) /*!< USBD_T::CFGP13: CLRRDY Mask */ 2711 2712 #define USBD_CFGP13_SSTALL_Pos (1) /*!< USBD_T::CFGP13: SSTALL Position */ 2713 #define USBD_CFGP13_SSTALL_Msk (0x1ul << USBD_CFGP13_SSTALL_Pos) /*!< USBD_T::CFGP13: SSTALL Mask */ 2714 2715 #define USBD_BUFSEG14_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG14: BUFSEG Position */ 2716 #define USBD_BUFSEG14_BUFSEG_Msk (0xfful << USBD_BUFSEG14_BUFSEG_Pos) /*!< USBD_T::BUFSEG14: BUFSEG Mask */ 2717 2718 #define USBD_MXPLD14_MXPLD_Pos (0) /*!< USBD_T::MXPLD14: MXPLD Position */ 2719 #define USBD_MXPLD14_MXPLD_Msk (0x7fful << USBD_MXPLD14_MXPLD_Pos) /*!< USBD_T::MXPLD14: MXPLD Mask */ 2720 2721 #define USBD_CFG14_EPNUM_Pos (0) /*!< USBD_T::CFG14: EPNUM Position */ 2722 #define USBD_CFG14_EPNUM_Msk (0xful << USBD_CFG14_EPNUM_Pos) /*!< USBD_T::CFG14: EPNUM Mask */ 2723 2724 #define USBD_CFG14_ISOCH_Pos (4) /*!< USBD_T::CFG14: ISOCH Position */ 2725 #define USBD_CFG14_ISOCH_Msk (0x1ul << USBD_CFG14_ISOCH_Pos) /*!< USBD_T::CFG14: ISOCH Mask */ 2726 2727 #define USBD_CFG14_STATE_Pos (5) /*!< USBD_T::CFG14: STATE Position */ 2728 #define USBD_CFG14_STATE_Msk (0x3ul << USBD_CFG14_STATE_Pos) /*!< USBD_T::CFG14: STATE Mask */ 2729 2730 #define USBD_CFG14_DSQSYNC_Pos (7) /*!< USBD_T::CFG14: DSQSYNC Position */ 2731 #define USBD_CFG14_DSQSYNC_Msk (0x1ul << USBD_CFG14_DSQSYNC_Pos) /*!< USBD_T::CFG14: DSQSYNC Mask */ 2732 2733 #define USBD_CFG14_CSTALL_Pos (9) /*!< USBD_T::CFG14: CSTALL Position */ 2734 #define USBD_CFG14_CSTALL_Msk (0x1ul << USBD_CFG14_CSTALL_Pos) /*!< USBD_T::CFG14: CSTALL Mask */ 2735 2736 #define USBD_CFG14_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG14: DBTGACTIVE Position */ 2737 #define USBD_CFG14_DBTGACTIVE_Msk (0x1ul << USBD_CFG14_DBTGACTIVE_Pos) /*!< USBD_T::CFG14: DBTGACTIVE Mask */ 2738 2739 #define USBD_CFG14_DBEN_Pos (11) /*!< USBD_T::CFG14: DBEN Position */ 2740 #define USBD_CFG14_DBEN_Msk (0x1ul << USBD_CFG14_DBEN_Pos) /*!< USBD_T::CFG14: DBEN Mask */ 2741 2742 #define USBD_CFGP14_CLRRDY_Pos (0) /*!< USBD_T::CFGP14: CLRRDY Position */ 2743 #define USBD_CFGP14_CLRRDY_Msk (0x1ul << USBD_CFGP14_CLRRDY_Pos) /*!< USBD_T::CFGP14: CLRRDY Mask */ 2744 2745 #define USBD_CFGP14_SSTALL_Pos (1) /*!< USBD_T::CFGP14: SSTALL Position */ 2746 #define USBD_CFGP14_SSTALL_Msk (0x1ul << USBD_CFGP14_SSTALL_Pos) /*!< USBD_T::CFGP14: SSTALL Mask */ 2747 2748 #define USBD_BUFSEG15_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG15: BUFSEG Position */ 2749 #define USBD_BUFSEG15_BUFSEG_Msk (0xfful << USBD_BUFSEG15_BUFSEG_Pos) /*!< USBD_T::BUFSEG15: BUFSEG Mask */ 2750 2751 #define USBD_MXPLD15_MXPLD_Pos (0) /*!< USBD_T::MXPLD15: MXPLD Position */ 2752 #define USBD_MXPLD15_MXPLD_Msk (0x7fful << USBD_MXPLD15_MXPLD_Pos) /*!< USBD_T::MXPLD15: MXPLD Mask */ 2753 2754 #define USBD_CFG15_EPNUM_Pos (0) /*!< USBD_T::CFG15: EPNUM Position */ 2755 #define USBD_CFG15_EPNUM_Msk (0xful << USBD_CFG15_EPNUM_Pos) /*!< USBD_T::CFG15: EPNUM Mask */ 2756 2757 #define USBD_CFG15_ISOCH_Pos (4) /*!< USBD_T::CFG15: ISOCH Position */ 2758 #define USBD_CFG15_ISOCH_Msk (0x1ul << USBD_CFG15_ISOCH_Pos) /*!< USBD_T::CFG15: ISOCH Mask */ 2759 2760 #define USBD_CFG15_STATE_Pos (5) /*!< USBD_T::CFG15: STATE Position */ 2761 #define USBD_CFG15_STATE_Msk (0x3ul << USBD_CFG15_STATE_Pos) /*!< USBD_T::CFG15: STATE Mask */ 2762 2763 #define USBD_CFG15_DSQSYNC_Pos (7) /*!< USBD_T::CFG15: DSQSYNC Position */ 2764 #define USBD_CFG15_DSQSYNC_Msk (0x1ul << USBD_CFG15_DSQSYNC_Pos) /*!< USBD_T::CFG15: DSQSYNC Mask */ 2765 2766 #define USBD_CFG15_CSTALL_Pos (9) /*!< USBD_T::CFG15: CSTALL Position */ 2767 #define USBD_CFG15_CSTALL_Msk (0x1ul << USBD_CFG15_CSTALL_Pos) /*!< USBD_T::CFG15: CSTALL Mask */ 2768 2769 #define USBD_CFG15_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG15: DBTGACTIVE Position */ 2770 #define USBD_CFG15_DBTGACTIVE_Msk (0x1ul << USBD_CFG15_DBTGACTIVE_Pos) /*!< USBD_T::CFG15: DBTGACTIVE Mask */ 2771 2772 #define USBD_CFG15_DBEN_Pos (11) /*!< USBD_T::CFG15: DBEN Position */ 2773 #define USBD_CFG15_DBEN_Msk (0x1ul << USBD_CFG15_DBEN_Pos) /*!< USBD_T::CFG15: DBEN Mask */ 2774 2775 #define USBD_CFGP15_CLRRDY_Pos (0) /*!< USBD_T::CFGP15: CLRRDY Position */ 2776 #define USBD_CFGP15_CLRRDY_Msk (0x1ul << USBD_CFGP15_CLRRDY_Pos) /*!< USBD_T::CFGP15: CLRRDY Mask */ 2777 2778 #define USBD_CFGP15_SSTALL_Pos (1) /*!< USBD_T::CFGP15: SSTALL Position */ 2779 #define USBD_CFGP15_SSTALL_Msk (0x1ul << USBD_CFGP15_SSTALL_Pos) /*!< USBD_T::CFGP15: SSTALL Mask */ 2780 2781 #define USBD_BUFSEG16_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG16: BUFSEG Position */ 2782 #define USBD_BUFSEG16_BUFSEG_Msk (0xfful << USBD_BUFSEG16_BUFSEG_Pos) /*!< USBD_T::BUFSEG16: BUFSEG Mask */ 2783 2784 #define USBD_MXPLD16_MXPLD_Pos (0) /*!< USBD_T::MXPLD16: MXPLD Position */ 2785 #define USBD_MXPLD16_MXPLD_Msk (0x7fful << USBD_MXPLD16_MXPLD_Pos) /*!< USBD_T::MXPLD16: MXPLD Mask */ 2786 2787 #define USBD_CFG16_EPNUM_Pos (0) /*!< USBD_T::CFG16: EPNUM Position */ 2788 #define USBD_CFG16_EPNUM_Msk (0xful << USBD_CFG16_EPNUM_Pos) /*!< USBD_T::CFG16: EPNUM Mask */ 2789 2790 #define USBD_CFG16_ISOCH_Pos (4) /*!< USBD_T::CFG16: ISOCH Position */ 2791 #define USBD_CFG16_ISOCH_Msk (0x1ul << USBD_CFG16_ISOCH_Pos) /*!< USBD_T::CFG16: ISOCH Mask */ 2792 2793 #define USBD_CFG16_STATE_Pos (5) /*!< USBD_T::CFG16: STATE Position */ 2794 #define USBD_CFG16_STATE_Msk (0x3ul << USBD_CFG16_STATE_Pos) /*!< USBD_T::CFG16: STATE Mask */ 2795 2796 #define USBD_CFG16_DSQSYNC_Pos (7) /*!< USBD_T::CFG16: DSQSYNC Position */ 2797 #define USBD_CFG16_DSQSYNC_Msk (0x1ul << USBD_CFG16_DSQSYNC_Pos) /*!< USBD_T::CFG16: DSQSYNC Mask */ 2798 2799 #define USBD_CFG16_CSTALL_Pos (9) /*!< USBD_T::CFG16: CSTALL Position */ 2800 #define USBD_CFG16_CSTALL_Msk (0x1ul << USBD_CFG16_CSTALL_Pos) /*!< USBD_T::CFG16: CSTALL Mask */ 2801 2802 #define USBD_CFG16_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG16: DBTGACTIVE Position */ 2803 #define USBD_CFG16_DBTGACTIVE_Msk (0x1ul << USBD_CFG16_DBTGACTIVE_Pos) /*!< USBD_T::CFG16: DBTGACTIVE Mask */ 2804 2805 #define USBD_CFG16_DBEN_Pos (11) /*!< USBD_T::CFG16: DBEN Position */ 2806 #define USBD_CFG16_DBEN_Msk (0x1ul << USBD_CFG16_DBEN_Pos) /*!< USBD_T::CFG16: DBEN Mask */ 2807 2808 #define USBD_CFGP16_CLRRDY_Pos (0) /*!< USBD_T::CFGP16: CLRRDY Position */ 2809 #define USBD_CFGP16_CLRRDY_Msk (0x1ul << USBD_CFGP16_CLRRDY_Pos) /*!< USBD_T::CFGP16: CLRRDY Mask */ 2810 2811 #define USBD_CFGP16_SSTALL_Pos (1) /*!< USBD_T::CFGP16: SSTALL Position */ 2812 #define USBD_CFGP16_SSTALL_Msk (0x1ul << USBD_CFGP16_SSTALL_Pos) /*!< USBD_T::CFGP16: SSTALL Mask */ 2813 2814 #define USBD_BUFSEG17_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG17: BUFSEG Position */ 2815 #define USBD_BUFSEG17_BUFSEG_Msk (0xfful << USBD_BUFSEG17_BUFSEG_Pos) /*!< USBD_T::BUFSEG17: BUFSEG Mask */ 2816 2817 #define USBD_MXPLD17_MXPLD_Pos (0) /*!< USBD_T::MXPLD17: MXPLD Position */ 2818 #define USBD_MXPLD17_MXPLD_Msk (0x7fful << USBD_MXPLD17_MXPLD_Pos) /*!< USBD_T::MXPLD17: MXPLD Mask */ 2819 2820 #define USBD_CFG17_EPNUM_Pos (0) /*!< USBD_T::CFG17: EPNUM Position */ 2821 #define USBD_CFG17_EPNUM_Msk (0xful << USBD_CFG17_EPNUM_Pos) /*!< USBD_T::CFG17: EPNUM Mask */ 2822 2823 #define USBD_CFG17_ISOCH_Pos (4) /*!< USBD_T::CFG17: ISOCH Position */ 2824 #define USBD_CFG17_ISOCH_Msk (0x1ul << USBD_CFG17_ISOCH_Pos) /*!< USBD_T::CFG17: ISOCH Mask */ 2825 2826 #define USBD_CFG17_STATE_Pos (5) /*!< USBD_T::CFG17: STATE Position */ 2827 #define USBD_CFG17_STATE_Msk (0x3ul << USBD_CFG17_STATE_Pos) /*!< USBD_T::CFG17: STATE Mask */ 2828 2829 #define USBD_CFG17_DSQSYNC_Pos (7) /*!< USBD_T::CFG17: DSQSYNC Position */ 2830 #define USBD_CFG17_DSQSYNC_Msk (0x1ul << USBD_CFG17_DSQSYNC_Pos) /*!< USBD_T::CFG17: DSQSYNC Mask */ 2831 2832 #define USBD_CFG17_CSTALL_Pos (9) /*!< USBD_T::CFG17: CSTALL Position */ 2833 #define USBD_CFG17_CSTALL_Msk (0x1ul << USBD_CFG17_CSTALL_Pos) /*!< USBD_T::CFG17: CSTALL Mask */ 2834 2835 #define USBD_CFG17_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG17: DBTGACTIVE Position */ 2836 #define USBD_CFG17_DBTGACTIVE_Msk (0x1ul << USBD_CFG17_DBTGACTIVE_Pos) /*!< USBD_T::CFG17: DBTGACTIVE Mask */ 2837 2838 #define USBD_CFG17_DBEN_Pos (11) /*!< USBD_T::CFG17: DBEN Position */ 2839 #define USBD_CFG17_DBEN_Msk (0x1ul << USBD_CFG17_DBEN_Pos) /*!< USBD_T::CFG17: DBEN Mask */ 2840 2841 #define USBD_CFGP17_CLRRDY_Pos (0) /*!< USBD_T::CFGP17: CLRRDY Position */ 2842 #define USBD_CFGP17_CLRRDY_Msk (0x1ul << USBD_CFGP17_CLRRDY_Pos) /*!< USBD_T::CFGP17: CLRRDY Mask */ 2843 2844 #define USBD_CFGP17_SSTALL_Pos (1) /*!< USBD_T::CFGP17: SSTALL Position */ 2845 #define USBD_CFGP17_SSTALL_Msk (0x1ul << USBD_CFGP17_SSTALL_Pos) /*!< USBD_T::CFGP17: SSTALL Mask */ 2846 2847 #define USBD_BUFSEG18_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG18: BUFSEG Position */ 2848 #define USBD_BUFSEG18_BUFSEG_Msk (0xfful << USBD_BUFSEG18_BUFSEG_Pos) /*!< USBD_T::BUFSEG18: BUFSEG Mask */ 2849 2850 #define USBD_MXPLD18_MXPLD_Pos (0) /*!< USBD_T::MXPLD18: MXPLD Position */ 2851 #define USBD_MXPLD18_MXPLD_Msk (0x7fful << USBD_MXPLD18_MXPLD_Pos) /*!< USBD_T::MXPLD18: MXPLD Mask */ 2852 2853 #define USBD_CFG18_EPNUM_Pos (0) /*!< USBD_T::CFG18: EPNUM Position */ 2854 #define USBD_CFG18_EPNUM_Msk (0xful << USBD_CFG18_EPNUM_Pos) /*!< USBD_T::CFG18: EPNUM Mask */ 2855 2856 #define USBD_CFG18_ISOCH_Pos (4) /*!< USBD_T::CFG18: ISOCH Position */ 2857 #define USBD_CFG18_ISOCH_Msk (0x1ul << USBD_CFG18_ISOCH_Pos) /*!< USBD_T::CFG18: ISOCH Mask */ 2858 2859 #define USBD_CFG18_STATE_Pos (5) /*!< USBD_T::CFG18: STATE Position */ 2860 #define USBD_CFG18_STATE_Msk (0x3ul << USBD_CFG18_STATE_Pos) /*!< USBD_T::CFG18: STATE Mask */ 2861 2862 #define USBD_CFG18_DSQSYNC_Pos (7) /*!< USBD_T::CFG18: DSQSYNC Position */ 2863 #define USBD_CFG18_DSQSYNC_Msk (0x1ul << USBD_CFG18_DSQSYNC_Pos) /*!< USBD_T::CFG18: DSQSYNC Mask */ 2864 2865 #define USBD_CFG18_CSTALL_Pos (9) /*!< USBD_T::CFG18: CSTALL Position */ 2866 #define USBD_CFG18_CSTALL_Msk (0x1ul << USBD_CFG18_CSTALL_Pos) /*!< USBD_T::CFG18: CSTALL Mask */ 2867 2868 #define USBD_CFG18_DBTGACTIVE_Pos (10) /*!< USBD_T::CFG18: DBTGACTIVE Position */ 2869 #define USBD_CFG18_DBTGACTIVE_Msk (0x1ul << USBD_CFG18_DBTGACTIVE_Pos) /*!< USBD_T::CFG18: DBTGACTIVE Mask */ 2870 2871 #define USBD_CFG18_DBEN_Pos (11) /*!< USBD_T::CFG18: DBEN Position */ 2872 #define USBD_CFG18_DBEN_Msk (0x1ul << USBD_CFG18_DBEN_Pos) /*!< USBD_T::CFG18: DBEN Mask */ 2873 2874 #define USBD_CFGP18_CLRRDY_Pos (0) /*!< USBD_T::CFGP18: CLRRDY Position */ 2875 #define USBD_CFGP18_CLRRDY_Msk (0x1ul << USBD_CFGP18_CLRRDY_Pos) /*!< USBD_T::CFGP18: CLRRDY Mask */ 2876 2877 #define USBD_CFGP18_SSTALL_Pos (1) /*!< USBD_T::CFGP18: SSTALL Position */ 2878 #define USBD_CFGP18_SSTALL_Msk (0x1ul << USBD_CFGP18_SSTALL_Pos) /*!< USBD_T::CFGP18: SSTALL Mask */ 2879 2880 /**@}*/ /* USBD_CONST */ 2881 /**@}*/ /* end of USBD register group */ 2882 2883 2884 /**@}*/ /* end of REGISTER group */ 2885
