1 /******************************************************************************* 2 * @file rsi_ulpss_clk.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 /** 31 * Includes 32 */ 33 34 #ifndef __RSI_ULPSS_CLK_H__ 35 #define __RSI_ULPSS_CLK_H__ 36 37 #include "rsi_ccp_common.h" 38 #include "rsi_error.h" 39 #include "rsi_pll.h" 40 #include "rsi_ulpss_clk.h" 41 #include "rsi_power_save.h" 42 43 /*requied delays for turn on the clocks in micro seconds*/ 44 #define MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 40MHZ CLK*/ 45 #define MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP DOUBLER CLK*/ 46 #define MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 20MHZ_RING_OSC CLK*/ 47 #define MCU_ULP_MHZ_RC_CLK_EN_TRUN_ON_DELAY 2 /* delay to enable the ULP MHZ_RC CLK*/ 48 #define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1 500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ 49 #define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2 1500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ 50 #define MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY 250 /* delay to enable the ULP 32KHZ_RO CLK*/ 51 #define MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY 150 /* delay to enable the ULP 32KHZ_RC CLK*/ 52 53 /*Clock enable Bits */ 54 #define TOUCH_SENSOR_PCLK_ENABLE BIT(31) /* Enables TOUCH_SENSOR_PCLK_ENABLE */ 55 #define FIM_AHB_CLK_ENABLE BIT(30) /* Enables FIM_AHB_CLK_ENABLE */ 56 #define ULPSS_TASS_QUASI_SYNC BIT(27) /* Enables ULPSS_TASS_QUASI_SYNC */ 57 #define ULPSS_M4SS_SLV_SEL BIT(26) /* Enables ULPSS_M4SS_SLV_SEL */ 58 #define AUX_SOC_EXT_TRIG_2_SEL BIT(25) /* Enables TOUCH_SENSOR_PCLK_ENABLE */ 59 #define AUX_SOC_EXT_TRIG_1_SEL BIT(24) /* Enables AUX_SOC_EXT_TRIG_1_SEL */ 60 #define AUX_ULP_EXT_TRIG_2_SEL BIT(23) /* Enables AUX_ULP_EXT_TRIG_2_SEL */ 61 #define AUX_ULP_EXT_TRIG_1_SEL BIT(22) /* Enables AUX_ULP_EXT_TRIG_1_SEL */ 62 #define TIMER_PCLK_EN BIT(21) /* Enables TIMER_PCLK_EN */ 63 #define EGPIO_PCLK_EN BIT(20) /* Enables EGPIO_PCLK_EN */ 64 #define EGPIO_PCLK_DYN_CTRL_DISABLE_ULP BIT(19) /* Enables EGPIO_PCLK_DYN_CTRL_DISABLE_ULP */ 65 #define CLK_ENABLE_ULP_MEMORIES BIT(18) /* Enables CLK_ENABLE_ULP_MEMORIES */ 66 #define VAD_CLK_EN BIT(17) /* Enables VAD_CLK_EN */ 67 #define FIM_CLK_EN BIT(16) /* Enables FIM_CLK_EN */ 68 #define REG_ACCESS_SPI_CLK_EN BIT(15) /* Enables REG_ACCESS_SPI_CLK_EN */ 69 #define EGPIO_CLK_EN BIT(14) /* Enables EGPIO_CLK_EN */ 70 #define CLK_ENABLE_TIMER BIT(13) /* Enables CLK_ENABLE_TIMER */ 71 #define VAD_PCLK_ENABLE BIT(12) /* Enables VAD_PCLK_ENABLE */ 72 #define FIM_PCLK_ENABLE BIT(11) /* Enables FIM_PCLK_ENABLE */ 73 #define SCLK_ENABLE_UART BIT(10) /* Enables SCLK_ENABLE_UART */ 74 #define PCLK_ENABLE_UART BIT(9) /* Enables PCLK_ENABLE_UART */ 75 #define SCLK_ENABLE_SSI_MASTER BIT(8) /* Enables SCLK_ENABLE_SSI_MASTER */ 76 #define PCLK_ENABLE_SSI_MASTER BIT(7) /* Enables PCLK_ENABLE_SSI_MASTER */ 77 #define CLK_ENABLE_I2S BIT(6) /* Enables CLK_ENABLE_I2S */ 78 #define PCLK_ENABLE_I2C BIT(5) /* Enables PCLK_ENABLE_I2C */ 79 #define IR_PCLK_EN BIT(4) /* Enables IR_PCLK_EN */ 80 #define PCM_FSYNC_START BIT(1) /* Enables PCM_FSYNC_START */ 81 #define PCM_ENABLE BIT(0) /* Enables PCM_ENABLE */ 82 83 #define I2C_PCLK_DYN_CTRL_DISABLE BIT(0) /* Enables PCM_ENABLE */ 84 #define I2S_CLK_DYN_CTRL_DISABLE BIT(1) 85 #define ULP_SSI_MST_PCLK_DYN_CTRL_DISABLE BIT(2) 86 #define ULP_SSI_MST_SCLK_DYN_CTRL_DISABLE BIT(3) 87 #define UART_CLK_DYN_CTRL_DISABLE BIT(4) 88 #define UART_SCLK_DYN_CTRL_DISABLE BIT(5) 89 #define ULP_TIMER_PCLK_DYN_CTRL_DISABLE BIT(6) 90 #define ULP_TIMER_SCLK_DYN_CTRL_DISABLE BIT(7) 91 #define REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE BIT(8) 92 #define FIM_CLK_DYN_CTRL_DISABLE BIT(9) 93 #define VAD_CLK_DYN_CTRL_DISABLE BIT(10) 94 #define AUX_PCLK_EN BIT(11) 95 #define AUX_CLK_EN BIT(12) 96 #define AUX_MEM_EN BIT(13) 97 #define AUX_PCLK_DYN_CTRL_DISABLE BIT(14) 98 #define AUX_CLK_DYN_CTRL_DISABLE BIT(15) 99 #define AUX_CLK_MEM_DYN_CTRL_DISABLE BIT(16) 100 #define UDMA_CLK_ENABLE BIT(17) 101 #define IR_CLK_ENABLE BIT(18) 102 #define IR_CLK_DYN_CTRL_DISABLE BIT(19) 103 104 /*ULP PROCESSOR CLOCK */ 105 #define ULP_PROC_MAX_SEL 7 /* Maximum Seletion value for ulp processor clock source*/ 106 #define ULP_PROC_MIN_SEL 0 /* Minimum Seletion value for ulp processor clock source*/ 107 #define ULP_PROC_MAX_DIVISOIN_FACTOR 255 /* Maximum division factor value for ulp processor clock*/ 108 #define ULP_PROC_MIN_DIVISOIN_FACTOR 0 /* Minimum division factor value for ulp processor clock*/ 109 110 /*ULP SSI CLOCK*/ 111 #define ULP_SSI_MAX_SEL 6 /* Maximum Seletion value for ulp SSI clock source*/ 112 #define ULP_SSI_MIN_SEL 0 /* Minimum Seletion value for ulp SSI clock source*/ 113 #define ULP_SSI_MAX_DIVISION_FACTOR 127 /* Maximum division factor value for ulp SSI clock*/ 114 #define ULP_SSI_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp SSI clock*/ 115 116 /*ULP I2S CLOCK*/ 117 #define ULP_I2S_MAX_SEL 8 /* Maximum Seletion value for ulp I2S clock source*/ 118 #define ULP_I2S_MIN_SEL 0 /* Minimum Seletion value for ulp I2S clock source*/ 119 #define ULP_I2S_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp SSI clock*/ 120 #define ULP_I2S_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp SSI clock*/ 121 122 /*ULP UART CLOCK*/ 123 #define ULP_UART_MAX_SEL 7 /* Maximum Seletion value for ulp Uart clock source*/ 124 #define ULP_UART_MIN_SEL 0 /* Minimum Seletion value for ulp Uart clock source*/ 125 #define ULP_UART_MAX_DIVISION_FACTOR 7 /* Maximum division factor value for ulp Uart clock*/ 126 #define ULP_UART_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Uart clock*/ 127 128 /*ULP AUX CLOCK*/ 129 #define ULP_AUX_MAX_SEL 8 /* Maximum Seletion value for ulp Aux clock source*/ 130 #define ULP_AUX_MIN_SEL 0 /* Minimum Seletion value for ulp Aux clock source*/ 131 #define ULP_AUX_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Aux clock*/ 132 #define ULP_AUX_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Aux clock*/ 133 134 /*ULP TIMER CLOCK*/ 135 #define ULP_TIMER_MAX_SEL 6 /* Maximum Seletion value for ulp Timer clock source*/ 136 #define ULP_TIMER_MIN_SEL 0 /* Minimum Seletion value for ulp Tiemer clock source*/ 137 138 /*ULP VAD CLOCK*/ 139 #define ULP_VAD_MAX_SEL 8 /* Maximum Seletion value for ulp Vad clock source*/ 140 #define ULP_VAD_MIN_SEL 0 /* Minimum Seletion value for ulp Vad clock source*/ 141 #define ULP_VAD_FCLK_MAX_SEL 8 /* Maximum Seletion value for ulp Vad fclock source*/ 142 #define ULP_VAD_FCLK_MIN_SEL 0 /* Minimum Seletion value for ulp Vad fclock source*/ 143 #define ULP_VAD_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Vad clock*/ 144 #define ULP_VAD_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Vad clock*/ 145 146 /*ULP TOUCH CLOCK*/ 147 #define ULP_TOUCH_MAX_SEL 6 /* Maximum Seletion value for ulp Touch clock source*/ 148 #define ULP_TOUCH_MIN_SEL 0 /* Minimum Seletion value for ulp Touch clock source*/ 149 #define ULP_TOUCH_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Touch clock*/ 150 #define ULP_TOUCH_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Touch clock*/ 151 152 /*ULP SLEEP SENSOR */ 153 #define ULP_SLP_SENSOR_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Sleep sensor clock*/ 154 #define ULP_SLP_SENSOR_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Sleep sensor clock*/ 155 /** 156 *@brief ulpss Reference Input clock source selection 157 **/ 158 typedef enum ULPSS_REF_CLK_SEL { 159 ULPSS_REF_BYP_CLK = 1, /*!< REF_BYP_CLK selection*/ 160 ULPSS_ULP_MHZ_RC_CLK = 2, /*!< ULP_MHZ_RC_CLK selection*/ 161 ULPSS_40MHZ_CLK = 3, /*!< EXT_40MHZ_CLK selection*/ 162 ULPSS_MEMS_REF_CLK = 4, /*!< MEMS_REF_CLK selection*/ 163 ULPSS_ULP_20MHZ_RINGOSC_CLK = 5, /*!< ULP_20MHZ_RINGOSC_CLK selection*/ 164 ULPSS_ULP_DOUBLER_CLK = 6, /*!< ULP_DOUBLER_CLK selection*/ 165 } ULPSS_REF_CLK_SEL_T; 166 /** 167 *@brief Different possible ref_clk sources for Ulp_proc_clk 168 **/ 169 typedef enum ULP_PROC_CLK_SELECT { 170 ULP_PROC_REF_CLK, /*!< ULP_REF_CLK selection*/ 171 ULP_PROC_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 172 ULP_PROC_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 173 ULP_PROC_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 174 ULP_PROC_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 175 ULP_PROC_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 176 ULP_PROC_SOC_CLK, /*!< SOC_CLK selection*/ 177 ULP_PROC_ULP_DOUBLER_CLK /*!< ULP_DOUBLER_CLK selection*/ 178 } ULP_PROC_CLK_SELECT_T; 179 /** 180 *@brief Different possible input clk sources for Ulp_SSI_clk 181 **/ 182 typedef enum ULP_SSI_CLK_SELECT { 183 184 ULP_SSI_REF_CLK, /*!< ULP_REF_CLK selection*/ 185 ULP_SSI_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 186 ULP_SSI_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 187 ULP_SSI_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 188 ULP_SSI_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 189 ULP_SSI_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 190 ULP_SSI_SOC_CLK, /*!< SOC_CLK selection*/ 191 } ULP_SSI_CLK_SELECT_T; 192 /** 193 *@brief Different possible input clk sources for Ulp_I2S_clk 194 **/ 195 typedef enum ULP_I2S_CLK_SELECT { 196 197 ULP_I2S_REF_CLK, /*!< ULP_REF_CLK selection*/ 198 ULP_I2S_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 199 ULP_I2S_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 200 ULP_I2S_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 201 ULP_I2S_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 202 ULP_I2S_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 203 ULP_I2S_SOC_CLK, /*!< SOC_CLK selection*/ 204 ULP_I2S_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ 205 ULP_I2S_PLL_CLK /*!< I2s_PLL_CLK selection*/ 206 207 } ULP_I2S_CLK_SELECT_T; 208 /** 209 *@brief Different possible input clk sources for Ulp_Uart_clk 210 **/ 211 typedef enum ULP_UART_CLK_SELECT { 212 213 ULP_UART_REF_CLK, /*!< ULP_REF_CLK selection*/ 214 ULP_UART_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 215 ULP_UART_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 216 ULP_UART_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 217 ULP_UART_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 218 ULP_UART_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 219 ULP_UART_SOC_CLK, /*!< SOC_CLK selection*/ 220 ULP_UART_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ 221 } ULP_UART_CLK_SELECT_T; 222 /** 223 *@brief Different possible input clk sources for Ulp_Timer_clk 224 **/ 225 typedef enum ULP_TIMER_CLK_SELECT { 226 227 ULP_TIMER_REF_CLK, /*!< ULP_REF_CLK selection*/ 228 ULP_TIMER_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 229 ULP_TIMER_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 230 ULP_TIMER_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 231 ULP_TIMER_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 232 ULP_TIMER_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 233 ULP_TIMER_ULP_SOC_CLK, /*!< SOC_CLK selection*/ 234 } ULP_TIMER_CLK_SELECT_T; 235 /** 236 *@brief Different possible input clk sources for Ulp_AUX_clk 237 **/ 238 typedef enum ULP_AUX_CLK_SELECT { 239 240 ULP_AUX_REF_CLK, /*!< ULP_REF_CLK selection*/ 241 ULP_AUX_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 242 ULP_AUX_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 243 ULP_AUX_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 244 ULP_AUX_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 245 ULP_AUX_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 246 ULP_AUX_ULP_SOC_CLK, /*!< SOC_CLK selection*/ 247 ULP_AUX_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ 248 ULP_AUX_I2S_PLL_CLK /*!< I2s_PLL_CLK selection*/ 249 } ULP_AUX_CLK_SELECT_T; 250 /** 251 *@brief Different possible input clk sources for Ulp_Vad_clk 252 **/ 253 typedef enum ULP_VAD_CLK_SELECT { 254 255 ULP_VAD_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 256 ULP_VAD_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 257 ULP_VAD_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 258 } ULP_VAD_CLK_SELECT_T; 259 /** 260 *@brief Different possible input clk sources for Ulp_Vad_fclk 261 **/ 262 typedef enum ULP_VAD_FCLK_SELECT { 263 264 ULP_VAD_ULP_PROCESSOR_CLK, /*!< ULP_PROCESSOR_CLK selection*/ 265 ULP_VAD_REF_CLK, /*!< ULP_REF_CLK selection*/ 266 ULP_VAD_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 267 ULP_VAD_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 268 ULP_VAD_ULP_SOC_CLK, /*!< SOC_CLK selection*/ 269 } ULP_VAD_FCLK_SELECT_T; 270 /** 271 *@brief Different possible input clk sources for Ulp_Touch_clk 272 **/ 273 typedef enum ULP_TOUCH_CLK_SELECT { 274 275 ULP_TOUCH_REF_CLK, /*!< ULP_REF_CLK selection*/ 276 ULP_TOUCH_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ 277 ULP_TOUCH_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ 278 ULP_TOUCH_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ 279 ULP_TOUCH_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ 280 ULP_TOUCH_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ 281 ULP_TOUCH_ULP_SOC_CLK /*!< SOC_CLK selection*/ 282 283 } ULP_TOUCH_CLK_SELECT_T; 284 285 /** 286 *@brief list of peripherals, particular ulp clock that to be disabled 287 **/ 288 typedef enum ULPPERIPHERALS_CLK { 289 ULP_I2C_CLK, /*!< Enables or Disables ULP_I2C Peripheral clock when it is passed */ 290 ULP_EGPIO_CLK, /*!< Enables or Disables Ulp_Egpio Peripheral clock when it is passed */ 291 ULP_AUX_CLK, /*!< Enables or Disables Ulp_Aux Peripheral clock when it is passed */ 292 ULP_FIM_CLK, /*!< Enables or Disables Ulp_Fim Peripheral clock when it is passed */ 293 ULP_VAD_CLK, /*!< Enables or Disables Ulp_Vad Peripheral clock when it is passed */ 294 ULP_TIMER_CLK, /*!< Enables or Disables Ulp_Timer Peripheral clock when it is passed */ 295 ULP_UDMA_CLK, /*!< Enables or Disables Ulp_Udma Peripheral clock when it is passed */ 296 ULP_TOUCH_CLK, /*!< Enables or Disables Ulp_Touch Peripheral clock when it is passed */ 297 ULP_UART_CLK, /*!< Enables or Disables Ulp_Uart Peripheral clock when it is passed */ 298 ULP_SSI_CLK, /*!< Enables or Disables Ulp_SSI Peripheral clock when it is passed */ 299 ULP_I2S_CLK, /*!< Enables or Disables Ulp_I2S Peripheral clock when it is passed */ 300 } ULPPERIPHERALS_CLK_T; 301 302 rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, 303 ULP_PROC_CLK_SELECT_T clkSource, 304 uint16_t divFactor, 305 cdDelay delayFn); 306 rsi_error_t ulpss_ref_clk_config(ULPSS_REF_CLK_SEL_T clkSource); 307 308 rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); 309 310 rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, 311 ULP_PROC_CLK_SELECT_T clkSource, 312 uint16_t divFactor, 313 cdDelay delayFn); 314 315 rsi_error_t ulpss_ulp_peri_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 316 317 rsi_error_t ulpss_ulp_peri_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 318 319 rsi_error_t ulpss_ulp_dyn_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 320 321 rsi_error_t ulpss_ulp_dyn_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 322 323 rsi_error_t ulpss_ulp_ssi_clk_config(ULPCLK_Type *pULPCLK, 324 CLK_ENABLE_T clkType, 325 ULP_SSI_CLK_SELECT_T clkSource, 326 uint16_t divFactor); 327 328 rsi_error_t ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); 329 330 rsi_error_t ulpss_ulp_uar_clk_config(ULPCLK_Type *pULPCLK, 331 CLK_ENABLE_T clkType, 332 boolean_t bFrClkSel, 333 ULP_UART_CLK_SELECT_T clkSource, 334 uint16_t divFactor); 335 336 rsi_error_t ulpss_time_clk_config(ULPCLK_Type *pULPCLK, 337 CLK_ENABLE_T clkType, 338 boolean_t bTmrSync, 339 ULP_TIMER_CLK_SELECT_T clkSource, 340 uint8_t skipSwitchTime); 341 342 rsi_error_t ulpss_aux_clk_config(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); 343 344 rsi_error_t ulpss_vad_clk_config(ULPCLK_Type *pULPCLK, 345 ULP_VAD_CLK_SELECT_T clkSource, 346 ULP_VAD_FCLK_SELECT_T FclkSource, 347 uint16_t divFactor); 348 349 rsi_error_t ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); 350 351 rsi_error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); 352 353 rsi_error_t ulpss_peripheral_enable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); 354 355 rsi_error_t ulpss_peripheral_disable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); 356 357 rsi_error_t ulpss_time_clk_disable(ULPCLK_Type *pULPCLK); 358 359 #endif /*__RSI_ULPSS_CLK_H__*/ 360
