Searched defs:ULPS_CTRL (Results 1 – 14 of 14) sorted by relevance
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/ |
| D | MIMX8DX2_cm4.h | 91822 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/ |
| D | MIMX8DX1_cm4.h | 91822 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/ |
| D | MIMX8QX2_cm4.h | 91823 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/ |
| D | MIMX8QX1_cm4.h | 91823 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/ |
| D | MIMX8QX4_cm4.h | 121911 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/ |
| D | MIMX8QX5_cm4.h | 121913 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/ |
| D | MIMX8UX6_cm4.h | 121913 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/ |
| D | MIMX8QX6_cm4.h | 121913 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/ |
| D | MIMX8UX5_cm4.h | 121913 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/ |
| D | MIMX8DX5_cm4.h | 121912 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/ |
| D | MIMX8DX6_cm4.h | 121912 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/ |
| D | MIMX8DX4_cm4.h | 121910 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/ |
| D | MIMX8DX3_cm4.h | 121910 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/ |
| D | MIMX8QX3_cm4.h | 121911 __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ member
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