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Searched defs:UFCR (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h50355 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h50353 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h50355 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_ca53.h50367 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
DMIMX8MN6_cm7.h50353 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h50355 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h50353 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h55675 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h53502 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h55675 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h55675 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h55675 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h35083 …__IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x… member
/hal_nxp-3.5.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h41331 …__IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h69163 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h69163 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h69163 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h69163 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h69163 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h69163 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
DMIMX8MM6_ca53.h68628 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_ca53.h96389 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
DMIMX8ML8_dsp.h92340 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
DMIMX8ML8_cm7.h96356 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h96356 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ member

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