1 /* 2 * Copyright (c) 2020 PHYTEC Messtechnik GmbH 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_ 8 #define ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_ 9 10 /* UC8176/UC8179 */ 11 #define UC81XX_CMD_PSR 0x00 12 #define UC81XX_CMD_PWR 0x01 13 #define UC81XX_CMD_POF 0x02 14 #define UC81XX_CMD_PFS 0x03 15 #define UC81XX_CMD_PON 0x04 16 #define UC81XX_CMD_PMES 0x05 17 #define UC81XX_CMD_BTST 0x06 18 #define UC81XX_CMD_DSLP 0x07 19 #define UC81XX_CMD_DTM1 0x10 20 #define UC81XX_CMD_DSP 0x11 21 #define UC81XX_CMD_DRF 0x12 22 23 /* UC8179 only */ 24 #define UC81XX_CMD_DTM2 0x13 25 #define UC81XX_CMD_DUSPI 0x15 26 #define UC81XX_CMD_AUTO 0x17 27 #define UC81XX_CMD_LUTOPT 0x2A 28 #define UC81XX_CMD_KWOPT 0x2B 29 30 #define UC81XX_CMD_LUTC 0x20 31 #define UC81XX_CMD_LUTWW 0x21 32 #define UC81XX_CMD_LUTKW 0x22 33 #define UC81XX_CMD_LUTWK 0x23 34 #define UC81XX_CMD_LUTKK 0x24 35 #define UC81XX_CMD_LUTBD 0x25 36 37 /* UC8176/UC8179 */ 38 #define UC81XX_CMD_PLL 0x30 39 #define UC81XX_CMD_TSC 0x40 40 #define UC81XX_CMD_TSE 0x41 41 #define UC81XX_CMD_TSW 0x42 42 #define UC81XX_CMD_TSR 0x43 43 44 /* UC8179 */ 45 #define UC81XX_CMD_PBC 0x44 46 47 /* UC8176/UC8179 - different register layouts */ 48 #define UC81XX_CMD_CDI 0x50 49 /* UC8176/UC8179 */ 50 #define UC81XX_CMD_LPD 0x51 51 52 /* UC8179 */ 53 #define UC81XX_CMD_EVS 0x52 54 55 /* UC8176/UC8179 */ 56 #define UC81XX_CMD_TCON 0x60 57 #define UC81XX_CMD_TRES 0x61 58 #define UC81XX_CMD_GSST 0x65 59 #define UC81XX_CMD_REV 0x70 60 #define UC81XX_CMD_FLG 0x71 61 #define UC81XX_CMD_AMV 0x80 62 #define UC81XX_CMD_VV 0x81 63 #define UC81XX_CMD_VDCS 0x82 64 #define UC81XX_CMD_PTL 0x90 65 #define UC81XX_CMD_PTIN 0x91 66 #define UC81XX_CMD_PTOUT 0x92 67 #define UC81XX_CMD_PGM 0xA0 68 #define UC81XX_CMD_APG 0xA1 69 #define UC81XX_CMD_ROTP 0xA2 70 #define UC81XX_CMD_CCSET 0xE0 71 #define UC81XX_CMD_PWS 0xE3 72 73 /* UC8179 */ 74 #define UC81XX_CMD_LVSEL 0xE4 75 76 /* UC8176/UC8179 */ 77 #define UC81XX_CMD_TSSET 0xE5 78 79 /* UC8179 */ 80 #define UC81XX_CMD_TSBDRY 0xE7 81 82 #define UC81XX_PSR_REG BIT(5) 83 #define UC81XX_PSR_KW_R BIT(4) 84 #define UC81XX_PSR_UD BIT(3) 85 #define UC81XX_PSR_SHL BIT(2) 86 #define UC81XX_PSR_SHD BIT(1) 87 #define UC81XX_PSR_RST BIT(0) 88 89 #define UC81XX_AUTO_PON_DRF_POF 0xA5 90 #define UC81XX_AUTO_PON_DRF_POF_DSLP 0xA7 91 92 #define UC8176_CDI_VBD_MASK 0xc0 93 #define UC8176_CDI_VBD0 BIT(6) 94 #define UC8176_CDI_VBD1 BIT(7) 95 #define UC8176_CDI_DDX1 BIT(5) 96 #define UC8176_CDI_DDX0 BIT(4) 97 #define UC8176_CDI_CDI_MASK 0x0f 98 99 #define UC8179_CDI_REG_LENGTH 2U 100 #define UC8179_CDI_BDZ_DDX_IDX 0 101 #define UC8179_CDI_CDI_IDX 1 102 #define UC8179_CDI_BDZ BIT(7) 103 #define UC8179_CDI_BDV1 BIT(5) 104 #define UC8179_CDI_BDV0 BIT(4) 105 #define UC8179_CDI_N2OCP BIT(3) 106 #define UC8179_CDI_DDX1 BIT(1) 107 #define UC8179_CDI_DDX0 BIT(0) 108 109 struct uc81xx_tres8 { 110 uint8_t hres; 111 uint8_t vres; 112 } __packed; 113 114 BUILD_ASSERT(sizeof(struct uc81xx_tres8) == 2); 115 116 struct uc81xx_ptl8 { 117 uint8_t hrst; 118 uint8_t hred; 119 uint8_t vrst; 120 uint8_t vred; 121 uint8_t flags; 122 } __packed; 123 124 BUILD_ASSERT(sizeof(struct uc81xx_ptl8) == 5); 125 126 struct uc81xx_tres16 { 127 uint16_t hres; 128 uint16_t vres; 129 } __packed; 130 131 BUILD_ASSERT(sizeof(struct uc81xx_tres16) == 4); 132 133 struct uc81xx_ptl16 { 134 uint16_t hrst; 135 uint16_t hred; 136 uint16_t vrst; 137 uint16_t vred; 138 uint8_t flags; 139 } __packed; 140 141 BUILD_ASSERT(sizeof(struct uc81xx_ptl16) == 9); 142 143 #define UC81XX_PTL_FLAG_PT_SCAN BIT(0) 144 145 /* Time constants in ms */ 146 #define UC81XX_RESET_DELAY 10U 147 #define UC81XX_PON_DELAY 100U 148 #define UC81XX_BUSY_DELAY 1U 149 150 #endif /* ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_ */ 151
