1 /* --COPYRIGHT--,BSD
2  * Copyright (c) 2017, Texas Instruments Incorporated
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32 #include <ti/devices/msp432p4xx/driverlib/uart.h>
33 #include <ti/devices/msp432p4xx/driverlib/interrupt.h>
34 #include <ti/devices/msp432p4xx/driverlib/debug.h>
35 #include <ti/devices/msp432p4xx/driverlib/eusci.h>
36 
UART_initModule(uint32_t moduleInstance,const eUSCI_UART_Config * config)37 bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
38 {
39     bool retVal = true;
40 
41     ASSERT(
42             (EUSCI_A_UART_MODE == config->uartMode)
43             || (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE
44                     == config->uartMode)
45             || (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE
46                     == config->uartMode)
47             || (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
48                     == config->uartMode));
49 
50     ASSERT(
51             (EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource)
52             || (EUSCI_A_UART_CLOCKSOURCE_SMCLK
53                     == config->selectClockSource));
54 
55     ASSERT(
56             (EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst)
57             || (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst));
58 
59     ASSERT(
60             (EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits)
61             || (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits));
62 
63     ASSERT(
64             (EUSCI_A_UART_NO_PARITY == config->parity)
65             || (EUSCI_A_UART_ODD_PARITY == config->parity)
66             || (EUSCI_A_UART_EVEN_PARITY == config->parity));
67 
68     /* Disable the USCI Module */
69     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
70 
71     /* Clock source select */
72     EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
73             (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
74                     | config->selectClockSource;
75 
76     /* MSB, LSB select */
77     if (config->msborLsbFirst)
78         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
79     else
80         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
81 
82     /* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
83     if (config->numberofStopBits)
84         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
85     else
86         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
87 
88     /* Parity */
89     switch (config->parity)
90     {
91     case EUSCI_A_UART_NO_PARITY:
92         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
93         break;
94     case EUSCI_A_UART_ODD_PARITY:
95         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
96         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
97         break;
98     case EUSCI_A_UART_EVEN_PARITY:
99         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
100         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
101         break;
102     }
103 
104     /* BaudRate Control Register */
105     EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
106     EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
107             + (config->firstModReg << 4) + config->overSampling);
108 
109     /* Asynchronous mode & 8 bit character select & clear mode */
110     EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
111             (EUSCI_A_CMSIS(moduleInstance)->CTLW0
112                     & ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
113                             | EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
114 
115     return retVal;
116 }
117 
UART_transmitData(uint32_t moduleInstance,uint_fast8_t transmitData)118 void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
119 {
120     /* If interrupts are not used, poll for flags */
121     if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
122         while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
123             ;
124 
125     EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
126 }
127 
UART_receiveData(uint32_t moduleInstance)128 uint8_t UART_receiveData(uint32_t moduleInstance)
129 {
130     /* If interrupts are not used, poll for flags */
131     if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_RXIE_OFS))
132         while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
133             ;
134 
135     return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
136 }
137 
UART_enableModule(uint32_t moduleInstance)138 void UART_enableModule(uint32_t moduleInstance)
139 {
140     /* Reset the UCSWRST bit to enable the USCI Module */
141     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
142 }
143 
UART_disableModule(uint32_t moduleInstance)144 void UART_disableModule(uint32_t moduleInstance)
145 {
146     /* Set the UCSWRST bit to disable the USCI Module */
147     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
148 }
149 
UART_queryStatusFlags(uint32_t moduleInstance,uint_fast8_t mask)150 uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
151 {
152     ASSERT(
153             0x00 != mask
154             && (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR
155                     + EUSCI_A_UART_OVERRUN_ERROR
156                     + EUSCI_A_UART_PARITY_ERROR
157                     + EUSCI_A_UART_BREAK_DETECT
158                     + EUSCI_A_UART_RECEIVE_ERROR
159                     + EUSCI_A_UART_ADDRESS_RECEIVED
160                     + EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
161 
162     return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
163 }
164 
UART_setDormant(uint32_t moduleInstance)165 void UART_setDormant(uint32_t moduleInstance)
166 {
167     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;
168 }
169 
UART_resetDormant(uint32_t moduleInstance)170 void UART_resetDormant(uint32_t moduleInstance)
171 {
172     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
173 }
174 
UART_transmitAddress(uint32_t moduleInstance,uint_fast8_t transmitAddress)175 void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
176 {
177     /* Set UCTXADDR bit */
178     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
179 
180     /* Place next byte to be sent into the transmit buffer */
181     EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
182 }
183 
UART_transmitBreak(uint32_t moduleInstance)184 void UART_transmitBreak(uint32_t moduleInstance)
185 {
186     /* Set UCTXADDR bit */
187     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
188 
189     /* If current mode is automatic baud-rate detection */
190     if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
191             == (EUSCI_A_CMSIS(moduleInstance)->CTLW0
192                     & EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
193         EUSCI_A_CMSIS(moduleInstance)->TXBUF =
194         EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
195     else
196         EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
197 
198     /* If interrupts are not used, poll for flags */
199     if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
200         while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
201             ;
202 }
203 
UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)204 uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
205 {
206     return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
207 }
208 
UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)209 uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
210 {
211     return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
212 }
213 
UART_selectDeglitchTime(uint32_t moduleInstance,uint32_t deglitchTime)214 void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
215 {
216     ASSERT(
217             (EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime)
218             || (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime)
219             || (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
220             || (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
221 
222     EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
223             (EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
224                     | deglitchTime;
225 
226 }
227 
UART_enableInterrupt(uint32_t moduleInstance,uint_fast8_t mask)228 void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
229 {
230     uint_fast8_t locMask;
231 
232     ASSERT(
233             !(mask
234                     & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
235                             | EUSCI_A_UART_TRANSMIT_INTERRUPT
236                             | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
237                             | EUSCI_A_UART_BREAKCHAR_INTERRUPT
238                             | EUSCI_A_UART_STARTBIT_INTERRUPT
239                             | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
240 
241     locMask = (mask
242             & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
243                     | EUSCI_A_UART_STARTBIT_INTERRUPT
244                     | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
245 
246     EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
247 
248     locMask = (mask
249             & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
250                     | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
251     EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
252 }
253 
UART_disableInterrupt(uint32_t moduleInstance,uint_fast8_t mask)254 void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
255 {
256     uint_fast8_t locMask;
257 
258     ASSERT(
259             !(mask
260                     & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
261                             | EUSCI_A_UART_TRANSMIT_INTERRUPT
262                             | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
263                             | EUSCI_A_UART_BREAKCHAR_INTERRUPT
264                             | EUSCI_A_UART_STARTBIT_INTERRUPT
265                             | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
266 
267     locMask = (mask
268             & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
269                     | EUSCI_A_UART_STARTBIT_INTERRUPT
270                     | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
271     EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask;
272 
273     locMask = (mask
274             & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
275                     | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
276     EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;
277 }
278 
UART_getInterruptStatus(uint32_t moduleInstance,uint8_t mask)279 uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
280 {
281     ASSERT(
282             !(mask
283                     & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
284                             | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
285                             | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
286                             | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
287 
288     return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
289 }
290 
UART_getEnabledInterruptStatus(uint32_t moduleInstance)291 uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
292 {
293     uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
294     EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
295     uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
296 
297     if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
298     {
299         intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
300     }
301 
302     if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
303     {
304         intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
305     }
306 
307     intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
308 
309     if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
310     {
311         intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
312     }
313 
314     if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
315     {
316         intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
317     }
318 
319     return intStatus;
320 }
321 
UART_clearInterruptFlag(uint32_t moduleInstance,uint_fast8_t mask)322 void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
323 {
324     ASSERT(
325             !(mask
326                     & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
327                             | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
328                             | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
329                             | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
330 
331     //Clear the UART interrupt source.
332     EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
333 }
334 
UART_registerInterrupt(uint32_t moduleInstance,void (* intHandler)(void))335 void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
336 {
337     switch (moduleInstance)
338     {
339     case EUSCI_A0_BASE:
340         Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
341         Interrupt_enableInterrupt(INT_EUSCIA0);
342         break;
343     case EUSCI_A1_BASE:
344         Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
345         Interrupt_enableInterrupt(INT_EUSCIA1);
346         break;
347 #ifdef EUSCI_A2_BASE
348     case EUSCI_A2_BASE:
349         Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
350         Interrupt_enableInterrupt(INT_EUSCIA2);
351         break;
352 #endif
353 #ifdef EUSCI_A3_BASE
354     case EUSCI_A3_BASE:
355         Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
356         Interrupt_enableInterrupt(INT_EUSCIA3);
357         break;
358 #endif
359     default:
360         ASSERT(false);
361     }
362 }
363 
UART_unregisterInterrupt(uint32_t moduleInstance)364 void UART_unregisterInterrupt(uint32_t moduleInstance)
365 {
366     switch (moduleInstance)
367     {
368     case EUSCI_A0_BASE:
369         Interrupt_disableInterrupt(INT_EUSCIA0);
370         Interrupt_unregisterInterrupt(INT_EUSCIA0);
371         break;
372     case EUSCI_A1_BASE:
373         Interrupt_disableInterrupt(INT_EUSCIA1);
374         Interrupt_unregisterInterrupt(INT_EUSCIA1);
375         break;
376 #ifdef EUSCI_A2_BASE
377     case EUSCI_A2_BASE:
378         Interrupt_disableInterrupt(INT_EUSCIA2);
379         Interrupt_unregisterInterrupt(INT_EUSCIA2);
380         break;
381 #endif
382 #ifdef EUSCI_A3_BASE
383     case EUSCI_A3_BASE:
384         Interrupt_disableInterrupt(INT_EUSCIA3);
385         Interrupt_unregisterInterrupt(INT_EUSCIA3);
386         break;
387 #endif
388     default:
389         ASSERT(false);
390     }
391 }
392