1 /**************************************************************************//** 2 * @file uart_reg.h 3 * @version V1.00 4 * @brief UART register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __UART_REG_H__ 10 #define __UART_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/ 20 /** 21 @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) 22 Memory Mapped Structure for UART Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var UART_T::DAT 32 * Offset: 0x00 UART Receive/Transmit Buffer Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[7:0] |DAT |Data Receive/Transmit Buffer 37 * | | |Write Operation: 38 * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO. 39 * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. 40 * | | |Read Operation: 41 * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 42 * |[8] |PARITY |Parity Bit Receive/Transmit Buffer 43 * | | |Write Operation: 44 * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO. 45 * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. 46 * | | |Read Operation: 47 * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. 48 * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 49 * @var UART_T::INTEN 50 * Offset: 0x04 UART Interrupt Enable Register 51 * --------------------------------------------------------------------------------------------------- 52 * |Bits |Field |Descriptions 53 * | :----: | :----: | :---- | 54 * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit 55 * | | |0 = Receive data available interrupt Disabled. 56 * | | |1 = Receive data available interrupt Enabled. 57 * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit 58 * | | |0 = Transmit holding register empty interrupt Disabled. 59 * | | |1 = Transmit holding register empty interrupt Enabled. 60 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit 61 * | | |0 = Receive Line Status interrupt Disabled. 62 * | | |1 = Receive Line Status interrupt Enabled. 63 * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit 64 * | | |0 = Modem status interrupt Disabled. 65 * | | |1 = Modem status interrupt Enabled. 66 * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit 67 * | | |0 = RX time-out interrupt Disabled. 68 * | | |1 = RX time-out interrupt Enabled. 69 * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit 70 * | | |0 = Buffer error interrupt Disabled. 71 * | | |1 = Buffer error interrupt Enabled. 72 * |[6] |WKIEN |Wake-up Interrupt Enable Bit 73 * | | |0 = Wake-up Interrupt Disabled. 74 * | | |1 = Wake-up Interrupt Enabled. 75 * |[8] |LINIEN |LIN Bus Interrupt Enable Bit 76 * | | |0 = LIN bus interrupt Disabled. 77 * | | |1 = LIN bus interrupt Enabled. 78 * | | |Note: This bit is used for LIN function mode. 79 * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit 80 * | | |0 = Receive Buffer Time-out counter Disabled. 81 * | | |1 = Receive Buffer Time-out counter Enabled. 82 * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit 83 * | | |0 = nRTS auto-flow control Disabled. 84 * | | |1 = nRTS auto-flow control Enabled. 85 * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 86 * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit 87 * | | |0 = nCTS auto-flow control Disabled. 88 * | | |1 = nCTS auto-flow control Enabled. 89 * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 90 * |[14] |TXPDMAEN |TX PDMA Enable Bit 91 * | | |This bit can enable or disable TX PDMA service. 92 * | | |0 = TX PDMA Disabled. 93 * | | |1 = TX PDMA Enabled. 94 * |[15] |RXPDMAEN |RX PDMA Enable Bit 95 * | | |This bit can enable or disable RX PDMA service. 96 * | | |0 = RX PDMA Disabled. 97 * | | |1 = RX PDMA Enabled. 98 * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. 99 * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop. 100 * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 101 * |[16] |SWBEIEN |Single-wire Bit Error Detection Interrupt Enable Bit 102 * | | |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set. 103 * | | |0 = Single-wire Bit Error Detect Interrupt Disabled. 104 * | | |1 = Single-wire Bit Error Detect Interrupt Enabled. 105 * | | |Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. 106 * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit 107 * | | |0 = Auto-baud rate interrupt Disabled. 108 * | | |1 = Auto-baud rate interrupt Enabled. 109 * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit 110 * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 111 * | | |0 = Transmitter empty interrupt Disabled. 112 * | | |1 = Transmitter empty interrupt Enabled. 113 * @var UART_T::FIFO 114 * Offset: 0x08 UART FIFO Control Register 115 * --------------------------------------------------------------------------------------------------- 116 * |Bits |Field |Descriptions 117 * | :----: | :----: | :---- | 118 * |[1] |RXRST |RX Field Software Reset 119 * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. 120 * | | |0 = No effect. 121 * | | |1 = Reset the RX internal state machine and pointers. 122 * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. 123 * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 124 * |[2] |TXRST |TX Field Software Reset 125 * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. 126 * | | |0 = No effect. 127 * | | |1 = Reset the TX internal state machine and pointers. 128 * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. 129 * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 130 * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level 131 * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 132 * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. 133 * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. 134 * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. 135 * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. 136 * | | |Others = Reserved. 137 * |[8] |RXOFF |Receiver Disable Bit 138 * | | |The receiver is disabled or not (set 1 to disable receiver). 139 * | | |0 = Receiver Enabled. 140 * | | |1 = Receiver Disabled. 141 * | | |Note: This bit is used for RS-485 Normal Multi-drop mode. 142 * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 143 * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use 144 * | | |0000 = nRTS Trigger Level is 1 byte. 145 * | | |0001 = nRTS Trigger Level is 4 bytes. 146 * | | |0010 = nRTS Trigger Level is 8 bytes. 147 * | | |0011 = nRTS Trigger Level is 14 bytes. 148 * | | |Others = Reserved. 149 * | | |Note: This field is used for auto nRTS flow control. 150 * @var UART_T::LINE 151 * Offset: 0x0C UART Line Control Register 152 * --------------------------------------------------------------------------------------------------- 153 * |Bits |Field |Descriptions 154 * | :----: | :----: | :---- | 155 * |[1:0] |WLS |Word Length Selection 156 * | | |This field sets UART word length. 157 * | | |00 = 5 bits. 158 * | | |01 = 6 bits. 159 * | | |10 = 7 bits. 160 * | | |11 = 8 bits. 161 * |[2] |NSB |Number of STOP Bit 162 * | | |0 = One STOP bit is generated in the transmitted data. 163 * | | |1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. 164 * | | |When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data. 165 * |[3] |PBE |Parity Bit Enable Bit 166 * | | |0 = Parity bit generated Disabled. 167 * | | |1 = Parity bit generated Enabled. 168 * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. 169 * |[4] |EPE |Even Parity Enable Bit 170 * | | |0 = Odd number of logic 1's is transmitted and checked in each word. 171 * | | |1 = Even number of logic 1's is transmitted and checked in each word. 172 * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. 173 * |[5] |SPE |Stick Parity Enable Bit 174 * | | |0 = Stick parity Disabled. 175 * | | |1 = Stick parity Enabled. 176 * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. 177 * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 178 * |[6] |BCB |Break Control Bit 179 * | | |0 = Break Control Disabled. 180 * | | |1 = Break Control Enabled. 181 * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) 182 * | | |This bit acts only on TX line and has no effect on the transmitter logic. 183 * |[7] |PSS |Parity Bit Source Selection 184 * | | |The parity bit can be selected to be generated and checked automatically or by software. 185 * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. 186 * | | |1 = Parity bit generated and checked by software. 187 * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set. 188 * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically. 189 * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 190 * |[8] |TXDINV |TX Data Inverted 191 * | | |0 = Transmitted data signal inverted Disabled. 192 * | | |1 = Transmitted data signal inverted Enabled. 193 * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. 194 * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 195 * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 196 * |[9] |RXDINV |RX Data Inverted 197 * | | |0 = Received data signal inverted Disabled. 198 * | | |1 = Received data signal inverted Enabled. 199 * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. 200 * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 201 * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 202 * @var UART_T::MODEM 203 * Offset: 0x10 UART Modem Control Register 204 * --------------------------------------------------------------------------------------------------- 205 * |Bits |Field |Descriptions 206 * | :----: | :----: | :---- | 207 * |[1] |RTS |nRTS (Request-to-send) Signal Control 208 * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. 209 * | | |0 = nRTS signal is active. 210 * | | |1 = nRTS signal is inactive. 211 * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. 212 * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 213 * |[9] |RTSACTLV |nRTS Pin Active Level 214 * | | |This bit defines the active level state of nRTS pin output. 215 * | | |0 = nRTS pin output is high level active. 216 * | | |1 = nRTS pin output is low level active. (Default) 217 * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. 218 * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 219 * |[13] |RTSSTS |nRTS Pin Status (Read Only) 220 * | | |This bit mirror from nRTS pin output of voltage logic status. 221 * | | |0 = nRTS pin output is low level voltage logic state. 222 * | | |1 = nRTS pin output is high level voltage logic state. 223 * @var UART_T::MODEMSTS 224 * Offset: 0x14 UART Modem Status Register 225 * --------------------------------------------------------------------------------------------------- 226 * |Bits |Field |Descriptions 227 * | :----: | :----: | :---- | 228 * |[0] |CTSDETF |Detect nCTS State Change Flag 229 * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. 230 * | | |0 = nCTS input has not change state. 231 * | | |1 = nCTS input has change state. 232 * | | |Note: This bit can be cleared by writing 1 to it. 233 * |[4] |CTSSTS |nCTS Pin Status (Read Only) 234 * | | |This bit mirror from nCTS pin input of voltage logic status. 235 * | | |0 = nCTS pin input is low level voltage logic state. 236 * | | |1 = nCTS pin input is high level voltage logic state. 237 * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 238 * |[8] |CTSACTLV |nCTS Pin Active Level 239 * | | |This bit defines the active level state of nCTS pin input. 240 * | | |0 = nCTS pin input is high level active. 241 * | | |1 = nCTS pin input is low level active. (Default) 242 * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. 243 * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 244 * @var UART_T::FIFOSTS 245 * Offset: 0x18 UART FIFO Status Register 246 * --------------------------------------------------------------------------------------------------- 247 * |Bits |Field |Descriptions 248 * | :----: | :----: | :---- | 249 * |[0] |RXOVIF |RX Overflow Error Interrupt Flag 250 * | | |This bit is set when RX FIFO overflow. 251 * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. 252 * | | |0 = RX FIFO is not overflow. 253 * | | |1 = RX FIFO is overflow. 254 * | | |Note: This bit can be cleared by writing 1 to it. 255 * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag 256 * | | |This bit is set to logic 1 when auto-baud rate detect function is finished. 257 * | | |0 = Auto-baud rate detect function is not finished. 258 * | | |1 = Auto-baud rate detect function is finished. 259 * | | |Note: This bit can be cleared by writing 1 to it. 260 * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag 261 * | | |This bit is set to logic 1 in Auto-baud Rate Detect mode when the baud rate counter is overflow. 262 * | | |0 = Auto-baud rate counter is underflow. 263 * | | |1 = Auto-baud rate counter is overflow. 264 * | | |Note: This bit can be cleared by writing 1 to it. 265 * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag 266 * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). 267 * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). 268 * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. 269 * | | |Note2: This bit can be cleared by writing 1 to it. 270 * |[4] |PEF |Parity Error Flag 271 * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. 272 * | | |0 = No parity error is generated. 273 * | | |1 = Parity error is generated. 274 * | | |Note: This bit can be cleared by writing 1 to it. 275 * |[5] |FEF |Framing Error Flag 276 * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). 277 * | | |0 = No framing error is generated. 278 * | | |1 = Framing error is generated. 279 * | | |Note: This bit can be cleared by writing 1 to it. 280 * |[6] |BIF |Break Interrupt Flag 281 * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). 282 * | | |0 = No Break interrupt is generated. 283 * | | |1 = Break interrupt is generated. 284 * | | |Note: This bit can be cleared by writing 1 to it. 285 * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) 286 * | | |This field indicates the RX FIFO Buffer Pointer. 287 * | | |When UART receives one byte from external device, RXPTR increases one. 288 * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. 289 * | | |The Maximum value shown in RXPTR is 15 290 * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. 291 * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 292 * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) 293 * | | |This bit initiate RX FIFO empty or not. 294 * | | |0 = RX FIFO is not empty. 295 * | | |1 = RX FIFO is empty. 296 * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. 297 * | | |It will be cleared when UART receives any new data. 298 * |[15] |RXFULL |Receiver FIFO Full (Read Only) 299 * | | |This bit initiates RX FIFO full or not. 300 * | | |0 = RX FIFO is not full. 301 * | | |1 = RX FIFO is full. 302 * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 303 * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) 304 * | | |This field indicates the TX FIFO Buffer Pointer. 305 * | | |When CPU writes one byte into UART_DAT, TXPTR increases one. 306 * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. 307 * | | |The Maximum value shown in TXPTR is 15. 308 * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. 309 * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 310 * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) 311 * | | |This bit indicates TX FIFO empty or not. 312 * | | |0 = TX FIFO is not empty. 313 * | | |1 = TX FIFO is empty. 314 * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. 315 * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). 316 * |[23] |TXFULL |Transmitter FIFO Full (Read Only) 317 * | | |This bit indicates TX FIFO full or not. 318 * | | |0 = TX FIFO is not full. 319 * | | |1 = TX FIFO is full. 320 * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 321 * |[24] |TXOVIF |TX Overflow Error Interrupt Flag 322 * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. 323 * | | |0 = TX FIFO is not overflow. 324 * | | |1 = TX FIFO is overflow. 325 * | | |Note: This bit can be cleared by writing 1 to it. 326 * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) 327 * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. 328 * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. 329 * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. 330 * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 331 * |[29] |RXIDLE |RX Idle Status (Read Only) 332 * | | |This bit is set by hardware when RX is idle. 333 * | | |0 = RX is busy. 334 * | | |1 = RX is idle. (Default) 335 * |[31] |TXRXACT |TX and RX Active Status (Read Only) 336 * | | |This bit indicates TX and RX are active or inactive. 337 * | | |0 = TX and RX are inactive. 338 * | | |1 = TX and RX are active. (Default) 339 * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. 340 * | | |The UART controller can not transmit or receive data at this moment. 341 * | | |Otherwise this bit is set. 342 * @var UART_T::INTSTS 343 * Offset: 0x1C UART Interrupt Status Register 344 * --------------------------------------------------------------------------------------------------- 345 * |Bits |Field |Descriptions 346 * | :----: | :----: | :---- | 347 * |[0] |RDAIF |Receive Data Available Interrupt Flag 348 * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. 349 * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. 350 * | | |0 = No RDA interrupt flag is generated. 351 * | | |1 = RDA interrupt flag is generated. 352 * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 353 * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag 354 * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. 355 * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. 356 * | | |0 = No THRE interrupt flag is generated. 357 * | | |1 = THRE interrupt flag is generated. 358 * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 359 * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) 360 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). 361 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. 362 * | | |0 = No RLS interrupt flag is generated. 363 * | | |1 = RLS interrupt flag is generated. 364 * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = 1) bit. 365 * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. 366 * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. 367 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 368 * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) 369 * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). 370 * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. 371 * | | |0 = No Modem interrupt flag is generated. 372 * | | |1 = Modem interrupt flag is generated. 373 * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 374 * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) 375 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). 376 * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. 377 * | | |0 = No RX time-out interrupt flag is generated. 378 * | | |1 = RX time-out interrupt flag is generated. 379 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 380 * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) 381 * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). 382 * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. 383 * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. 384 * | | |0 = No buffer error interrupt flag is generated. 385 * | | |1 = Buffer error interrupt flag is generated. 386 * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 387 * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) 388 * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. 389 * | | |0 = No UART wake-up interrupt flag is generated. 390 * | | |1 = UART wake-up interrupt flag is generated. 391 * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 392 * |[7] |LINIF |LIN Bus Interrupt Flag 393 * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0]=1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) 394 * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. 395 * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. 396 * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. 397 * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing 1 to LINIF(UART_INTSTS[7]). 398 * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) 399 * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 400 * | | |0 = No RDA interrupt is generated. 401 * | | |1 = RDA interrupt is generated. 402 * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) 403 * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 404 * | | |0 = No THRE interrupt is generated. 405 * | | |1 = THRE interrupt is generated. 406 * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) 407 * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 408 * | | |0 = No RLS interrupt is generated. 409 * | | |1 = RLS interrupt is generated. 410 * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) 411 * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 412 * | | |0 = No Modem interrupt is generated. 413 * | | |1 = Modem interrupt is generated.. 414 * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) 415 * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 416 * | | |0 = No RX time-out interrupt is generated. 417 * | | |1 = RX time-out interrupt is generated. 418 * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) 419 * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 420 * | | |0 = No buffer error interrupt is generated. 421 * | | |1 = Buffer error interrupt is generated. 422 * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) 423 * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 424 * | | |0 = No UART wake-up interrupt is generated. 425 * | | |1 = UART wake-up interrupt is generated. 426 * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) 427 * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 428 * | | |0 = No LIN Bus interrupt is generated. 429 * | | |1 = The LIN Bus interrupt is generated. 430 * |[16] |SWBEIF |Single-wire Bit Error Detection Interrupt Flag 431 * | | |This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. 432 * | | |0 = No single-wire bit error detection interrupt flag is generated. 433 * | | |1 = Single-wire bit error detection interrupt flag is generated. 434 * | | |Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. 435 * | | |Note 2: This bit can be cleared by writing "1" to it. 436 * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) 437 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). 438 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. 439 * | | |0 = No RLS interrupt flag is generated in PDMA mode. 440 * | | |1 = RLS interrupt flag is generated in PDMA mode. 441 * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = 1) bit. 442 * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. 443 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 444 * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) 445 * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]=1)). 446 * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. 447 * | | |0 = No Modem interrupt flag is generated in PDMA mode. 448 * | | |1 = Modem interrupt flag is generated in PDMA mode. 449 * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 450 * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) 451 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). 452 * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. 453 * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. 454 * | | |1 = RX time-out interrupt flag is generated in PDMA mode. 455 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 456 * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) 457 * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). 458 * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. 459 * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. 460 * | | |0 = No buffer error interrupt flag is generated in PDMA mode. 461 * | | |1 = Buffer error interrupt flag is generated in PDMA mode. 462 * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 463 * |[22] |TXENDIF |Transmitter Empty Interrupt Flag 464 * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). 465 * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. 466 * | | |0 = No transmitter empty interrupt flag is generated. 467 * | | |1 = Transmitter empty interrupt flag is generated. 468 * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 469 * |[24] |SWBEINT |Single-wire Bit Error Detect Interrupt Indicator (Read Only) 470 * | | |This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 471 * | | |0 = No Single-wire Bit Error Detection Interrupt generated. 472 * | | |1 = Single-wire Bit Error Detection Interrupt generated. 473 * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) 474 * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 475 * | | |0 = No RLS interrupt is generated in PDMA mode. 476 * | | |1 = RLS interrupt is generated in PDMA mode. 477 * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) 478 * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 479 * | | |0 = No Modem interrupt is generated in PDMA mode. 480 * | | |1 = Modem interrupt is generated in PDMA mode. 481 * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) 482 * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 483 * | | |0 = No RX time-out interrupt is generated in PDMA mode. 484 * | | |1 = RX time-out interrupt is generated in PDMA mode. 485 * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) 486 * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 487 * | | |0 = No buffer error interrupt is generated in PDMA mode. 488 * | | |1 = Buffer error interrupt is generated in PDMA mode. 489 * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) 490 * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 491 * | | |0 = No Transmitter Empty interrupt is generated. 492 * | | |1 = Transmitter Empty interrupt is generated. 493 * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) 494 * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 495 * | | |0 = No Auto-baud Rate interrupt is generated. 496 * | | |1 = The Auto-baud Rate interrupt is generated. 497 * @var UART_T::TOUT 498 * Offset: 0x20 UART Time-out Register 499 * --------------------------------------------------------------------------------------------------- 500 * |Bits |Field |Descriptions 501 * | :----: | :----: | :---- | 502 * |[7:0] |TOIC |Time-out Interrupt Comparator 503 * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]). 504 * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled. 505 * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]). 506 * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. 507 * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. 508 * |[15:8] |DLY |TX Delay Time Value 509 * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit. 510 * | | |The unit is bit time. 511 * @var UART_T::BAUD 512 * Offset: 0x24 UART Baud Rate Divider Register 513 * --------------------------------------------------------------------------------------------------- 514 * |Bits |Field |Descriptions 515 * | :----: | :----: | :---- | 516 * |[15:0] |BRD |Baud Rate Divider 517 * | | |The field indicates the baud rate divider. 518 * | | |This filed is used in baud rate calculation. 519 * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 520 * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. 521 * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 522 * | | |This bit is baud rate mode selection bit 0 523 * | | |UART provides three baud rate calculation modes. 524 * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. 525 * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 526 * | | |This bit is baud rate mode selection bit 1. 527 * | | |UART provides three baud rate calculation modes. 528 * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. 529 * | | |Note: In IrDA mode must be operated in mode 0. 530 * @var UART_T::IRDA 531 * Offset: 0x28 UART IrDA Control Register 532 * --------------------------------------------------------------------------------------------------- 533 * |Bits |Field |Descriptions 534 * | :----: | :----: | :---- | 535 * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit 536 * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) 537 * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. 538 * |[5] |TXINV |IrDA Inverse Transmitting Output Signal 539 * | | |0 = None inverse transmitting signal. (Default). 540 * | | |1 = Inverse transmitting output signal. 541 * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. 542 * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 543 * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 544 * |[6] |RXINV |IrDA Inverse Receive Input Signal 545 * | | |0 = None inverse receiving input signal. 546 * | | |1 = Inverse receiving input signal. (Default) 547 * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. 548 * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 549 * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 550 * @var UART_T::ALTCTL 551 * Offset: 0x2C UART Alternate Control/Status Register 552 * --------------------------------------------------------------------------------------------------- 553 * |Bits |Field |Descriptions 554 * | :----: | :----: | :---- | 555 * |[3:0] |BRKFL |UART LIN Break Field Length 556 * | | |This field indicates a 4-bit LIN TX break field count. 557 * | | |Note1: This break field length is BRKFL + 1. 558 * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). 559 * |[6] |LINRXEN |LIN RX Enable Bit 560 * | | |0 = LIN RX mode Disabled. 561 * | | |1 = LIN RX mode Enabled. 562 * |[7] |LINTXEN |LIN TX Break Mode Enable Bit 563 * | | |0 = LIN TX Break mode Disabled. 564 * | | |1 = LIN TX Break mode Enabled. 565 * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. 566 * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM) 567 * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. 568 * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. 569 * | | |Note: It cannot be active with RS-485_AAD operation mode. 570 * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD) 571 * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. 572 * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. 573 * | | |Note: It cannot be active with RS-485_NMM operation mode. 574 * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) 575 * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. 576 * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. 577 * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 578 * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit 579 * | | |This bit is used to enable RS-485 Address Detection mode. 580 * | | |0 = Address detection mode Disabled. 581 * | | |1 = Address detection mode Enabled. 582 * | | |Note: This bit is used for RS-485 any operation mode. 583 * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) 584 * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. 585 * | | |0 = No auto-baud rate interrupt flag is generated. 586 * | | |1 = Auto-baud rate interrupt flag is generated. 587 * | | |Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 588 * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit 589 * | | |0 = Auto-baud rate detect function Disabled. 590 * | | |1 = Auto-baud rate detect function Enabled. 591 * | | |Note : This bit is cleared automatically after auto-baud detection is finished. 592 * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length 593 * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. 594 * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. 595 * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. 596 * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. 597 * | | |Note : The calculation of bit number includes the START bit. 598 * |[31:24] |ADDRMV |Address Match Value 599 * | | |This field contains the RS-485 address match values. 600 * | | |Note: This field is used for RS-485 auto address detection mode. 601 * @var UART_T::FUNCSEL 602 * Offset: 0x30 UART Function Select Register 603 * --------------------------------------------------------------------------------------------------- 604 * |Bits |Field |Descriptions 605 * | :----: | :----: | :---- | 606 * |[2:0] |FUNCSEL |Function Select 607 * | | |000 = UART function. 608 * | | |001 = LIN function. 609 * | | |010 = IrDA function. 610 * | | |011 = RS-485 function. 611 * | | |100 = UART Single-wire function. 612 * | | |Others = Reserved. 613 * |[3] |TXRXDIS |TX and RX Disable Bit 614 * | | |Setting this bit can disable TX and RX. 615 * | | |0 = TX and RX Enabled. 616 * | | |1 = TX and RX Disabled. 617 * | | |Note: The TX and RX will not disable immediately when this bit is set. 618 * | | |The TX and RX complete current task before disable TX and RX. 619 * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 620 * |[6] |DGE |Deglitch Enable Bit 621 * | | |0 = Deglitch Disabled. 622 * | | |1 = Deglitch Enabled. 623 * | | |Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). 624 * | | |This bit acts only on RX line and has no effect on the transmitter logic. 625 * @var UART_T::LINCTL 626 * Offset: 0x34 UART LIN Control Register 627 * --------------------------------------------------------------------------------------------------- 628 * |Bits |Field |Descriptions 629 * | :----: | :----: | :---- | 630 * |[0] |SLVEN |LIN Slave Mode Enable Bit 631 * | | |0 = LIN slave mode Disabled. 632 * | | |1 = LIN slave mode Enabled. 633 * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit 634 * | | |0 = LIN slave header detection Disabled. 635 * | | |1 = LIN slave header detection Enabled. 636 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). 637 * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted. 638 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. 639 * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit 640 * | | |0 = LIN automatic resynchronization Disabled. 641 * | | |1 = LIN automatic resynchronization Enabled. 642 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). 643 * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). 644 * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit 645 * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). 646 * | | |1 = UART_BAUD is updated at the next received character 647 * | | |User must set the bit before checksum reception. 648 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). 649 * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) 650 * |[4] |MUTE |LIN Mute Mode Enable Bit 651 * | | |0 = LIN mute mode Disabled. 652 * | | |1 = LIN mute mode Enabled. 653 * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode). 654 * |[8] |SENDH |LIN TX Send Header Enable Bit 655 * | | |The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting HSEL (UART_LINCTL[23:22]). 656 * | | |0 = Send LIN TX header Disabled. 657 * | | |1 = Send LIN TX header Enabled. 658 * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). 659 * | | |Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 660 * |[9] |IDPEN |LIN ID Parity Enable Bit 661 * | | |0 = LIN frame ID parity Disabled. 662 * | | |1 = LIN frame ID parity Enabled. 663 * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. 664 * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10. 665 * |[10] |BRKDETEN |LIN Break Detection Enable Bit 666 * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field. 667 * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. 668 * | | |0 = LIN break detection Disabled . 669 * | | |1 = LIN break detection Enabled. 670 * |[11] |LINRXOFF |LIN Receiver Disable Bit 671 * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (RXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. 672 * | | |0 = LIN receiver Enabled. 673 * | | |1 = LIN receiver Disabled. 674 * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). 675 * |[12] |BITERREN |Bit Error Detect Enable Bit 676 * | | |0 = Bit error detection function Disabled. 677 * | | |1 = Bit error detection function Enabled. 678 * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted. 679 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. 680 * |[19:16] |BRKFL |LIN Break Field Length 681 * | | |This field indicates a 4-bit LIN TX break field count. 682 * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). 683 * | | |Note2: This break field length is BRKFL + 1. 684 * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). 685 * |[21:20] |BSL |LIN Break/Sync Delimiter Length 686 * | | |00 = The LIN break/sync delimiter length is 1-bit time. 687 * | | |01 = The LIN break/sync delimiter length is 2-bit time. 688 * | | |10 = The LIN break/sync delimiter length is 3-bit time. 689 * | | |11 = The LIN break/sync delimiter length is 4-bit time. 690 * | | |Note: This bit used for LIN master to sending header field. 691 * |[23:22] |HSEL |LIN Header Select 692 * | | |00 = The LIN header includes break field. 693 * | | |01 = The LIN header includes break field and sync field. 694 * | | |10 = The LIN header includes break field, sync field and frame ID field. 695 * | | |11 = Reserved. 696 * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). 697 * |[31:24] |PID |LIN PID Bits 698 * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. 699 * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. 700 * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). 701 * | | |Note2: This field can be used for LIN master mode or slave mode. 702 * @var UART_T::LINSTS 703 * Offset: 0x38 UART LIN Status Register 704 * --------------------------------------------------------------------------------------------------- 705 * |Bits |Field |Descriptions 706 * | :----: | :----: | :---- | 707 * |[0] |SLVHDETF |LIN Slave Header Detection Flag 708 * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. 709 * | | |0 = LIN header not detected. 710 * | | |1 = LIN header detected (break + sync + frame ID). 711 * | | |Note1: This bit can be cleared by writing 1 to it. 712 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). 713 * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header (break + sync + frame ID), the SLVHDETF will be set whether the frame ID correct or not. 714 * |[1] |SLVHEF |LIN Slave Header Error Flag 715 * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it 716 * | | |The header errors include break delimiter is too short (less than 0.5 bit time), frame error in sync field or Identifier field, sync field data is not 0x55 in Non-Automatic Resynchronization mode, sync field deviation error with Automatic Resynchronization mode, sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out. 717 * | | |0 = LIN header error not detected. 718 * | | |1 = LIN header error detected. 719 * | | |Note1: This bit can be cleared by writing 1 to it. 720 * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). 721 * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag 722 * | | |This bit is set by hardware when receipted frame ID parity is not correct. 723 * | | |0 = No active. 724 * | | |1 = Receipted frame ID parity is not correct. 725 * | | |Note1: This bit can be cleared by writing 1 to it. 726 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). 727 * |[3] |SLVSYNCF |LIN Slave Sync Field 728 * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. 729 * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. 730 * | | |0 = The current character is not at LIN sync state. 731 * | | |1 = The current character is at LIN sync state. 732 * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). 733 * | | |Note2: This bit can be cleared by writing 1 to it. 734 * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 735 * |[8] |BRKDETF |LIN Break Detection Flag 736 * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 737 * | | |0 = LIN break not detected. 738 * | | |1 = LIN break detected. 739 * | | |Note1: This bit can be cleared by writing 1 to it. 740 * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) = 1). 741 * |[9] |BITEF |Bit Error Detect Status Flag 742 * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 743 * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. 744 * | | |0 = Bit error not detected. 745 * | | |1 = Bit error detected. 746 * | | |Note1: This bit can be cleared by writing 1 to it. 747 * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). 748 * @var UART_T::BRCOMP 749 * Offset: 0x3C UART Baud Rate Compensation Register 750 * --------------------------------------------------------------------------------------------------- 751 * |Bits |Field |Descriptions 752 * | :----: | :----: | :---- | 753 * |[8:0] |BRCOMP |Baud Rate Compensation Patten 754 * | | |These 9-bits are used to define the relative bit is compensated or not. 755 * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOMP[8] is used to define the parity bit. 756 * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease 757 * | | |0 = Positive (increase one module clock) compensation for each compensated bit. 758 * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. 759 * @var UART_T::WKCTL 760 * Offset: 0x40 UART Wake-up Control Register 761 * --------------------------------------------------------------------------------------------------- 762 * |Bits |Field |Descriptions 763 * | :----: | :----: | :---- | 764 * |[0] |WKCTSEN |nCTS Wake-up Enable Bit 765 * | | |0 = nCTS Wake-up system function Disabled. 766 * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external. 767 * | | |nCTS change will wake-up system from Power-down mode. 768 * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit 769 * | | |0 = Incoming data wake-up system function Disabled. 770 * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,. 771 * | | |incoming data will wake-up system from Power-down mode. 772 * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit 773 * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. 774 * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is. 775 * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from 776 * | | |Power-down mode. 777 * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit 778 * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. 779 * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. 780 * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 781 * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit 782 * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. 783 * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode. 784 * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 785 * @var UART_T::WKSTS 786 * Offset: 0x44 UART Wake-up Status Register 787 * --------------------------------------------------------------------------------------------------- 788 * |Bits |Field |Descriptions 789 * | :----: | :----: | :---- | 790 * |[0] |CTSWKF |nCTS Wake-up Flag 791 * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. 792 * | | |0 = Chip stays in power-down state. 793 * | | |1 = Chip wake-up from power-down state by nCTS wake-up. 794 * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to 1. 795 * | | |Note2: This bit can be cleared by writing 1 to it. 796 * |[1] |DATWKF |Incoming Data Wake-up Flag 797 * | | |This bit is set if chip wake-up from power-down state by data wake-up. 798 * | | |0 = Chip stays in power-down state. 799 * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. 800 * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to 1. 801 * | | |Note2: This bit can be cleared by writing 1 to it. 802 * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag 803 * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. 804 * | | |0 = Chip stays in power-down state. 805 * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. 806 * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to 1. 807 * | | |Note2: This bit can be cleared by writing 1 to it. 808 * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag 809 * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). 810 * | | |0 = Chip stays in power-down state. 811 * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. 812 * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to 1. 813 * | | |Note2: This bit can be cleared by writing 1 to it. 814 * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag 815 * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. 816 * | | |0 = Chip stays in power-down state. 817 * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up. 818 * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to 1. 819 * | | |Note2: This bit can be cleared by writing 1 to it. 820 * @var UART_T::DWKCOMP 821 * Offset: 0x48 UART Incoming Data Wake-up Compensation Register 822 * --------------------------------------------------------------------------------------------------- 823 * |Bits |Field |Descriptions 824 * | :----: | :----: | :---- | 825 * |[15:0] |STCOMP |Start Bit Compensation Value 826 * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. 827 * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 828 */ 829 830 831 __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ 832 __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ 833 __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ 834 __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ 835 __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ 836 __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ 837 __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ 838 __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ 839 __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ 840 __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ 841 __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ 842 __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ 843 __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ 844 __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ 845 __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ 846 __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ 847 __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ 848 __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ 849 __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ 850 851 852 } UART_T; 853 854 /** 855 @addtogroup UART_CONST UART Bit Field Definition 856 Constant Definitions for UART Controller 857 @{ 858 */ 859 860 #define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ 861 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ 862 863 #define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ 864 #define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ 865 866 #define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ 867 #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ 868 869 #define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ 870 #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ 871 872 #define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ 873 #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ 874 875 #define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ 876 #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ 877 878 #define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ 879 #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ 880 881 #define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ 882 #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ 883 884 #define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ 885 #define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ 886 887 #define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ 888 #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ 889 890 #define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ 891 #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ 892 893 #define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ 894 #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ 895 896 #define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ 897 #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ 898 899 #define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ 900 #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ 901 902 #define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ 903 #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ 904 905 #define UART_INTEN_SWBEIEN_Pos (16) /*!< UART_T::INTEN: SWBEIEN Position */ 906 #define UART_INTEN_SWBEIEN_Msk (0x1ul << UART_INTEN_SWBEIEN_Pos) /*!< UART_T::INTEN: SWBEIEN Mask */ 907 908 #define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ 909 #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ 910 911 #define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ 912 #define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ 913 914 #define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ 915 #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ 916 917 #define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ 918 #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ 919 920 #define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ 921 #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ 922 923 #define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ 924 #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ 925 926 #define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ 927 #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ 928 929 #define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ 930 #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ 931 932 #define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ 933 #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ 934 935 #define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ 936 #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ 937 938 #define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ 939 #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ 940 941 #define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ 942 #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ 943 944 #define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ 945 #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ 946 947 #define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ 948 #define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ 949 950 #define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ 951 #define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ 952 953 #define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ 954 #define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ 955 956 #define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ 957 #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ 958 959 #define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ 960 #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ 961 962 #define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ 963 #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ 964 965 #define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ 966 #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ 967 968 #define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ 969 #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ 970 971 #define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ 972 #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ 973 974 #define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ 975 #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ 976 977 #define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ 978 #define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ 979 980 #define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ 981 #define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ 982 983 #define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ 984 #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ 985 986 #define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ 987 #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ 988 989 #define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ 990 #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ 991 992 #define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ 993 #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ 994 995 #define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ 996 #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ 997 998 #define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ 999 #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ 1000 1001 #define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ 1002 #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ 1003 1004 #define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ 1005 #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ 1006 1007 #define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ 1008 #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ 1009 1010 #define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ 1011 #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ 1012 1013 #define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ 1014 #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ 1015 1016 #define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ 1017 #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ 1018 1019 #define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ 1020 #define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ 1021 1022 #define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ 1023 #define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ 1024 1025 #define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ 1026 #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ 1027 1028 #define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ 1029 #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ 1030 1031 #define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ 1032 #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ 1033 1034 #define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ 1035 #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ 1036 1037 #define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ 1038 #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ 1039 1040 #define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ 1041 #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ 1042 1043 #define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ 1044 #define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ 1045 1046 #define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ 1047 #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ 1048 1049 #define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ 1050 #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ 1051 1052 #define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ 1053 #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ 1054 1055 #define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ 1056 #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ 1057 1058 #define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ 1059 #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ 1060 1061 #define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ 1062 #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ 1063 1064 #define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ 1065 #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ 1066 1067 #define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ 1068 #define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ 1069 1070 #define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ 1071 #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ 1072 1073 #define UART_INTSTS_SWBEIF_Pos (16) /*!< UART_T::INTSTS: SWBEIF Position */ 1074 #define UART_INTSTS_SWBEIF_Msk (0x1ul << UART_INTSTS_SWBEIF_Pos) /*!< UART_T::INTSTS: SWBEIF Mask */ 1075 1076 #define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ 1077 #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ 1078 1079 #define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ 1080 #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ 1081 1082 #define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ 1083 #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ 1084 1085 #define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ 1086 #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ 1087 1088 #define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ 1089 #define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ 1090 1091 #define UART_INTSTS_SWBEINT_Pos (24) /*!< UART_T::INTSTS: SWBEINT Position */ 1092 #define UART_INTSTS_SWBEINT_Msk (0x1ul << UART_INTSTS_SWBEINT_Pos) /*!< UART_T::INTSTS: SWBEINT Mask */ 1093 1094 #define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ 1095 #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ 1096 1097 #define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ 1098 #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ 1099 1100 #define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ 1101 #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ 1102 1103 #define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ 1104 #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ 1105 1106 #define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ 1107 #define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ 1108 1109 #define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ 1110 #define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ 1111 1112 #define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ 1113 #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ 1114 1115 #define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ 1116 #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ 1117 1118 #define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ 1119 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ 1120 1121 #define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ 1122 #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ 1123 1124 #define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ 1125 #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ 1126 1127 #define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ 1128 #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ 1129 1130 #define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ 1131 #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ 1132 1133 #define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ 1134 #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ 1135 1136 #define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ 1137 #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ 1138 1139 #define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ 1140 #define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ 1141 1142 #define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ 1143 #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ 1144 1145 #define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ 1146 #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ 1147 1148 #define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ 1149 #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ 1150 1151 #define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ 1152 #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ 1153 1154 #define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ 1155 #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ 1156 1157 #define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ 1158 #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ 1159 1160 #define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ 1161 #define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ 1162 1163 #define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ 1164 #define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ 1165 1166 #define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ 1167 #define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ 1168 1169 #define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ 1170 #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ 1171 1172 #define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ 1173 #define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ 1174 1175 #define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ 1176 #define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ 1177 1178 #define UART_FUNCSEL_DGE_Pos (6) /*!< UART_T::FUNCSEL: DGE Position */ 1179 #define UART_FUNCSEL_DGE_Msk (0x1ul << UART_FUNCSEL_DGE_Pos) /*!< UART_T::FUNCSEL: DGE Mask */ 1180 1181 #define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ 1182 #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ 1183 1184 #define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ 1185 #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ 1186 1187 #define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ 1188 #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ 1189 1190 #define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ 1191 #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ 1192 1193 #define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ 1194 #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ 1195 1196 #define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ 1197 #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ 1198 1199 #define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ 1200 #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ 1201 1202 #define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ 1203 #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ 1204 1205 #define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ 1206 #define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ 1207 1208 #define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ 1209 #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ 1210 1211 #define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ 1212 #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ 1213 1214 #define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ 1215 #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ 1216 1217 #define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ 1218 #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ 1219 1220 #define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ 1221 #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ 1222 1223 #define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ 1224 #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ 1225 1226 #define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ 1227 #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ 1228 1229 #define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ 1230 #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ 1231 1232 #define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ 1233 #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ 1234 1235 #define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ 1236 #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ 1237 1238 #define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ 1239 #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ 1240 1241 #define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ 1242 #define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ 1243 1244 #define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ 1245 #define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ 1246 1247 #define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ 1248 #define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ 1249 1250 #define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ 1251 #define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ 1252 1253 #define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ 1254 #define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ 1255 1256 #define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ 1257 #define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ 1258 1259 #define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ 1260 #define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ 1261 1262 #define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ 1263 #define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ 1264 1265 #define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ 1266 #define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ 1267 1268 #define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ 1269 #define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ 1270 1271 #define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ 1272 #define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ 1273 1274 #define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ 1275 #define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ 1276 1277 #define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ 1278 #define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ 1279 1280 /**@}*/ /* UART_CONST */ 1281 /**@}*/ /* end of UART register group */ 1282 /**@}*/ /* end of REGISTER group */ 1283 1284 #endif /* __UART_REG_H__ */ 1285
