1 /*! 2 \file gd32f4xx_usart.h 3 \brief definitions for the USART 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F4XX_USART_H 39 #define GD32F4XX_USART_H 40 41 #include "gd32f4xx.h" 42 43 /* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */ 44 #define USART1 USART_BASE /*!< USART1 base address */ 45 #define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ 46 #define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ 47 #define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ 48 #define UART6 (USART_BASE+0x00003400U) /*!< UART6 base address */ 49 #define UART7 (USART_BASE+0x00003800U) /*!< UART7 base address */ 50 #define USART0 (USART_BASE+0x0000CC00U) /*!< USART0 base address */ 51 #define USART5 (USART_BASE+0x0000D000U) /*!< USART5 base address */ 52 53 /* registers definitions */ 54 #define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ 55 #define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ 56 #define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ 57 #define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ 58 #define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ 59 #define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ 60 #define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ 61 #define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ 62 #define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ 63 #define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ 64 #define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */ 65 66 /* bits definitions */ 67 /* USARTx_STAT0 */ 68 #define USART_STAT0_PERR BIT(0) /*!< parity error flag */ 69 #define USART_STAT0_FERR BIT(1) /*!< frame error flag */ 70 #define USART_STAT0_NERR BIT(2) /*!< noise error flag */ 71 #define USART_STAT0_ORERR BIT(3) /*!< overrun error */ 72 #define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ 73 #define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ 74 #define USART_STAT0_TC BIT(6) /*!< transmission complete */ 75 #define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ 76 #define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ 77 #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ 78 79 /* USARTx_DATA */ 80 #define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ 81 82 /* USARTx_BAUD */ 83 #define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ 84 #define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ 85 86 /* USARTx_CTL0 */ 87 #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ 88 #define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ 89 #define USART_CTL0_REN BIT(2) /*!< receiver enable */ 90 #define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ 91 #define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ 92 #define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ 93 #define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ 94 #define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ 95 #define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ 96 #define USART_CTL0_PM BIT(9) /*!< parity mode */ 97 #define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ 98 #define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ 99 #define USART_CTL0_WL BIT(12) /*!< word length */ 100 #define USART_CTL0_UEN BIT(13) /*!< USART enable */ 101 #define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ 102 103 /* USARTx_CTL1 */ 104 #define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ 105 #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ 106 #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ 107 #define USART_CTL1_CLEN BIT(8) /*!< CK length */ 108 #define USART_CTL1_CPH BIT(9) /*!< CK phase */ 109 #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ 110 #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ 111 #define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ 112 #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ 113 114 /* USARTx_CTL2 */ 115 #define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ 116 #define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ 117 #define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ 118 #define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ 119 #define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ 120 #define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ 121 #define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ 122 #define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ 123 #define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ 124 #define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ 125 #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ 126 #define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ 127 128 /* USARTx_GP */ 129 #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ 130 #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ 131 132 /* USARTx_CTL3 */ 133 #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ 134 #define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ 135 #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ 136 #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ 137 #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ 138 #define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ 139 #define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ 140 #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ 141 142 /* USARTx_RT */ 143 #define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ 144 #define USART_RT_BL BITS(24,31) /*!< block length */ 145 146 /* USARTx_STAT1 */ 147 #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ 148 #define USART_STAT1_EBF BIT(12) /*!< end of block flag */ 149 #define USART_STAT1_BSY BIT(16) /*!< busy flag */ 150 151 /* USARTx_CHC */ 152 #define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ 153 #define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ 154 #define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ 155 #define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ 156 157 /* constants definitions */ 158 /* define the USART bit position and its register index offset */ 159 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 160 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) 161 #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 162 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 163 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 164 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) 165 #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) 166 167 /* register offset */ 168 #define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ 169 #define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ 170 #define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ 171 #define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ 172 #define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ 173 #define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ 174 #define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ 175 176 /* USART flags */ 177 typedef enum { 178 /* flags in STAT0 register */ 179 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ 180 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ 181 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 182 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ 183 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ 184 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ 185 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ 186 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ 187 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ 188 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ 189 /* flags in STAT1 register */ 190 USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ 191 USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ 192 USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ 193 /* flags in CHC register */ 194 USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ 195 } usart_flag_enum; 196 197 /* USART interrupt flags */ 198 typedef enum { 199 /* interrupt flags in CTL0 register */ 200 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 201 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 202 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 203 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 204 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 205 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 206 /* interrupt flags in CTL1 register */ 207 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ 208 /* interrupt flags in CTL2 register */ 209 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ 210 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ 211 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 212 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 213 /* interrupt flags in CTL3 register */ 214 USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ 215 USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ 216 } usart_interrupt_flag_enum; 217 218 /* USART interrupt flags */ 219 typedef enum { 220 /* interrupt in CTL0 register */ 221 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 222 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 223 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 224 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 225 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 226 /* interrupt in CTL1 register */ 227 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ 228 /* interrupt in CTL2 register */ 229 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ 230 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 231 /* interrupt in CTL3 register */ 232 USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ 233 USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ 234 } usart_interrupt_enum; 235 236 /* USART invert configure */ 237 typedef enum { 238 /* data bit level inversion */ 239 USART_DINV_ENABLE, /*!< data bit level inversion */ 240 USART_DINV_DISABLE, /*!< data bit level not inversion */ 241 /* TX pin level inversion */ 242 USART_TXPIN_ENABLE, /*!< TX pin level inversion */ 243 USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ 244 /* RX pin level inversion */ 245 USART_RXPIN_ENABLE, /*!< RX pin level inversion */ 246 USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ 247 } usart_invert_enum; 248 249 /* USART receiver configure */ 250 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 251 #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ 252 #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ 253 254 /* USART transmitter configure */ 255 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) 256 #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ 257 #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ 258 259 /* USART parity bits definitions */ 260 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) 261 #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ 262 #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ 263 #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ 264 265 /* USART wakeup method in mute mode */ 266 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 267 #define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */ 268 #define USART_WM_ADDR CTL0_WM(1) /*!< address mask */ 269 270 /* USART word length definitions */ 271 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) 272 #define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ 273 #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ 274 275 /* USART oversampling mode definitions */ 276 #define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 277 #define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */ 278 #define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */ 279 280 /* USART stop bits definitions */ 281 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 282 #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ 283 #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ 284 #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ 285 #define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ 286 287 /* USART LIN break frame length */ 288 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) 289 #define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ 290 #define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ 291 292 /* USART CK length */ 293 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 294 #define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ 295 #define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ 296 297 /* USART clock phase */ 298 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 299 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ 300 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ 301 302 /* USART clock polarity */ 303 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) 304 #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ 305 #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ 306 307 /* USART DMA request for receive configure */ 308 #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) 309 #define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ 310 #define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ 311 312 /* USART DMA request for transmission configure */ 313 #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) 314 #define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ 315 #define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ 316 317 /* USART RTS configure */ 318 #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 319 #define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ 320 #define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ 321 322 /* USART CTS configure */ 323 #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 324 #define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ 325 #define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ 326 327 /* USART one sample bit method configure */ 328 #define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 329 #define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ 330 #define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ 331 332 /* USART IrDA low-power enable */ 333 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 334 #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ 335 #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ 336 337 /* USART data is transmitted/received with the LSB/MSB first */ 338 #define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 339 #define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ 340 #define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ 341 342 /* break frame coherence mode */ 343 #define CHC_BCM(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 344 #define USART_BCM_NONE CHC_BCM(0) /*!< no parity error is detected */ 345 #define USART_BCM_EN CHC_BCM(1) /*!< parity error is detected */ 346 347 /* USART parity check coherence mode */ 348 #define CHC_PCM(regval) (BIT(1) & ((uint32_t)(regval) << 1)) 349 #define USART_PCM_NONE CHC_PCM(0) /*!< not check parity */ 350 #define USART_PCM_EN CHC_PCM(1) /*!< check the parity */ 351 352 /* USART hardware flow control coherence mode */ 353 #define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) 354 #define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ 355 #define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ 356 357 /* function declarations */ 358 /* initialization functions */ 359 /* reset USART */ 360 void usart_deinit(uint32_t usart_periph); 361 /* configure usart baud rate value */ 362 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); 363 /* configure usart parity function */ 364 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); 365 /* configure usart word length */ 366 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); 367 /* configure usart stop bit length */ 368 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); 369 /* enable usart */ 370 void usart_enable(uint32_t usart_periph); 371 /* disable usart */ 372 void usart_disable(uint32_t usart_periph); 373 /* configure USART transmitter */ 374 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); 375 /* configure USART receiver */ 376 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); 377 378 /* USART normal mode communication */ 379 /* data is transmitted/received with the LSB/MSB first */ 380 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); 381 /* configure USART inverted */ 382 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); 383 /* configure the USART oversample mode */ 384 void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); 385 /* configure sample bit method */ 386 void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm); 387 /* enable receiver timeout */ 388 void usart_receiver_timeout_enable(uint32_t usart_periph); 389 /* disable receiver timeout */ 390 void usart_receiver_timeout_disable(uint32_t usart_periph); 391 /* configure receiver timeout threshold */ 392 void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); 393 /* USART transmit data function */ 394 void usart_data_transmit(uint32_t usart_periph, uint32_t data); 395 /* USART receive data function */ 396 uint16_t usart_data_receive(uint32_t usart_periph); 397 398 /* multi-processor communication */ 399 /* configure address of the USART */ 400 void usart_address_config(uint32_t usart_periph, uint8_t addr); 401 /* enable mute mode */ 402 void usart_mute_mode_enable(uint32_t usart_periph); 403 /* disable mute mode */ 404 void usart_mute_mode_disable(uint32_t usart_periph); 405 /* configure wakeup method in mute mode */ 406 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod); 407 408 /* LIN mode communication */ 409 /* enable LIN mode */ 410 void usart_lin_mode_enable(uint32_t usart_periph); 411 /* disable LIN mode */ 412 void usart_lin_mode_disable(uint32_t usart_periph); 413 /* LIN break detection length */ 414 void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); 415 /* send break frame */ 416 void usart_send_break(uint32_t usart_periph); 417 418 /* half-duplex communication */ 419 /* enable half-duplex mode */ 420 void usart_halfduplex_enable(uint32_t usart_periph); 421 /* disable half-duplex mode */ 422 void usart_halfduplex_disable(uint32_t usart_periph); 423 424 /* synchronous communication */ 425 /* enable CK pin in synchronous mode */ 426 void usart_synchronous_clock_enable(uint32_t usart_periph); 427 /* disable CK pin in synchronous mode */ 428 void usart_synchronous_clock_disable(uint32_t usart_periph); 429 /* configure usart synchronous mode parameters */ 430 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); 431 432 /* smartcard communication */ 433 /* configure guard time value in smartcard mode */ 434 void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); 435 /* enable smartcard mode */ 436 void usart_smartcard_mode_enable(uint32_t usart_periph); 437 /* disable smartcard mode */ 438 void usart_smartcard_mode_disable(uint32_t usart_periph); 439 /* enable NACK in smartcard mode */ 440 void usart_smartcard_mode_nack_enable(uint32_t usart_periph); 441 /* disable NACK in smartcard mode */ 442 void usart_smartcard_mode_nack_disable(uint32_t usart_periph); 443 /* configure smartcard auto-retry number */ 444 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); 445 /* configure block length */ 446 void usart_block_length_config(uint32_t usart_periph, uint32_t bl); 447 448 /* IrDA communication */ 449 /* enable IrDA mode */ 450 void usart_irda_mode_enable(uint32_t usart_periph); 451 /* disable IrDA mode */ 452 void usart_irda_mode_disable(uint32_t usart_periph); 453 /* configure the peripheral clock prescaler */ 454 void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); 455 /* configure IrDA low-power */ 456 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); 457 458 /* hardware flow communication */ 459 /* configure hardware flow control RTS */ 460 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); 461 /* configure hardware flow control CTS */ 462 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); 463 464 /* coherence control */ 465 /* configure break frame coherence mode */ 466 void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm); 467 /* configure parity check coherence mode */ 468 void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm); 469 /* configure hardware flow control coherence mode */ 470 void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); 471 472 /* DMA communication */ 473 /* configure USART DMA for reception */ 474 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); 475 /* configure USART DMA for transmission */ 476 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); 477 478 /* flag & interrupt functions */ 479 /* get flag in STAT0/STAT1 register */ 480 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); 481 /* clear flag in STAT0/STAT1 register */ 482 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); 483 /* enable USART interrupt */ 484 void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); 485 /* disable USART interrupt */ 486 void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); 487 /* get USART interrupt and flag status */ 488 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 489 /* clear interrupt flag in STAT0/STAT1 register */ 490 void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 491 492 #endif /* GD32F4XX_USART_H */ 493
