1 /*
2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c
21 * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c
22 */
23
24 #include "tfm_hal_device_header.h"
25 #if defined(TEST_NS_FPU) || defined(TEST_S_FPU)
26 #include "test_interrupt.h"
27 #endif
28
29 /*----------------------------------------------------------------------------
30 External References
31 *----------------------------------------------------------------------------*/
32 extern uint32_t __INITIAL_SP;
33 extern uint32_t __STACK_LIMIT;
34 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
35 extern uint64_t __STACK_SEAL;
36 #endif
37
38 extern __NO_RETURN void __PROGRAM_START(void);
39
40 /*----------------------------------------------------------------------------
41 Internal References
42 *----------------------------------------------------------------------------*/
43 __NO_RETURN void Reset_Handler (void);
44
45 /*----------------------------------------------------------------------------
46 Exception / Interrupt Handler
47 *----------------------------------------------------------------------------*/
48 #define DEFAULT_IRQ_HANDLER(handler_name) \
49 __NO_RETURN void __WEAK handler_name(void); \
50 void handler_name(void) { \
51 while(1); \
52 }
53
54 DEFAULT_IRQ_HANDLER(NMI_Handler)
55 DEFAULT_IRQ_HANDLER(HardFault_Handler)
56 DEFAULT_IRQ_HANDLER(MemManage_Handler)
57 DEFAULT_IRQ_HANDLER(BusFault_Handler)
58 DEFAULT_IRQ_HANDLER(UsageFault_Handler)
59 DEFAULT_IRQ_HANDLER(SecureFault_Handler)
60 DEFAULT_IRQ_HANDLER(SVC_Handler)
61 DEFAULT_IRQ_HANDLER(DebugMon_Handler)
62 DEFAULT_IRQ_HANDLER(PendSV_Handler)
63 DEFAULT_IRQ_HANDLER(SysTick_Handler)
64
65 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
66 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
67 DEFAULT_IRQ_HANDLER(S32K_TIMER_Handler)
68 DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
69 DEFAULT_IRQ_HANDLER(TIMER1_Handler)
70 DEFAULT_IRQ_HANDLER(DUALTIMER_Handler)
71 DEFAULT_IRQ_HANDLER(MHU0_Handler)
72 DEFAULT_IRQ_HANDLER(MHU1_Handler)
73 DEFAULT_IRQ_HANDLER(MPC_Handler)
74 DEFAULT_IRQ_HANDLER(PPC_Handler)
75 DEFAULT_IRQ_HANDLER(MSC_Handler)
76 DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
77 DEFAULT_IRQ_HANDLER(INVALID_INSTR_CACHE_Handler)
78 DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
79 DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
80 DEFAULT_IRQ_HANDLER(CPU1_PPU_Handler)
81 DEFAULT_IRQ_HANDLER(CPU0_DBG_PPU_Handler)
82 DEFAULT_IRQ_HANDLER(CPU1_DBG_PPU_Handler)
83 DEFAULT_IRQ_HANDLER(CRYPT_PPU_Handler)
84 DEFAULT_IRQ_HANDLER(RAM0_PPU_Handler)
85 DEFAULT_IRQ_HANDLER(RAM1_PPU_Handler)
86 DEFAULT_IRQ_HANDLER(RAM2_PPU_Handler)
87 DEFAULT_IRQ_HANDLER(RAM3_PPU_Handler)
88 DEFAULT_IRQ_HANDLER(DBG_PPU_Handler)
89 DEFAULT_IRQ_HANDLER(CPU0_CTI_Handler)
90 DEFAULT_IRQ_HANDLER(CPU1_CTI_Handler)
91
92 DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
93 DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
94 DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
95 DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
96 DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
97 DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
98 DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
99 DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
100 DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
101 DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
102 #if defined(TEST_NS_FPU) || defined(TEST_S_FPU)
103 #define UART0_Combined_Handler TFM_FPU_S_TEST_Handler
104 #else
105 DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
106 #endif
107 DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
108 DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
109 DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
110 DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
111 DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
112 DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
113 DEFAULT_IRQ_HANDLER(I2S_Handler)
114 DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
115 DEFAULT_IRQ_HANDLER(SPI0_Handler)
116 DEFAULT_IRQ_HANDLER(SPI1_Handler)
117 DEFAULT_IRQ_HANDLER(SPI2_Handler)
118 DEFAULT_IRQ_HANDLER(SPI3_Handler)
119 DEFAULT_IRQ_HANDLER(SPI4_Handler)
120 DEFAULT_IRQ_HANDLER(DMA0_ERROR_Handler)
121 DEFAULT_IRQ_HANDLER(DMA0_TC_Handler)
122 DEFAULT_IRQ_HANDLER(DMA0_Handler)
123 DEFAULT_IRQ_HANDLER(DMA1_ERROR_Handler)
124 DEFAULT_IRQ_HANDLER(DMA1_TC_Handler)
125 DEFAULT_IRQ_HANDLER(DMA1_Handler)
126 DEFAULT_IRQ_HANDLER(DMA2_ERROR_Handler)
127 DEFAULT_IRQ_HANDLER(DMA2_TC_Handler)
128 DEFAULT_IRQ_HANDLER(DMA2_Handler)
129 DEFAULT_IRQ_HANDLER(DMA3_ERROR_Handler)
130 DEFAULT_IRQ_HANDLER(DMA3_TC_Handler)
131 DEFAULT_IRQ_HANDLER(DMA3_Handler)
132 DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
133 DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
134 DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
135 DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
136 DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
137 DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
138 DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
139 DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
140 DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
141 DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
142 DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
143 DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
144 DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
145 DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
146 DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
147 DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
148 DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
149 DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
150 DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
151 DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
152 DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
153 DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
154 DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
155 DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
156 DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
157 DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
158 DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
159 DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
160
161
162 /*----------------------------------------------------------------------------
163 Exception / Interrupt Vector table
164 *----------------------------------------------------------------------------*/
165
166 #if defined ( __GNUC__ )
167 #pragma GCC diagnostic push
168 #pragma GCC diagnostic ignored "-Wpedantic"
169 #endif
170
171 extern const VECTOR_TABLE_Type __VECTOR_TABLE[];
172 const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
173 (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
174 Reset_Handler, /* Reset Handler */
175 NMI_Handler, /* -14: NMI Handler */
176 HardFault_Handler, /* -13: Hard Fault Handler */
177 MemManage_Handler, /* -12: MPU Fault Handler */
178 BusFault_Handler, /* -11: Bus Fault Handler */
179 UsageFault_Handler, /* -10: Usage Fault Handler */
180 SecureFault_Handler, /* -9: Secure Fault Handler */
181 0, /* -8: Reserved */
182 0, /* -7: Reserved */
183 0, /* -6: Reserved */
184 SVC_Handler, /* -5: SVCall Handler */
185 DebugMon_Handler, /* -4: Debug Monitor Handler */
186 0, /* -3: Reserved */
187 PendSV_Handler, /* -2: PendSV Handler */
188 SysTick_Handler, /* -1: SysTick Handler */
189
190 NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */
191 NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Interrupt Handler */
192 S32K_TIMER_Handler, /* 2: S32K Timer Handler */
193 TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
194 TIMER1_Handler, /* 4: TIMER 1 Handler */
195 DUALTIMER_Handler, /* 5: Dual Timer Handler */
196 MHU0_Handler, /* 6: Message Handling Unit 0 */
197 MHU1_Handler, /* 7: Message Handling Unit 1 */
198 0, /* 8: Reserved */
199 MPC_Handler, /* 9: MPC Combined (Secure) Handler */
200 PPC_Handler, /* 10: PPC Combined (Secure) Handler */
201 MSC_Handler, /* 11: MSC Combined (Secure) Handler */
202 BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
203 INVALID_INSTR_CACHE_Handler, /* 13: CPU Instruction Cache Invalidation Handler */
204 0, /* 14: Reserved */
205 SYS_PPU_Handler, /* 15: SYS PPU Handler */
206 CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
207 CPU1_PPU_Handler, /* 17: CPU1 PPU Handler */
208 CPU0_DBG_PPU_Handler, /* 18: CPU0 DBG PPU_Handler */
209 CPU1_DBG_PPU_Handler, /* 19: CPU1 DBG PPU_Handler */
210 CRYPT_PPU_Handler, /* 20: CRYPT PPU Handler */
211 0, /* 21: Reserved */
212 RAM0_PPU_Handler, /* 22: RAM0 PPU Handler */
213 RAM1_PPU_Handler, /* 23: RAM1 PPU Handler */
214 RAM2_PPU_Handler, /* 24: RAM2 PPU Handler */
215 RAM3_PPU_Handler, /* 25: RAM3 PPU Handler */
216 DBG_PPU_Handler, /* 26: DBG PPU Handler */
217 0, /* 27: Reserved */
218 CPU0_CTI_Handler, /* 28: CPU0 CTI Handler */
219 CPU1_CTI_Handler, /* 29: CPU1 CTI Handler */
220 0, /* 30: Reserved */
221 0, /* 31: Reserved */
222
223 /* External interrupts */
224 UARTRX0_Handler, /* 32: UART 0 RX Handler */
225 UARTTX0_Handler, /* 33: UART 0 TX Handler */
226 UARTRX1_Handler, /* 34: UART 1 RX Handler */
227 UARTTX1_Handler, /* 35: UART 1 TX Handler */
228 UARTRX2_Handler, /* 36: UART 2 RX Handler */
229 UARTTX2_Handler, /* 37: UART 2 TX Handler */
230 UARTRX3_Handler, /* 38: UART 3 RX Handler */
231 UARTTX3_Handler, /* 39: UART 3 TX Handler */
232 UARTRX4_Handler, /* 40: UART 4 RX Handler */
233 UARTTX4_Handler, /* 41: UART 4 TX Handler */
234 UART0_Combined_Handler, /* 42: UART 0 Combined Handler */
235 UART1_Combined_Handler, /* 43: UART 1 Combined Handler */
236 UART2_Combined_Handler, /* 44: UART 2 Combined Handler */
237 UART3_Combined_Handler, /* 45: UART 3 Combined Handler */
238 UART4_Combined_Handler, /* 46: UART 4 Combined Handler */
239 UARTOVF_Handler, /* 47: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
240 ETHERNET_Handler, /* 48: Ethernet Handler */
241 I2S_Handler, /* 49: Audio I2S Handler */
242 TOUCH_SCREEN_Handler, /* 50: Touch Screen Handler */
243 SPI0_Handler, /* 51: SPI 0 Handler */
244 SPI1_Handler, /* 52: SPI 1 Handler */
245 SPI2_Handler, /* 53: SPI 2 Handler */
246 SPI3_Handler, /* 54: SPI 3 Handler */
247 SPI4_Handler, /* 55: SPI 4 Handler */
248 DMA0_ERROR_Handler, /* 56: DMA 0 Error Handler */
249 DMA0_TC_Handler, /* 57: DMA 0 Terminal Count Handler */
250 DMA0_Handler, /* 58: DMA 0 Combined Handler */
251 DMA1_ERROR_Handler, /* 59: DMA 1 Error Handler */
252 DMA1_TC_Handler, /* 60: DMA 1 Terminal Count Handler */
253 DMA1_Handler, /* 61: DMA 1 Combined Handler */
254 DMA2_ERROR_Handler, /* 62: DMA 2 Error Handler */
255 DMA2_TC_Handler, /* 63: DMA 2 Terminal Count Handler */
256 DMA2_Handler, /* 64: DMA 2 Combined Handler */
257 DMA3_ERROR_Handler, /* 65: DMA 3 Error Handler */
258 DMA3_TC_Handler, /* 66: DMA 3 Terminal Count Handler */
259 DMA3_Handler, /* 67: DMA 3 Combined Handler */
260 GPIO0_Combined_Handler, /* 68: GPIO 0 Combined Handler */
261 GPIO1_Combined_Handler, /* 69: GPIO 1 Combined Handler */
262 GPIO2_Combined_Handler, /* 70: GPIO 2 Combined Handler */
263 GPIO3_Combined_Handler, /* 71: GPIO 3 Combined Handler */
264 GPIO0_0_Handler, /* 72: GPIO0 Pin 0 Handler */
265 GPIO0_1_Handler, /* 73: GPIO0 Pin 1 Handler */
266 GPIO0_2_Handler, /* 74: GPIO0 Pin 2 Handler */
267 GPIO0_3_Handler, /* 75: GPIO0 Pin 3 Handler */
268 GPIO0_4_Handler, /* 76: GPIO0 Pin 4 Handler */
269 GPIO0_5_Handler, /* 77: GPIO0 Pin 5 Handler */
270 GPIO0_6_Handler, /* 78: GPIO0 Pin 6 Handler */
271 GPIO0_7_Handler, /* 79: GPIO0 Pin 7 Handler */
272 GPIO0_8_Handler, /* 80: GPIO0 Pin 8 Handler */
273 GPIO0_9_Handler, /* 81: GPIO0 Pin 9 Handler */
274 GPIO0_10_Handler, /* 82: GPIO0 Pin 10 Handler */
275 GPIO0_11_Handler, /* 83: GPIO0 Pin 11 Handler */
276 GPIO0_12_Handler, /* 84: GPIO0 Pin 12 Handler */
277 GPIO0_13_Handler, /* 85: GPIO0 Pin 13 Handler */
278 GPIO0_14_Handler, /* 86: GPIO0 Pin 14 Handler */
279 GPIO0_15_Handler, /* 87: GPIO0 Pin 15 Handler */
280 GPIO1_0_Handler, /* 88: GPIO1 Pin 0 Handler */
281 GPIO1_1_Handler, /* 89: GPIO1 Pin 1 Handler */
282 GPIO1_2_Handler, /* 90: GPIO1 Pin 2 Handler */
283 GPIO1_3_Handler, /* 91: GPIO1 Pin 3 Handler */
284 GPIO1_4_Handler, /* 92: GPIO1 Pin 4 Handler */
285 GPIO1_5_Handler, /* 93: GPIO1 Pin 5 Handler */
286 GPIO1_6_Handler, /* 94: GPIO1 Pin 6 Handler */
287 GPIO1_7_Handler, /* 95: GPIO1 Pin 7 Handler */
288 };
289
290 #if defined ( __GNUC__ )
291 #pragma GCC diagnostic pop
292 #endif
293
294 /*----------------------------------------------------------------------------
295 Reset Handler called on controller reset
296 *----------------------------------------------------------------------------*/
Reset_Handler(void)297 void Reset_Handler(void)
298 {
299 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
300 __disable_irq();
301 #endif
302 __set_PSP((uint32_t)(&__INITIAL_SP));
303
304 __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
305 __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
306
307 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
308 __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
309 #endif
310
311 SystemInit(); /* CMSIS System Initialization */
312 __PROGRAM_START(); /* Enter PreMain (C library entry point) */
313 }
314
