1 /* 2 ** ################################################################### 3 ** Processors: MKL25Z128VFM4 4 ** MKL25Z128VFT4 5 ** MKL25Z128VLH4 6 ** MKL25Z128VLK4 7 ** MKL25Z32VFM4 8 ** MKL25Z32VFT4 9 ** MKL25Z32VLH4 10 ** MKL25Z32VLK4 11 ** MKL25Z64VFM4 12 ** MKL25Z64VFT4 13 ** MKL25Z64VLH4 14 ** MKL25Z64VLK4 15 ** 16 ** Compilers: Keil ARM C/C++ Compiler 17 ** Freescale C/C++ for Embedded ARM 18 ** GNU C Compiler 19 ** IAR ANSI C/C++ Compiler for ARM 20 ** MCUXpresso Compiler 21 ** 22 ** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012 23 ** Version: rev. 2.5, 2015-02-19 24 ** Build: b170112 25 ** 26 ** Abstract: 27 ** CMSIS Peripheral Access Layer for MKL25Z4 28 ** 29 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. 30 ** Copyright 2016 - 2017 NXP 31 ** Redistribution and use in source and binary forms, with or without modification, 32 ** are permitted provided that the following conditions are met: 33 ** 34 ** o Redistributions of source code must retain the above copyright notice, this list 35 ** of conditions and the following disclaimer. 36 ** 37 ** o Redistributions in binary form must reproduce the above copyright notice, this 38 ** list of conditions and the following disclaimer in the documentation and/or 39 ** other materials provided with the distribution. 40 ** 41 ** o Neither the name of the copyright holder nor the names of its 42 ** contributors may be used to endorse or promote products derived from this 43 ** software without specific prior written permission. 44 ** 45 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 46 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 47 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 48 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 49 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 50 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 51 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 52 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 54 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 ** 56 ** http: www.nxp.com 57 ** mail: support@nxp.com 58 ** 59 ** Revisions: 60 ** - rev. 1.0 (2012-06-13) 61 ** Initial version. 62 ** - rev. 1.1 (2012-06-21) 63 ** Update according to reference manual rev. 1. 64 ** - rev. 1.2 (2012-08-01) 65 ** Device type UARTLP changed to UART0. 66 ** - rev. 1.3 (2012-10-04) 67 ** Update according to reference manual rev. 3. 68 ** - rev. 1.4 (2012-11-22) 69 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0. 70 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed. 71 ** - rev. 1.5 (2013-04-05) 72 ** Changed start of doxygen comment. 73 ** - rev. 2.0 (2013-10-29) 74 ** Register accessor macros added to the memory map. 75 ** Symbols for Processor Expert memory map compatibility added to the memory map. 76 ** Startup file for gcc has been updated according to CMSIS 3.2. 77 ** System initialization updated. 78 ** - rev. 2.1 (2014-07-16) 79 ** Module access macro module_BASES replaced by module_BASE_PTRS. 80 ** System initialization and startup updated. 81 ** - rev. 2.2 (2014-08-22) 82 ** System initialization updated - default clock config changed. 83 ** - rev. 2.3 (2014-08-28) 84 ** Update of startup files - possibility to override DefaultISR added. 85 ** - rev. 2.4 (2014-10-14) 86 ** Interrupt INT_LPTimer renamed to INT_LPTMR0. 87 ** - rev. 2.5 (2015-02-19) 88 ** Renamed interrupt vector LLW to LLWU. 89 ** 90 ** ################################################################### 91 */ 92 93 /*! 94 * @file MKL25Z4.h 95 * @version 2.5 96 * @date 2015-02-19 97 * @brief CMSIS Peripheral Access Layer for MKL25Z4 98 * 99 * CMSIS Peripheral Access Layer for MKL25Z4 100 */ 101 102 #ifndef _MKL25Z4_H_ 103 #define _MKL25Z4_H_ /**< Symbol preventing repeated inclusion */ 104 105 /** Memory map major version (memory maps with equal major version number are 106 * compatible) */ 107 #define MCU_MEM_MAP_VERSION 0x0200U 108 /** Memory map minor version */ 109 #define MCU_MEM_MAP_VERSION_MINOR 0x0005U 110 111 112 /* ---------------------------------------------------------------------------- 113 -- Interrupt vector numbers 114 ---------------------------------------------------------------------------- */ 115 116 /*! 117 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 118 * @{ 119 */ 120 121 /** Interrupt Number Definitions */ 122 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 123 124 typedef enum IRQn { 125 /* Auxiliary constants */ 126 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 127 128 /* Core interrupts */ 129 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 130 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 131 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 132 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 133 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 134 135 /* Device specific interrupts */ 136 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ 137 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ 138 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ 139 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ 140 Reserved20_IRQn = 4, /**< Reserved interrupt */ 141 FTFA_IRQn = 5, /**< Command complete and read collision */ 142 LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ 143 LLWU_IRQn = 7, /**< Low leakage wakeup Unit */ 144 I2C0_IRQn = 8, /**< I2C0 interrupt */ 145 I2C1_IRQn = 9, /**< I2C1 interrupt */ 146 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ 147 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */ 148 UART0_IRQn = 12, /**< UART0 status and error */ 149 UART1_IRQn = 13, /**< UART1 status and error */ 150 UART2_IRQn = 14, /**< UART2 status and error */ 151 ADC0_IRQn = 15, /**< ADC0 interrupt */ 152 CMP0_IRQn = 16, /**< CMP0 interrupt */ 153 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ 154 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ 155 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ 156 RTC_IRQn = 20, /**< RTC alarm */ 157 RTC_Seconds_IRQn = 21, /**< RTC seconds */ 158 PIT_IRQn = 22, /**< PIT interrupt */ 159 Reserved39_IRQn = 23, /**< Reserved interrupt */ 160 USB0_IRQn = 24, /**< USB0 interrupt */ 161 DAC0_IRQn = 25, /**< DAC0 interrupt */ 162 TSI0_IRQn = 26, /**< TSI0 interrupt */ 163 MCG_IRQn = 27, /**< MCG interrupt */ 164 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ 165 Reserved45_IRQn = 29, /**< Reserved interrupt */ 166 PORTA_IRQn = 30, /**< PORTA Pin detect */ 167 PORTD_IRQn = 31 /**< PORTD Pin detect */ 168 } IRQn_Type; 169 170 /*! 171 * @} 172 */ /* end of group Interrupt_vector_numbers */ 173 174 175 /* ---------------------------------------------------------------------------- 176 -- Cortex M0 Core Configuration 177 ---------------------------------------------------------------------------- */ 178 179 /*! 180 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 181 * @{ 182 */ 183 184 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 185 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 186 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 187 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 188 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 189 190 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 191 #include "system_MKL25Z4.h" /* Device specific configuration file */ 192 193 /*! 194 * @} 195 */ /* end of group Cortex_Core_Configuration */ 196 197 198 /* ---------------------------------------------------------------------------- 199 -- Mapping Information 200 ---------------------------------------------------------------------------- */ 201 202 /*! 203 * @addtogroup Mapping_Information Mapping Information 204 * @{ 205 */ 206 207 /** Mapping Information */ 208 /*! 209 * @addtogroup edma_request 210 * @{ 211 */ 212 213 /******************************************************************************* 214 * Definitions 215 ******************************************************************************/ 216 217 /*! 218 * @brief Structure for the DMA hardware request 219 * 220 * Defines the structure for the DMA hardware request collections. The user can configure the 221 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index 222 * of the hardware request varies according to the to SoC. 223 */ 224 typedef enum _dma_request_source 225 { 226 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ 227 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ 228 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ 229 kDmaRequestMux0LPSCI0Rx = 2|0x100U, /**< UART0 Receive. */ 230 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ 231 kDmaRequestMux0LPSCI0Tx = 3|0x100U, /**< UART0 Transmit. */ 232 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ 233 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ 234 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ 235 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ 236 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ 237 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ 238 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ 239 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ 240 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ 241 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ 242 kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ 243 kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ 244 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ 245 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ 246 kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ 247 kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ 248 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ 249 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ 250 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ 251 kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ 252 kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ 253 kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ 254 kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ 255 kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ 256 kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 C4V. */ 257 kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 C5V. */ 258 kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ 259 kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ 260 kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ 261 kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ 262 kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ 263 kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ 264 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ 265 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ 266 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ 267 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ 268 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ 269 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ 270 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ 271 kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ 272 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ 273 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ 274 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ 275 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ 276 kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ 277 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ 278 kDmaRequestMux0Reserved50 = 50|0x100U, /**< Reserved50 */ 279 kDmaRequestMux0Reserved51 = 51|0x100U, /**< Reserved51 */ 280 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ 281 kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ 282 kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ 283 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ 284 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ 285 kDmaRequestMux0TSI0 = 57|0x100U, /**< TSI0. */ 286 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ 287 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ 288 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ 289 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ 290 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ 291 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ 292 } dma_request_source_t; 293 294 /* @} */ 295 296 297 /*! 298 * @} 299 */ /* end of group Mapping_Information */ 300 301 302 /* ---------------------------------------------------------------------------- 303 -- Device Peripheral Access Layer 304 ---------------------------------------------------------------------------- */ 305 306 /*! 307 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 308 * @{ 309 */ 310 311 312 /* 313 ** Start of section using anonymous unions 314 */ 315 316 #if defined(__ARMCC_VERSION) 317 #pragma push 318 #pragma anon_unions 319 #elif defined(__CWCC__) 320 #pragma push 321 #pragma cpp_extensions on 322 #elif defined(__GNUC__) 323 /* anonymous unions are enabled by default */ 324 #elif defined(__IAR_SYSTEMS_ICC__) 325 #pragma language=extended 326 #else 327 #error Not supported compiler type 328 #endif 329 330 /* ---------------------------------------------------------------------------- 331 -- ADC Peripheral Access Layer 332 ---------------------------------------------------------------------------- */ 333 334 /*! 335 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 336 * @{ 337 */ 338 339 /** ADC - Register Layout Typedef */ 340 typedef struct { 341 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 342 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 343 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 344 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 345 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 346 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 347 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 348 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 349 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 350 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 351 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 352 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 353 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 354 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 355 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 356 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 357 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 358 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 359 uint8_t RESERVED_0[4]; 360 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 361 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 362 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 363 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 364 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 365 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 366 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 367 } ADC_Type; 368 369 /* ---------------------------------------------------------------------------- 370 -- ADC Register Masks 371 ---------------------------------------------------------------------------- */ 372 373 /*! 374 * @addtogroup ADC_Register_Masks ADC Register Masks 375 * @{ 376 */ 377 378 /*! @name SC1 - ADC Status and Control Registers 1 */ 379 #define ADC_SC1_ADCH_MASK (0x1FU) 380 #define ADC_SC1_ADCH_SHIFT (0U) 381 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 382 #define ADC_SC1_DIFF_MASK (0x20U) 383 #define ADC_SC1_DIFF_SHIFT (5U) 384 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) 385 #define ADC_SC1_AIEN_MASK (0x40U) 386 #define ADC_SC1_AIEN_SHIFT (6U) 387 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 388 #define ADC_SC1_COCO_MASK (0x80U) 389 #define ADC_SC1_COCO_SHIFT (7U) 390 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 391 392 /* The count of ADC_SC1 */ 393 #define ADC_SC1_COUNT (2U) 394 395 /*! @name CFG1 - ADC Configuration Register 1 */ 396 #define ADC_CFG1_ADICLK_MASK (0x3U) 397 #define ADC_CFG1_ADICLK_SHIFT (0U) 398 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 399 #define ADC_CFG1_MODE_MASK (0xCU) 400 #define ADC_CFG1_MODE_SHIFT (2U) 401 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 402 #define ADC_CFG1_ADLSMP_MASK (0x10U) 403 #define ADC_CFG1_ADLSMP_SHIFT (4U) 404 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) 405 #define ADC_CFG1_ADIV_MASK (0x60U) 406 #define ADC_CFG1_ADIV_SHIFT (5U) 407 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 408 #define ADC_CFG1_ADLPC_MASK (0x80U) 409 #define ADC_CFG1_ADLPC_SHIFT (7U) 410 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) 411 412 /*! @name CFG2 - ADC Configuration Register 2 */ 413 #define ADC_CFG2_ADLSTS_MASK (0x3U) 414 #define ADC_CFG2_ADLSTS_SHIFT (0U) 415 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) 416 #define ADC_CFG2_ADHSC_MASK (0x4U) 417 #define ADC_CFG2_ADHSC_SHIFT (2U) 418 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) 419 #define ADC_CFG2_ADACKEN_MASK (0x8U) 420 #define ADC_CFG2_ADACKEN_SHIFT (3U) 421 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) 422 #define ADC_CFG2_MUXSEL_MASK (0x10U) 423 #define ADC_CFG2_MUXSEL_SHIFT (4U) 424 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) 425 426 /*! @name R - ADC Data Result Register */ 427 #define ADC_R_D_MASK (0xFFFFU) 428 #define ADC_R_D_SHIFT (0U) 429 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 430 431 /* The count of ADC_R */ 432 #define ADC_R_COUNT (2U) 433 434 /*! @name CV1 - Compare Value Registers */ 435 #define ADC_CV1_CV_MASK (0xFFFFU) 436 #define ADC_CV1_CV_SHIFT (0U) 437 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 438 439 /*! @name CV2 - Compare Value Registers */ 440 #define ADC_CV2_CV_MASK (0xFFFFU) 441 #define ADC_CV2_CV_SHIFT (0U) 442 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 443 444 /*! @name SC2 - Status and Control Register 2 */ 445 #define ADC_SC2_REFSEL_MASK (0x3U) 446 #define ADC_SC2_REFSEL_SHIFT (0U) 447 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 448 #define ADC_SC2_DMAEN_MASK (0x4U) 449 #define ADC_SC2_DMAEN_SHIFT (2U) 450 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 451 #define ADC_SC2_ACREN_MASK (0x8U) 452 #define ADC_SC2_ACREN_SHIFT (3U) 453 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 454 #define ADC_SC2_ACFGT_MASK (0x10U) 455 #define ADC_SC2_ACFGT_SHIFT (4U) 456 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 457 #define ADC_SC2_ACFE_MASK (0x20U) 458 #define ADC_SC2_ACFE_SHIFT (5U) 459 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 460 #define ADC_SC2_ADTRG_MASK (0x40U) 461 #define ADC_SC2_ADTRG_SHIFT (6U) 462 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 463 #define ADC_SC2_ADACT_MASK (0x80U) 464 #define ADC_SC2_ADACT_SHIFT (7U) 465 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 466 467 /*! @name SC3 - Status and Control Register 3 */ 468 #define ADC_SC3_AVGS_MASK (0x3U) 469 #define ADC_SC3_AVGS_SHIFT (0U) 470 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 471 #define ADC_SC3_AVGE_MASK (0x4U) 472 #define ADC_SC3_AVGE_SHIFT (2U) 473 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 474 #define ADC_SC3_ADCO_MASK (0x8U) 475 #define ADC_SC3_ADCO_SHIFT (3U) 476 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 477 #define ADC_SC3_CALF_MASK (0x40U) 478 #define ADC_SC3_CALF_SHIFT (6U) 479 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) 480 #define ADC_SC3_CAL_MASK (0x80U) 481 #define ADC_SC3_CAL_SHIFT (7U) 482 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 483 484 /*! @name OFS - ADC Offset Correction Register */ 485 #define ADC_OFS_OFS_MASK (0xFFFFU) 486 #define ADC_OFS_OFS_SHIFT (0U) 487 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 488 489 /*! @name PG - ADC Plus-Side Gain Register */ 490 #define ADC_PG_PG_MASK (0xFFFFU) 491 #define ADC_PG_PG_SHIFT (0U) 492 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) 493 494 /*! @name MG - ADC Minus-Side Gain Register */ 495 #define ADC_MG_MG_MASK (0xFFFFU) 496 #define ADC_MG_MG_SHIFT (0U) 497 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) 498 499 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ 500 #define ADC_CLPD_CLPD_MASK (0x3FU) 501 #define ADC_CLPD_CLPD_SHIFT (0U) 502 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) 503 504 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ 505 #define ADC_CLPS_CLPS_MASK (0x3FU) 506 #define ADC_CLPS_CLPS_SHIFT (0U) 507 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 508 509 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ 510 #define ADC_CLP4_CLP4_MASK (0x3FFU) 511 #define ADC_CLP4_CLP4_SHIFT (0U) 512 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) 513 514 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ 515 #define ADC_CLP3_CLP3_MASK (0x1FFU) 516 #define ADC_CLP3_CLP3_SHIFT (0U) 517 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 518 519 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ 520 #define ADC_CLP2_CLP2_MASK (0xFFU) 521 #define ADC_CLP2_CLP2_SHIFT (0U) 522 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 523 524 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ 525 #define ADC_CLP1_CLP1_MASK (0x7FU) 526 #define ADC_CLP1_CLP1_SHIFT (0U) 527 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 528 529 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ 530 #define ADC_CLP0_CLP0_MASK (0x3FU) 531 #define ADC_CLP0_CLP0_SHIFT (0U) 532 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 533 534 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ 535 #define ADC_CLMD_CLMD_MASK (0x3FU) 536 #define ADC_CLMD_CLMD_SHIFT (0U) 537 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) 538 539 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ 540 #define ADC_CLMS_CLMS_MASK (0x3FU) 541 #define ADC_CLMS_CLMS_SHIFT (0U) 542 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) 543 544 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ 545 #define ADC_CLM4_CLM4_MASK (0x3FFU) 546 #define ADC_CLM4_CLM4_SHIFT (0U) 547 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) 548 549 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ 550 #define ADC_CLM3_CLM3_MASK (0x1FFU) 551 #define ADC_CLM3_CLM3_SHIFT (0U) 552 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) 553 554 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ 555 #define ADC_CLM2_CLM2_MASK (0xFFU) 556 #define ADC_CLM2_CLM2_SHIFT (0U) 557 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) 558 559 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ 560 #define ADC_CLM1_CLM1_MASK (0x7FU) 561 #define ADC_CLM1_CLM1_SHIFT (0U) 562 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) 563 564 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ 565 #define ADC_CLM0_CLM0_MASK (0x3FU) 566 #define ADC_CLM0_CLM0_SHIFT (0U) 567 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) 568 569 570 /*! 571 * @} 572 */ /* end of group ADC_Register_Masks */ 573 574 575 /* ADC - Peripheral instance base addresses */ 576 /** Peripheral ADC0 base address */ 577 #define ADC0_BASE (0x4003B000u) 578 /** Peripheral ADC0 base pointer */ 579 #define ADC0 ((ADC_Type *)ADC0_BASE) 580 /** Array initializer of ADC peripheral base addresses */ 581 #define ADC_BASE_ADDRS { ADC0_BASE } 582 /** Array initializer of ADC peripheral base pointers */ 583 #define ADC_BASE_PTRS { ADC0 } 584 /** Interrupt vectors for the ADC peripheral type */ 585 #define ADC_IRQS { ADC0_IRQn } 586 587 /*! 588 * @} 589 */ /* end of group ADC_Peripheral_Access_Layer */ 590 591 592 /* ---------------------------------------------------------------------------- 593 -- CMP Peripheral Access Layer 594 ---------------------------------------------------------------------------- */ 595 596 /*! 597 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 598 * @{ 599 */ 600 601 /** CMP - Register Layout Typedef */ 602 typedef struct { 603 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 604 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 605 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 606 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 607 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 608 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 609 } CMP_Type; 610 611 /* ---------------------------------------------------------------------------- 612 -- CMP Register Masks 613 ---------------------------------------------------------------------------- */ 614 615 /*! 616 * @addtogroup CMP_Register_Masks CMP Register Masks 617 * @{ 618 */ 619 620 /*! @name CR0 - CMP Control Register 0 */ 621 #define CMP_CR0_HYSTCTR_MASK (0x3U) 622 #define CMP_CR0_HYSTCTR_SHIFT (0U) 623 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) 624 #define CMP_CR0_FILTER_CNT_MASK (0x70U) 625 #define CMP_CR0_FILTER_CNT_SHIFT (4U) 626 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) 627 628 /*! @name CR1 - CMP Control Register 1 */ 629 #define CMP_CR1_EN_MASK (0x1U) 630 #define CMP_CR1_EN_SHIFT (0U) 631 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) 632 #define CMP_CR1_OPE_MASK (0x2U) 633 #define CMP_CR1_OPE_SHIFT (1U) 634 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) 635 #define CMP_CR1_COS_MASK (0x4U) 636 #define CMP_CR1_COS_SHIFT (2U) 637 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) 638 #define CMP_CR1_INV_MASK (0x8U) 639 #define CMP_CR1_INV_SHIFT (3U) 640 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) 641 #define CMP_CR1_PMODE_MASK (0x10U) 642 #define CMP_CR1_PMODE_SHIFT (4U) 643 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) 644 #define CMP_CR1_TRIGM_MASK (0x20U) 645 #define CMP_CR1_TRIGM_SHIFT (5U) 646 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) 647 #define CMP_CR1_WE_MASK (0x40U) 648 #define CMP_CR1_WE_SHIFT (6U) 649 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) 650 #define CMP_CR1_SE_MASK (0x80U) 651 #define CMP_CR1_SE_SHIFT (7U) 652 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) 653 654 /*! @name FPR - CMP Filter Period Register */ 655 #define CMP_FPR_FILT_PER_MASK (0xFFU) 656 #define CMP_FPR_FILT_PER_SHIFT (0U) 657 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) 658 659 /*! @name SCR - CMP Status and Control Register */ 660 #define CMP_SCR_COUT_MASK (0x1U) 661 #define CMP_SCR_COUT_SHIFT (0U) 662 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) 663 #define CMP_SCR_CFF_MASK (0x2U) 664 #define CMP_SCR_CFF_SHIFT (1U) 665 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) 666 #define CMP_SCR_CFR_MASK (0x4U) 667 #define CMP_SCR_CFR_SHIFT (2U) 668 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) 669 #define CMP_SCR_IEF_MASK (0x8U) 670 #define CMP_SCR_IEF_SHIFT (3U) 671 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) 672 #define CMP_SCR_IER_MASK (0x10U) 673 #define CMP_SCR_IER_SHIFT (4U) 674 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) 675 #define CMP_SCR_DMAEN_MASK (0x40U) 676 #define CMP_SCR_DMAEN_SHIFT (6U) 677 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) 678 679 /*! @name DACCR - DAC Control Register */ 680 #define CMP_DACCR_VOSEL_MASK (0x3FU) 681 #define CMP_DACCR_VOSEL_SHIFT (0U) 682 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) 683 #define CMP_DACCR_VRSEL_MASK (0x40U) 684 #define CMP_DACCR_VRSEL_SHIFT (6U) 685 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) 686 #define CMP_DACCR_DACEN_MASK (0x80U) 687 #define CMP_DACCR_DACEN_SHIFT (7U) 688 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) 689 690 /*! @name MUXCR - MUX Control Register */ 691 #define CMP_MUXCR_MSEL_MASK (0x7U) 692 #define CMP_MUXCR_MSEL_SHIFT (0U) 693 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) 694 #define CMP_MUXCR_PSEL_MASK (0x38U) 695 #define CMP_MUXCR_PSEL_SHIFT (3U) 696 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) 697 #define CMP_MUXCR_PSTM_MASK (0x80U) 698 #define CMP_MUXCR_PSTM_SHIFT (7U) 699 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) 700 701 702 /*! 703 * @} 704 */ /* end of group CMP_Register_Masks */ 705 706 707 /* CMP - Peripheral instance base addresses */ 708 /** Peripheral CMP0 base address */ 709 #define CMP0_BASE (0x40073000u) 710 /** Peripheral CMP0 base pointer */ 711 #define CMP0 ((CMP_Type *)CMP0_BASE) 712 /** Array initializer of CMP peripheral base addresses */ 713 #define CMP_BASE_ADDRS { CMP0_BASE } 714 /** Array initializer of CMP peripheral base pointers */ 715 #define CMP_BASE_PTRS { CMP0 } 716 /** Interrupt vectors for the CMP peripheral type */ 717 #define CMP_IRQS { CMP0_IRQn } 718 719 /*! 720 * @} 721 */ /* end of group CMP_Peripheral_Access_Layer */ 722 723 724 /* ---------------------------------------------------------------------------- 725 -- DAC Peripheral Access Layer 726 ---------------------------------------------------------------------------- */ 727 728 /*! 729 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 730 * @{ 731 */ 732 733 /** DAC - Register Layout Typedef */ 734 typedef struct { 735 struct { /* offset: 0x0, array step: 0x2 */ 736 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 737 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 738 } DAT[2]; 739 uint8_t RESERVED_0[28]; 740 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 741 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 742 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 743 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 744 } DAC_Type; 745 746 /* ---------------------------------------------------------------------------- 747 -- DAC Register Masks 748 ---------------------------------------------------------------------------- */ 749 750 /*! 751 * @addtogroup DAC_Register_Masks DAC Register Masks 752 * @{ 753 */ 754 755 /*! @name DATL - DAC Data Low Register */ 756 #define DAC_DATL_DATA0_MASK (0xFFU) 757 #define DAC_DATL_DATA0_SHIFT (0U) 758 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) 759 760 /* The count of DAC_DATL */ 761 #define DAC_DATL_COUNT (2U) 762 763 /*! @name DATH - DAC Data High Register */ 764 #define DAC_DATH_DATA1_MASK (0xFU) 765 #define DAC_DATH_DATA1_SHIFT (0U) 766 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) 767 768 /* The count of DAC_DATH */ 769 #define DAC_DATH_COUNT (2U) 770 771 /*! @name SR - DAC Status Register */ 772 #define DAC_SR_DACBFRPBF_MASK (0x1U) 773 #define DAC_SR_DACBFRPBF_SHIFT (0U) 774 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) 775 #define DAC_SR_DACBFRPTF_MASK (0x2U) 776 #define DAC_SR_DACBFRPTF_SHIFT (1U) 777 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) 778 779 /*! @name C0 - DAC Control Register */ 780 #define DAC_C0_DACBBIEN_MASK (0x1U) 781 #define DAC_C0_DACBBIEN_SHIFT (0U) 782 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) 783 #define DAC_C0_DACBTIEN_MASK (0x2U) 784 #define DAC_C0_DACBTIEN_SHIFT (1U) 785 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) 786 #define DAC_C0_LPEN_MASK (0x8U) 787 #define DAC_C0_LPEN_SHIFT (3U) 788 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) 789 #define DAC_C0_DACSWTRG_MASK (0x10U) 790 #define DAC_C0_DACSWTRG_SHIFT (4U) 791 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) 792 #define DAC_C0_DACTRGSEL_MASK (0x20U) 793 #define DAC_C0_DACTRGSEL_SHIFT (5U) 794 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) 795 #define DAC_C0_DACRFS_MASK (0x40U) 796 #define DAC_C0_DACRFS_SHIFT (6U) 797 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) 798 #define DAC_C0_DACEN_MASK (0x80U) 799 #define DAC_C0_DACEN_SHIFT (7U) 800 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) 801 802 /*! @name C1 - DAC Control Register 1 */ 803 #define DAC_C1_DACBFEN_MASK (0x1U) 804 #define DAC_C1_DACBFEN_SHIFT (0U) 805 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) 806 #define DAC_C1_DACBFMD_MASK (0x4U) 807 #define DAC_C1_DACBFMD_SHIFT (2U) 808 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) 809 #define DAC_C1_DMAEN_MASK (0x80U) 810 #define DAC_C1_DMAEN_SHIFT (7U) 811 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) 812 813 /*! @name C2 - DAC Control Register 2 */ 814 #define DAC_C2_DACBFUP_MASK (0x1U) 815 #define DAC_C2_DACBFUP_SHIFT (0U) 816 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) 817 #define DAC_C2_DACBFRP_MASK (0x10U) 818 #define DAC_C2_DACBFRP_SHIFT (4U) 819 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) 820 821 822 /*! 823 * @} 824 */ /* end of group DAC_Register_Masks */ 825 826 827 /* DAC - Peripheral instance base addresses */ 828 /** Peripheral DAC0 base address */ 829 #define DAC0_BASE (0x4003F000u) 830 /** Peripheral DAC0 base pointer */ 831 #define DAC0 ((DAC_Type *)DAC0_BASE) 832 /** Array initializer of DAC peripheral base addresses */ 833 #define DAC_BASE_ADDRS { DAC0_BASE } 834 /** Array initializer of DAC peripheral base pointers */ 835 #define DAC_BASE_PTRS { DAC0 } 836 /** Interrupt vectors for the DAC peripheral type */ 837 #define DAC_IRQS { DAC0_IRQn } 838 839 /*! 840 * @} 841 */ /* end of group DAC_Peripheral_Access_Layer */ 842 843 844 /* ---------------------------------------------------------------------------- 845 -- DMA Peripheral Access Layer 846 ---------------------------------------------------------------------------- */ 847 848 /*! 849 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 850 * @{ 851 */ 852 853 /** DMA - Register Layout Typedef */ 854 typedef struct { 855 uint8_t RESERVED_0[256]; 856 struct { /* offset: 0x100, array step: 0x10 */ 857 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ 858 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ 859 union { /* offset: 0x108, array step: 0x10 */ 860 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ 861 struct { /* offset: 0x108, array step: 0x10 */ 862 uint8_t RESERVED_0[3]; 863 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ 864 } DMA_DSR_ACCESS8BIT; 865 }; 866 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ 867 } DMA[4]; 868 } DMA_Type; 869 870 /* ---------------------------------------------------------------------------- 871 -- DMA Register Masks 872 ---------------------------------------------------------------------------- */ 873 874 /*! 875 * @addtogroup DMA_Register_Masks DMA Register Masks 876 * @{ 877 */ 878 879 /*! @name SAR - Source Address Register */ 880 #define DMA_SAR_SAR_MASK (0xFFFFFFFFU) 881 #define DMA_SAR_SAR_SHIFT (0U) 882 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK) 883 884 /* The count of DMA_SAR */ 885 #define DMA_SAR_COUNT (4U) 886 887 /*! @name DAR - Destination Address Register */ 888 #define DMA_DAR_DAR_MASK (0xFFFFFFFFU) 889 #define DMA_DAR_DAR_SHIFT (0U) 890 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK) 891 892 /* The count of DMA_DAR */ 893 #define DMA_DAR_COUNT (4U) 894 895 /*! @name DSR_BCR - DMA Status Register / Byte Count Register */ 896 #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU) 897 #define DMA_DSR_BCR_BCR_SHIFT (0U) 898 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK) 899 #define DMA_DSR_BCR_DONE_MASK (0x1000000U) 900 #define DMA_DSR_BCR_DONE_SHIFT (24U) 901 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK) 902 #define DMA_DSR_BCR_BSY_MASK (0x2000000U) 903 #define DMA_DSR_BCR_BSY_SHIFT (25U) 904 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK) 905 #define DMA_DSR_BCR_REQ_MASK (0x4000000U) 906 #define DMA_DSR_BCR_REQ_SHIFT (26U) 907 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK) 908 #define DMA_DSR_BCR_BED_MASK (0x10000000U) 909 #define DMA_DSR_BCR_BED_SHIFT (28U) 910 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK) 911 #define DMA_DSR_BCR_BES_MASK (0x20000000U) 912 #define DMA_DSR_BCR_BES_SHIFT (29U) 913 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK) 914 #define DMA_DSR_BCR_CE_MASK (0x40000000U) 915 #define DMA_DSR_BCR_CE_SHIFT (30U) 916 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK) 917 918 /* The count of DMA_DSR_BCR */ 919 #define DMA_DSR_BCR_COUNT (4U) 920 921 /* The count of DMA_DSR */ 922 #define DMA_DSR_COUNT (4U) 923 924 /*! @name DCR - DMA Control Register */ 925 #define DMA_DCR_LCH2_MASK (0x3U) 926 #define DMA_DCR_LCH2_SHIFT (0U) 927 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK) 928 #define DMA_DCR_LCH1_MASK (0xCU) 929 #define DMA_DCR_LCH1_SHIFT (2U) 930 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK) 931 #define DMA_DCR_LINKCC_MASK (0x30U) 932 #define DMA_DCR_LINKCC_SHIFT (4U) 933 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK) 934 #define DMA_DCR_D_REQ_MASK (0x80U) 935 #define DMA_DCR_D_REQ_SHIFT (7U) 936 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK) 937 #define DMA_DCR_DMOD_MASK (0xF00U) 938 #define DMA_DCR_DMOD_SHIFT (8U) 939 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK) 940 #define DMA_DCR_SMOD_MASK (0xF000U) 941 #define DMA_DCR_SMOD_SHIFT (12U) 942 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK) 943 #define DMA_DCR_START_MASK (0x10000U) 944 #define DMA_DCR_START_SHIFT (16U) 945 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK) 946 #define DMA_DCR_DSIZE_MASK (0x60000U) 947 #define DMA_DCR_DSIZE_SHIFT (17U) 948 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK) 949 #define DMA_DCR_DINC_MASK (0x80000U) 950 #define DMA_DCR_DINC_SHIFT (19U) 951 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK) 952 #define DMA_DCR_SSIZE_MASK (0x300000U) 953 #define DMA_DCR_SSIZE_SHIFT (20U) 954 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK) 955 #define DMA_DCR_SINC_MASK (0x400000U) 956 #define DMA_DCR_SINC_SHIFT (22U) 957 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK) 958 #define DMA_DCR_EADREQ_MASK (0x800000U) 959 #define DMA_DCR_EADREQ_SHIFT (23U) 960 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK) 961 #define DMA_DCR_AA_MASK (0x10000000U) 962 #define DMA_DCR_AA_SHIFT (28U) 963 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK) 964 #define DMA_DCR_CS_MASK (0x20000000U) 965 #define DMA_DCR_CS_SHIFT (29U) 966 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK) 967 #define DMA_DCR_ERQ_MASK (0x40000000U) 968 #define DMA_DCR_ERQ_SHIFT (30U) 969 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK) 970 #define DMA_DCR_EINT_MASK (0x80000000U) 971 #define DMA_DCR_EINT_SHIFT (31U) 972 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK) 973 974 /* The count of DMA_DCR */ 975 #define DMA_DCR_COUNT (4U) 976 977 978 /*! 979 * @} 980 */ /* end of group DMA_Register_Masks */ 981 982 983 /* DMA - Peripheral instance base addresses */ 984 /** Peripheral DMA base address */ 985 #define DMA_BASE (0x40008000u) 986 /** Peripheral DMA base pointer */ 987 #define DMA0 ((DMA_Type *)DMA_BASE) 988 /** Array initializer of DMA peripheral base addresses */ 989 #define DMA_BASE_ADDRS { DMA_BASE } 990 /** Array initializer of DMA peripheral base pointers */ 991 #define DMA_BASE_PTRS { DMA0 } 992 /** Interrupt vectors for the DMA peripheral type */ 993 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } } 994 995 /*! 996 * @} 997 */ /* end of group DMA_Peripheral_Access_Layer */ 998 999 1000 /* ---------------------------------------------------------------------------- 1001 -- DMAMUX Peripheral Access Layer 1002 ---------------------------------------------------------------------------- */ 1003 1004 /*! 1005 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 1006 * @{ 1007 */ 1008 1009 /** DMAMUX - Register Layout Typedef */ 1010 typedef struct { 1011 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 1012 } DMAMUX_Type; 1013 1014 /* ---------------------------------------------------------------------------- 1015 -- DMAMUX Register Masks 1016 ---------------------------------------------------------------------------- */ 1017 1018 /*! 1019 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 1020 * @{ 1021 */ 1022 1023 /*! @name CHCFG - Channel Configuration register */ 1024 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) 1025 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) 1026 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) 1027 #define DMAMUX_CHCFG_TRIG_MASK (0x40U) 1028 #define DMAMUX_CHCFG_TRIG_SHIFT (6U) 1029 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) 1030 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) 1031 #define DMAMUX_CHCFG_ENBL_SHIFT (7U) 1032 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) 1033 1034 /* The count of DMAMUX_CHCFG */ 1035 #define DMAMUX_CHCFG_COUNT (4U) 1036 1037 1038 /*! 1039 * @} 1040 */ /* end of group DMAMUX_Register_Masks */ 1041 1042 1043 /* DMAMUX - Peripheral instance base addresses */ 1044 /** Peripheral DMAMUX0 base address */ 1045 #define DMAMUX0_BASE (0x40021000u) 1046 /** Peripheral DMAMUX0 base pointer */ 1047 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) 1048 /** Array initializer of DMAMUX peripheral base addresses */ 1049 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } 1050 /** Array initializer of DMAMUX peripheral base pointers */ 1051 #define DMAMUX_BASE_PTRS { DMAMUX0 } 1052 1053 /*! 1054 * @} 1055 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 1056 1057 1058 /* ---------------------------------------------------------------------------- 1059 -- FGPIO Peripheral Access Layer 1060 ---------------------------------------------------------------------------- */ 1061 1062 /*! 1063 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 1064 * @{ 1065 */ 1066 1067 /** FGPIO - Register Layout Typedef */ 1068 typedef struct { 1069 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 1070 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 1071 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 1072 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 1073 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 1074 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 1075 } FGPIO_Type; 1076 1077 /* ---------------------------------------------------------------------------- 1078 -- FGPIO Register Masks 1079 ---------------------------------------------------------------------------- */ 1080 1081 /*! 1082 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 1083 * @{ 1084 */ 1085 1086 /*! @name PDOR - Port Data Output Register */ 1087 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 1088 #define FGPIO_PDOR_PDO_SHIFT (0U) 1089 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 1090 1091 /*! @name PSOR - Port Set Output Register */ 1092 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 1093 #define FGPIO_PSOR_PTSO_SHIFT (0U) 1094 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 1095 1096 /*! @name PCOR - Port Clear Output Register */ 1097 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 1098 #define FGPIO_PCOR_PTCO_SHIFT (0U) 1099 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 1100 1101 /*! @name PTOR - Port Toggle Output Register */ 1102 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 1103 #define FGPIO_PTOR_PTTO_SHIFT (0U) 1104 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 1105 1106 /*! @name PDIR - Port Data Input Register */ 1107 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 1108 #define FGPIO_PDIR_PDI_SHIFT (0U) 1109 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 1110 1111 /*! @name PDDR - Port Data Direction Register */ 1112 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 1113 #define FGPIO_PDDR_PDD_SHIFT (0U) 1114 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 1115 1116 1117 /*! 1118 * @} 1119 */ /* end of group FGPIO_Register_Masks */ 1120 1121 1122 /* FGPIO - Peripheral instance base addresses */ 1123 /** Peripheral FGPIOA base address */ 1124 #define FGPIOA_BASE (0xF80FF000u) 1125 /** Peripheral FGPIOA base pointer */ 1126 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 1127 /** Peripheral FGPIOB base address */ 1128 #define FGPIOB_BASE (0xF80FF040u) 1129 /** Peripheral FGPIOB base pointer */ 1130 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) 1131 /** Peripheral FGPIOC base address */ 1132 #define FGPIOC_BASE (0xF80FF080u) 1133 /** Peripheral FGPIOC base pointer */ 1134 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) 1135 /** Peripheral FGPIOD base address */ 1136 #define FGPIOD_BASE (0xF80FF0C0u) 1137 /** Peripheral FGPIOD base pointer */ 1138 #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE) 1139 /** Peripheral FGPIOE base address */ 1140 #define FGPIOE_BASE (0xF80FF100u) 1141 /** Peripheral FGPIOE base pointer */ 1142 #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) 1143 /** Array initializer of FGPIO peripheral base addresses */ 1144 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE } 1145 /** Array initializer of FGPIO peripheral base pointers */ 1146 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE } 1147 1148 /*! 1149 * @} 1150 */ /* end of group FGPIO_Peripheral_Access_Layer */ 1151 1152 1153 /* ---------------------------------------------------------------------------- 1154 -- FTFA Peripheral Access Layer 1155 ---------------------------------------------------------------------------- */ 1156 1157 /*! 1158 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 1159 * @{ 1160 */ 1161 1162 /** FTFA - Register Layout Typedef */ 1163 typedef struct { 1164 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 1165 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 1166 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 1167 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 1168 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 1169 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 1170 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 1171 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 1172 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 1173 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 1174 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 1175 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 1176 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 1177 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 1178 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 1179 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 1180 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 1181 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 1182 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 1183 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 1184 } FTFA_Type; 1185 1186 /* ---------------------------------------------------------------------------- 1187 -- FTFA Register Masks 1188 ---------------------------------------------------------------------------- */ 1189 1190 /*! 1191 * @addtogroup FTFA_Register_Masks FTFA Register Masks 1192 * @{ 1193 */ 1194 1195 /*! @name FSTAT - Flash Status Register */ 1196 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) 1197 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) 1198 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) 1199 #define FTFA_FSTAT_FPVIOL_MASK (0x10U) 1200 #define FTFA_FSTAT_FPVIOL_SHIFT (4U) 1201 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) 1202 #define FTFA_FSTAT_ACCERR_MASK (0x20U) 1203 #define FTFA_FSTAT_ACCERR_SHIFT (5U) 1204 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) 1205 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) 1206 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) 1207 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) 1208 #define FTFA_FSTAT_CCIF_MASK (0x80U) 1209 #define FTFA_FSTAT_CCIF_SHIFT (7U) 1210 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) 1211 1212 /*! @name FCNFG - Flash Configuration Register */ 1213 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) 1214 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) 1215 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) 1216 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) 1217 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) 1218 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) 1219 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) 1220 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) 1221 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) 1222 #define FTFA_FCNFG_CCIE_MASK (0x80U) 1223 #define FTFA_FCNFG_CCIE_SHIFT (7U) 1224 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) 1225 1226 /*! @name FSEC - Flash Security Register */ 1227 #define FTFA_FSEC_SEC_MASK (0x3U) 1228 #define FTFA_FSEC_SEC_SHIFT (0U) 1229 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) 1230 #define FTFA_FSEC_FSLACC_MASK (0xCU) 1231 #define FTFA_FSEC_FSLACC_SHIFT (2U) 1232 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) 1233 #define FTFA_FSEC_MEEN_MASK (0x30U) 1234 #define FTFA_FSEC_MEEN_SHIFT (4U) 1235 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) 1236 #define FTFA_FSEC_KEYEN_MASK (0xC0U) 1237 #define FTFA_FSEC_KEYEN_SHIFT (6U) 1238 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) 1239 1240 /*! @name FOPT - Flash Option Register */ 1241 #define FTFA_FOPT_OPT_MASK (0xFFU) 1242 #define FTFA_FOPT_OPT_SHIFT (0U) 1243 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) 1244 1245 /*! @name FCCOB3 - Flash Common Command Object Registers */ 1246 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) 1247 #define FTFA_FCCOB3_CCOBn_SHIFT (0U) 1248 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) 1249 1250 /*! @name FCCOB2 - Flash Common Command Object Registers */ 1251 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) 1252 #define FTFA_FCCOB2_CCOBn_SHIFT (0U) 1253 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) 1254 1255 /*! @name FCCOB1 - Flash Common Command Object Registers */ 1256 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) 1257 #define FTFA_FCCOB1_CCOBn_SHIFT (0U) 1258 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) 1259 1260 /*! @name FCCOB0 - Flash Common Command Object Registers */ 1261 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) 1262 #define FTFA_FCCOB0_CCOBn_SHIFT (0U) 1263 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) 1264 1265 /*! @name FCCOB7 - Flash Common Command Object Registers */ 1266 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) 1267 #define FTFA_FCCOB7_CCOBn_SHIFT (0U) 1268 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) 1269 1270 /*! @name FCCOB6 - Flash Common Command Object Registers */ 1271 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) 1272 #define FTFA_FCCOB6_CCOBn_SHIFT (0U) 1273 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) 1274 1275 /*! @name FCCOB5 - Flash Common Command Object Registers */ 1276 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) 1277 #define FTFA_FCCOB5_CCOBn_SHIFT (0U) 1278 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) 1279 1280 /*! @name FCCOB4 - Flash Common Command Object Registers */ 1281 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) 1282 #define FTFA_FCCOB4_CCOBn_SHIFT (0U) 1283 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) 1284 1285 /*! @name FCCOBB - Flash Common Command Object Registers */ 1286 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) 1287 #define FTFA_FCCOBB_CCOBn_SHIFT (0U) 1288 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) 1289 1290 /*! @name FCCOBA - Flash Common Command Object Registers */ 1291 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) 1292 #define FTFA_FCCOBA_CCOBn_SHIFT (0U) 1293 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) 1294 1295 /*! @name FCCOB9 - Flash Common Command Object Registers */ 1296 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) 1297 #define FTFA_FCCOB9_CCOBn_SHIFT (0U) 1298 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) 1299 1300 /*! @name FCCOB8 - Flash Common Command Object Registers */ 1301 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) 1302 #define FTFA_FCCOB8_CCOBn_SHIFT (0U) 1303 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) 1304 1305 /*! @name FPROT3 - Program Flash Protection Registers */ 1306 #define FTFA_FPROT3_PROT_MASK (0xFFU) 1307 #define FTFA_FPROT3_PROT_SHIFT (0U) 1308 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) 1309 1310 /*! @name FPROT2 - Program Flash Protection Registers */ 1311 #define FTFA_FPROT2_PROT_MASK (0xFFU) 1312 #define FTFA_FPROT2_PROT_SHIFT (0U) 1313 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) 1314 1315 /*! @name FPROT1 - Program Flash Protection Registers */ 1316 #define FTFA_FPROT1_PROT_MASK (0xFFU) 1317 #define FTFA_FPROT1_PROT_SHIFT (0U) 1318 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) 1319 1320 /*! @name FPROT0 - Program Flash Protection Registers */ 1321 #define FTFA_FPROT0_PROT_MASK (0xFFU) 1322 #define FTFA_FPROT0_PROT_SHIFT (0U) 1323 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) 1324 1325 1326 /*! 1327 * @} 1328 */ /* end of group FTFA_Register_Masks */ 1329 1330 1331 /* FTFA - Peripheral instance base addresses */ 1332 /** Peripheral FTFA base address */ 1333 #define FTFA_BASE (0x40020000u) 1334 /** Peripheral FTFA base pointer */ 1335 #define FTFA ((FTFA_Type *)FTFA_BASE) 1336 /** Array initializer of FTFA peripheral base addresses */ 1337 #define FTFA_BASE_ADDRS { FTFA_BASE } 1338 /** Array initializer of FTFA peripheral base pointers */ 1339 #define FTFA_BASE_PTRS { FTFA } 1340 /** Interrupt vectors for the FTFA peripheral type */ 1341 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } 1342 1343 /*! 1344 * @} 1345 */ /* end of group FTFA_Peripheral_Access_Layer */ 1346 1347 1348 /* ---------------------------------------------------------------------------- 1349 -- GPIO Peripheral Access Layer 1350 ---------------------------------------------------------------------------- */ 1351 1352 /*! 1353 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 1354 * @{ 1355 */ 1356 1357 /** GPIO - Register Layout Typedef */ 1358 typedef struct { 1359 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 1360 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 1361 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 1362 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 1363 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 1364 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 1365 } GPIO_Type; 1366 1367 /* ---------------------------------------------------------------------------- 1368 -- GPIO Register Masks 1369 ---------------------------------------------------------------------------- */ 1370 1371 /*! 1372 * @addtogroup GPIO_Register_Masks GPIO Register Masks 1373 * @{ 1374 */ 1375 1376 /*! @name PDOR - Port Data Output Register */ 1377 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 1378 #define GPIO_PDOR_PDO_SHIFT (0U) 1379 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 1380 1381 /*! @name PSOR - Port Set Output Register */ 1382 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 1383 #define GPIO_PSOR_PTSO_SHIFT (0U) 1384 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 1385 1386 /*! @name PCOR - Port Clear Output Register */ 1387 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 1388 #define GPIO_PCOR_PTCO_SHIFT (0U) 1389 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 1390 1391 /*! @name PTOR - Port Toggle Output Register */ 1392 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 1393 #define GPIO_PTOR_PTTO_SHIFT (0U) 1394 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 1395 1396 /*! @name PDIR - Port Data Input Register */ 1397 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 1398 #define GPIO_PDIR_PDI_SHIFT (0U) 1399 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 1400 1401 /*! @name PDDR - Port Data Direction Register */ 1402 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 1403 #define GPIO_PDDR_PDD_SHIFT (0U) 1404 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 1405 1406 1407 /*! 1408 * @} 1409 */ /* end of group GPIO_Register_Masks */ 1410 1411 1412 /* GPIO - Peripheral instance base addresses */ 1413 /** Peripheral GPIOA base address */ 1414 #define GPIOA_BASE (0x400FF000u) 1415 /** Peripheral GPIOA base pointer */ 1416 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 1417 /** Peripheral GPIOB base address */ 1418 #define GPIOB_BASE (0x400FF040u) 1419 /** Peripheral GPIOB base pointer */ 1420 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 1421 /** Peripheral GPIOC base address */ 1422 #define GPIOC_BASE (0x400FF080u) 1423 /** Peripheral GPIOC base pointer */ 1424 #define GPIOC ((GPIO_Type *)GPIOC_BASE) 1425 /** Peripheral GPIOD base address */ 1426 #define GPIOD_BASE (0x400FF0C0u) 1427 /** Peripheral GPIOD base pointer */ 1428 #define GPIOD ((GPIO_Type *)GPIOD_BASE) 1429 /** Peripheral GPIOE base address */ 1430 #define GPIOE_BASE (0x400FF100u) 1431 /** Peripheral GPIOE base pointer */ 1432 #define GPIOE ((GPIO_Type *)GPIOE_BASE) 1433 /** Array initializer of GPIO peripheral base addresses */ 1434 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } 1435 /** Array initializer of GPIO peripheral base pointers */ 1436 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } 1437 1438 /*! 1439 * @} 1440 */ /* end of group GPIO_Peripheral_Access_Layer */ 1441 1442 1443 /* ---------------------------------------------------------------------------- 1444 -- I2C Peripheral Access Layer 1445 ---------------------------------------------------------------------------- */ 1446 1447 /*! 1448 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 1449 * @{ 1450 */ 1451 1452 /** I2C - Register Layout Typedef */ 1453 typedef struct { 1454 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 1455 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 1456 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 1457 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 1458 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 1459 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 1460 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 1461 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 1462 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 1463 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 1464 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 1465 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 1466 } I2C_Type; 1467 1468 /* ---------------------------------------------------------------------------- 1469 -- I2C Register Masks 1470 ---------------------------------------------------------------------------- */ 1471 1472 /*! 1473 * @addtogroup I2C_Register_Masks I2C Register Masks 1474 * @{ 1475 */ 1476 1477 /*! @name A1 - I2C Address Register 1 */ 1478 #define I2C_A1_AD_MASK (0xFEU) 1479 #define I2C_A1_AD_SHIFT (1U) 1480 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 1481 1482 /*! @name F - I2C Frequency Divider register */ 1483 #define I2C_F_ICR_MASK (0x3FU) 1484 #define I2C_F_ICR_SHIFT (0U) 1485 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 1486 #define I2C_F_MULT_MASK (0xC0U) 1487 #define I2C_F_MULT_SHIFT (6U) 1488 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 1489 1490 /*! @name C1 - I2C Control Register 1 */ 1491 #define I2C_C1_DMAEN_MASK (0x1U) 1492 #define I2C_C1_DMAEN_SHIFT (0U) 1493 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) 1494 #define I2C_C1_WUEN_MASK (0x2U) 1495 #define I2C_C1_WUEN_SHIFT (1U) 1496 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 1497 #define I2C_C1_RSTA_MASK (0x4U) 1498 #define I2C_C1_RSTA_SHIFT (2U) 1499 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 1500 #define I2C_C1_TXAK_MASK (0x8U) 1501 #define I2C_C1_TXAK_SHIFT (3U) 1502 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 1503 #define I2C_C1_TX_MASK (0x10U) 1504 #define I2C_C1_TX_SHIFT (4U) 1505 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 1506 #define I2C_C1_MST_MASK (0x20U) 1507 #define I2C_C1_MST_SHIFT (5U) 1508 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 1509 #define I2C_C1_IICIE_MASK (0x40U) 1510 #define I2C_C1_IICIE_SHIFT (6U) 1511 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 1512 #define I2C_C1_IICEN_MASK (0x80U) 1513 #define I2C_C1_IICEN_SHIFT (7U) 1514 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 1515 1516 /*! @name S - I2C Status register */ 1517 #define I2C_S_RXAK_MASK (0x1U) 1518 #define I2C_S_RXAK_SHIFT (0U) 1519 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 1520 #define I2C_S_IICIF_MASK (0x2U) 1521 #define I2C_S_IICIF_SHIFT (1U) 1522 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 1523 #define I2C_S_SRW_MASK (0x4U) 1524 #define I2C_S_SRW_SHIFT (2U) 1525 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 1526 #define I2C_S_RAM_MASK (0x8U) 1527 #define I2C_S_RAM_SHIFT (3U) 1528 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 1529 #define I2C_S_ARBL_MASK (0x10U) 1530 #define I2C_S_ARBL_SHIFT (4U) 1531 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 1532 #define I2C_S_BUSY_MASK (0x20U) 1533 #define I2C_S_BUSY_SHIFT (5U) 1534 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 1535 #define I2C_S_IAAS_MASK (0x40U) 1536 #define I2C_S_IAAS_SHIFT (6U) 1537 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 1538 #define I2C_S_TCF_MASK (0x80U) 1539 #define I2C_S_TCF_SHIFT (7U) 1540 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 1541 1542 /*! @name D - I2C Data I/O register */ 1543 #define I2C_D_DATA_MASK (0xFFU) 1544 #define I2C_D_DATA_SHIFT (0U) 1545 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 1546 1547 /*! @name C2 - I2C Control Register 2 */ 1548 #define I2C_C2_AD_MASK (0x7U) 1549 #define I2C_C2_AD_SHIFT (0U) 1550 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 1551 #define I2C_C2_RMEN_MASK (0x8U) 1552 #define I2C_C2_RMEN_SHIFT (3U) 1553 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 1554 #define I2C_C2_SBRC_MASK (0x10U) 1555 #define I2C_C2_SBRC_SHIFT (4U) 1556 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 1557 #define I2C_C2_HDRS_MASK (0x20U) 1558 #define I2C_C2_HDRS_SHIFT (5U) 1559 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) 1560 #define I2C_C2_ADEXT_MASK (0x40U) 1561 #define I2C_C2_ADEXT_SHIFT (6U) 1562 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 1563 #define I2C_C2_GCAEN_MASK (0x80U) 1564 #define I2C_C2_GCAEN_SHIFT (7U) 1565 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 1566 1567 /*! @name FLT - I2C Programmable Input Glitch Filter register */ 1568 #define I2C_FLT_FLT_MASK (0x1FU) 1569 #define I2C_FLT_FLT_SHIFT (0U) 1570 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 1571 #define I2C_FLT_STOPIE_MASK (0x20U) 1572 #define I2C_FLT_STOPIE_SHIFT (5U) 1573 #define I2C_FLT_STOPIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPIE_SHIFT)) & I2C_FLT_STOPIE_MASK) 1574 #define I2C_FLT_STOPF_MASK (0x40U) 1575 #define I2C_FLT_STOPF_SHIFT (6U) 1576 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 1577 #define I2C_FLT_SHEN_MASK (0x80U) 1578 #define I2C_FLT_SHEN_SHIFT (7U) 1579 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 1580 1581 /*! @name RA - I2C Range Address register */ 1582 #define I2C_RA_RAD_MASK (0xFEU) 1583 #define I2C_RA_RAD_SHIFT (1U) 1584 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 1585 1586 /*! @name SMB - I2C SMBus Control and Status register */ 1587 #define I2C_SMB_SHTF2IE_MASK (0x1U) 1588 #define I2C_SMB_SHTF2IE_SHIFT (0U) 1589 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 1590 #define I2C_SMB_SHTF2_MASK (0x2U) 1591 #define I2C_SMB_SHTF2_SHIFT (1U) 1592 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 1593 #define I2C_SMB_SHTF1_MASK (0x4U) 1594 #define I2C_SMB_SHTF1_SHIFT (2U) 1595 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 1596 #define I2C_SMB_SLTF_MASK (0x8U) 1597 #define I2C_SMB_SLTF_SHIFT (3U) 1598 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 1599 #define I2C_SMB_TCKSEL_MASK (0x10U) 1600 #define I2C_SMB_TCKSEL_SHIFT (4U) 1601 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 1602 #define I2C_SMB_SIICAEN_MASK (0x20U) 1603 #define I2C_SMB_SIICAEN_SHIFT (5U) 1604 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 1605 #define I2C_SMB_ALERTEN_MASK (0x40U) 1606 #define I2C_SMB_ALERTEN_SHIFT (6U) 1607 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 1608 #define I2C_SMB_FACK_MASK (0x80U) 1609 #define I2C_SMB_FACK_SHIFT (7U) 1610 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 1611 1612 /*! @name A2 - I2C Address Register 2 */ 1613 #define I2C_A2_SAD_MASK (0xFEU) 1614 #define I2C_A2_SAD_SHIFT (1U) 1615 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 1616 1617 /*! @name SLTH - I2C SCL Low Timeout Register High */ 1618 #define I2C_SLTH_SSLT_MASK (0xFFU) 1619 #define I2C_SLTH_SSLT_SHIFT (0U) 1620 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 1621 1622 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 1623 #define I2C_SLTL_SSLT_MASK (0xFFU) 1624 #define I2C_SLTL_SSLT_SHIFT (0U) 1625 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 1626 1627 1628 /*! 1629 * @} 1630 */ /* end of group I2C_Register_Masks */ 1631 1632 1633 /* I2C - Peripheral instance base addresses */ 1634 /** Peripheral I2C0 base address */ 1635 #define I2C0_BASE (0x40066000u) 1636 /** Peripheral I2C0 base pointer */ 1637 #define I2C0 ((I2C_Type *)I2C0_BASE) 1638 /** Peripheral I2C1 base address */ 1639 #define I2C1_BASE (0x40067000u) 1640 /** Peripheral I2C1 base pointer */ 1641 #define I2C1 ((I2C_Type *)I2C1_BASE) 1642 /** Array initializer of I2C peripheral base addresses */ 1643 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } 1644 /** Array initializer of I2C peripheral base pointers */ 1645 #define I2C_BASE_PTRS { I2C0, I2C1 } 1646 /** Interrupt vectors for the I2C peripheral type */ 1647 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } 1648 1649 /*! 1650 * @} 1651 */ /* end of group I2C_Peripheral_Access_Layer */ 1652 1653 1654 /* ---------------------------------------------------------------------------- 1655 -- LLWU Peripheral Access Layer 1656 ---------------------------------------------------------------------------- */ 1657 1658 /*! 1659 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 1660 * @{ 1661 */ 1662 1663 /** LLWU - Register Layout Typedef */ 1664 typedef struct { 1665 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 1666 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 1667 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 1668 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 1669 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 1670 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 1671 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 1672 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 1673 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 1674 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 1675 } LLWU_Type; 1676 1677 /* ---------------------------------------------------------------------------- 1678 -- LLWU Register Masks 1679 ---------------------------------------------------------------------------- */ 1680 1681 /*! 1682 * @addtogroup LLWU_Register_Masks LLWU Register Masks 1683 * @{ 1684 */ 1685 1686 /*! @name PE1 - LLWU Pin Enable 1 register */ 1687 #define LLWU_PE1_WUPE0_MASK (0x3U) 1688 #define LLWU_PE1_WUPE0_SHIFT (0U) 1689 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) 1690 #define LLWU_PE1_WUPE1_MASK (0xCU) 1691 #define LLWU_PE1_WUPE1_SHIFT (2U) 1692 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) 1693 #define LLWU_PE1_WUPE2_MASK (0x30U) 1694 #define LLWU_PE1_WUPE2_SHIFT (4U) 1695 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) 1696 #define LLWU_PE1_WUPE3_MASK (0xC0U) 1697 #define LLWU_PE1_WUPE3_SHIFT (6U) 1698 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) 1699 1700 /*! @name PE2 - LLWU Pin Enable 2 register */ 1701 #define LLWU_PE2_WUPE4_MASK (0x3U) 1702 #define LLWU_PE2_WUPE4_SHIFT (0U) 1703 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) 1704 #define LLWU_PE2_WUPE5_MASK (0xCU) 1705 #define LLWU_PE2_WUPE5_SHIFT (2U) 1706 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) 1707 #define LLWU_PE2_WUPE6_MASK (0x30U) 1708 #define LLWU_PE2_WUPE6_SHIFT (4U) 1709 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) 1710 #define LLWU_PE2_WUPE7_MASK (0xC0U) 1711 #define LLWU_PE2_WUPE7_SHIFT (6U) 1712 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) 1713 1714 /*! @name PE3 - LLWU Pin Enable 3 register */ 1715 #define LLWU_PE3_WUPE8_MASK (0x3U) 1716 #define LLWU_PE3_WUPE8_SHIFT (0U) 1717 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) 1718 #define LLWU_PE3_WUPE9_MASK (0xCU) 1719 #define LLWU_PE3_WUPE9_SHIFT (2U) 1720 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) 1721 #define LLWU_PE3_WUPE10_MASK (0x30U) 1722 #define LLWU_PE3_WUPE10_SHIFT (4U) 1723 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) 1724 #define LLWU_PE3_WUPE11_MASK (0xC0U) 1725 #define LLWU_PE3_WUPE11_SHIFT (6U) 1726 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) 1727 1728 /*! @name PE4 - LLWU Pin Enable 4 register */ 1729 #define LLWU_PE4_WUPE12_MASK (0x3U) 1730 #define LLWU_PE4_WUPE12_SHIFT (0U) 1731 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) 1732 #define LLWU_PE4_WUPE13_MASK (0xCU) 1733 #define LLWU_PE4_WUPE13_SHIFT (2U) 1734 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) 1735 #define LLWU_PE4_WUPE14_MASK (0x30U) 1736 #define LLWU_PE4_WUPE14_SHIFT (4U) 1737 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) 1738 #define LLWU_PE4_WUPE15_MASK (0xC0U) 1739 #define LLWU_PE4_WUPE15_SHIFT (6U) 1740 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) 1741 1742 /*! @name ME - LLWU Module Enable register */ 1743 #define LLWU_ME_WUME0_MASK (0x1U) 1744 #define LLWU_ME_WUME0_SHIFT (0U) 1745 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) 1746 #define LLWU_ME_WUME1_MASK (0x2U) 1747 #define LLWU_ME_WUME1_SHIFT (1U) 1748 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) 1749 #define LLWU_ME_WUME2_MASK (0x4U) 1750 #define LLWU_ME_WUME2_SHIFT (2U) 1751 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) 1752 #define LLWU_ME_WUME3_MASK (0x8U) 1753 #define LLWU_ME_WUME3_SHIFT (3U) 1754 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) 1755 #define LLWU_ME_WUME4_MASK (0x10U) 1756 #define LLWU_ME_WUME4_SHIFT (4U) 1757 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) 1758 #define LLWU_ME_WUME5_MASK (0x20U) 1759 #define LLWU_ME_WUME5_SHIFT (5U) 1760 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) 1761 #define LLWU_ME_WUME6_MASK (0x40U) 1762 #define LLWU_ME_WUME6_SHIFT (6U) 1763 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) 1764 #define LLWU_ME_WUME7_MASK (0x80U) 1765 #define LLWU_ME_WUME7_SHIFT (7U) 1766 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) 1767 1768 /*! @name F1 - LLWU Flag 1 register */ 1769 #define LLWU_F1_WUF0_MASK (0x1U) 1770 #define LLWU_F1_WUF0_SHIFT (0U) 1771 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) 1772 #define LLWU_F1_WUF1_MASK (0x2U) 1773 #define LLWU_F1_WUF1_SHIFT (1U) 1774 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) 1775 #define LLWU_F1_WUF2_MASK (0x4U) 1776 #define LLWU_F1_WUF2_SHIFT (2U) 1777 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) 1778 #define LLWU_F1_WUF3_MASK (0x8U) 1779 #define LLWU_F1_WUF3_SHIFT (3U) 1780 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) 1781 #define LLWU_F1_WUF4_MASK (0x10U) 1782 #define LLWU_F1_WUF4_SHIFT (4U) 1783 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) 1784 #define LLWU_F1_WUF5_MASK (0x20U) 1785 #define LLWU_F1_WUF5_SHIFT (5U) 1786 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) 1787 #define LLWU_F1_WUF6_MASK (0x40U) 1788 #define LLWU_F1_WUF6_SHIFT (6U) 1789 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) 1790 #define LLWU_F1_WUF7_MASK (0x80U) 1791 #define LLWU_F1_WUF7_SHIFT (7U) 1792 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) 1793 1794 /*! @name F2 - LLWU Flag 2 register */ 1795 #define LLWU_F2_WUF8_MASK (0x1U) 1796 #define LLWU_F2_WUF8_SHIFT (0U) 1797 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) 1798 #define LLWU_F2_WUF9_MASK (0x2U) 1799 #define LLWU_F2_WUF9_SHIFT (1U) 1800 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) 1801 #define LLWU_F2_WUF10_MASK (0x4U) 1802 #define LLWU_F2_WUF10_SHIFT (2U) 1803 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) 1804 #define LLWU_F2_WUF11_MASK (0x8U) 1805 #define LLWU_F2_WUF11_SHIFT (3U) 1806 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) 1807 #define LLWU_F2_WUF12_MASK (0x10U) 1808 #define LLWU_F2_WUF12_SHIFT (4U) 1809 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) 1810 #define LLWU_F2_WUF13_MASK (0x20U) 1811 #define LLWU_F2_WUF13_SHIFT (5U) 1812 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) 1813 #define LLWU_F2_WUF14_MASK (0x40U) 1814 #define LLWU_F2_WUF14_SHIFT (6U) 1815 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) 1816 #define LLWU_F2_WUF15_MASK (0x80U) 1817 #define LLWU_F2_WUF15_SHIFT (7U) 1818 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) 1819 1820 /*! @name F3 - LLWU Flag 3 register */ 1821 #define LLWU_F3_MWUF0_MASK (0x1U) 1822 #define LLWU_F3_MWUF0_SHIFT (0U) 1823 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) 1824 #define LLWU_F3_MWUF1_MASK (0x2U) 1825 #define LLWU_F3_MWUF1_SHIFT (1U) 1826 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) 1827 #define LLWU_F3_MWUF2_MASK (0x4U) 1828 #define LLWU_F3_MWUF2_SHIFT (2U) 1829 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) 1830 #define LLWU_F3_MWUF3_MASK (0x8U) 1831 #define LLWU_F3_MWUF3_SHIFT (3U) 1832 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) 1833 #define LLWU_F3_MWUF4_MASK (0x10U) 1834 #define LLWU_F3_MWUF4_SHIFT (4U) 1835 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) 1836 #define LLWU_F3_MWUF5_MASK (0x20U) 1837 #define LLWU_F3_MWUF5_SHIFT (5U) 1838 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) 1839 #define LLWU_F3_MWUF6_MASK (0x40U) 1840 #define LLWU_F3_MWUF6_SHIFT (6U) 1841 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) 1842 #define LLWU_F3_MWUF7_MASK (0x80U) 1843 #define LLWU_F3_MWUF7_SHIFT (7U) 1844 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) 1845 1846 /*! @name FILT1 - LLWU Pin Filter 1 register */ 1847 #define LLWU_FILT1_FILTSEL_MASK (0xFU) 1848 #define LLWU_FILT1_FILTSEL_SHIFT (0U) 1849 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) 1850 #define LLWU_FILT1_FILTE_MASK (0x60U) 1851 #define LLWU_FILT1_FILTE_SHIFT (5U) 1852 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) 1853 #define LLWU_FILT1_FILTF_MASK (0x80U) 1854 #define LLWU_FILT1_FILTF_SHIFT (7U) 1855 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) 1856 1857 /*! @name FILT2 - LLWU Pin Filter 2 register */ 1858 #define LLWU_FILT2_FILTSEL_MASK (0xFU) 1859 #define LLWU_FILT2_FILTSEL_SHIFT (0U) 1860 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) 1861 #define LLWU_FILT2_FILTE_MASK (0x60U) 1862 #define LLWU_FILT2_FILTE_SHIFT (5U) 1863 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) 1864 #define LLWU_FILT2_FILTF_MASK (0x80U) 1865 #define LLWU_FILT2_FILTF_SHIFT (7U) 1866 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) 1867 1868 1869 /*! 1870 * @} 1871 */ /* end of group LLWU_Register_Masks */ 1872 1873 1874 /* LLWU - Peripheral instance base addresses */ 1875 /** Peripheral LLWU base address */ 1876 #define LLWU_BASE (0x4007C000u) 1877 /** Peripheral LLWU base pointer */ 1878 #define LLWU ((LLWU_Type *)LLWU_BASE) 1879 /** Array initializer of LLWU peripheral base addresses */ 1880 #define LLWU_BASE_ADDRS { LLWU_BASE } 1881 /** Array initializer of LLWU peripheral base pointers */ 1882 #define LLWU_BASE_PTRS { LLWU } 1883 /** Interrupt vectors for the LLWU peripheral type */ 1884 #define LLWU_IRQS { LLWU_IRQn } 1885 1886 /*! 1887 * @} 1888 */ /* end of group LLWU_Peripheral_Access_Layer */ 1889 1890 1891 /* ---------------------------------------------------------------------------- 1892 -- LPTMR Peripheral Access Layer 1893 ---------------------------------------------------------------------------- */ 1894 1895 /*! 1896 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 1897 * @{ 1898 */ 1899 1900 /** LPTMR - Register Layout Typedef */ 1901 typedef struct { 1902 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 1903 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 1904 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 1905 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 1906 } LPTMR_Type; 1907 1908 /* ---------------------------------------------------------------------------- 1909 -- LPTMR Register Masks 1910 ---------------------------------------------------------------------------- */ 1911 1912 /*! 1913 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 1914 * @{ 1915 */ 1916 1917 /*! @name CSR - Low Power Timer Control Status Register */ 1918 #define LPTMR_CSR_TEN_MASK (0x1U) 1919 #define LPTMR_CSR_TEN_SHIFT (0U) 1920 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 1921 #define LPTMR_CSR_TMS_MASK (0x2U) 1922 #define LPTMR_CSR_TMS_SHIFT (1U) 1923 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 1924 #define LPTMR_CSR_TFC_MASK (0x4U) 1925 #define LPTMR_CSR_TFC_SHIFT (2U) 1926 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 1927 #define LPTMR_CSR_TPP_MASK (0x8U) 1928 #define LPTMR_CSR_TPP_SHIFT (3U) 1929 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 1930 #define LPTMR_CSR_TPS_MASK (0x30U) 1931 #define LPTMR_CSR_TPS_SHIFT (4U) 1932 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 1933 #define LPTMR_CSR_TIE_MASK (0x40U) 1934 #define LPTMR_CSR_TIE_SHIFT (6U) 1935 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 1936 #define LPTMR_CSR_TCF_MASK (0x80U) 1937 #define LPTMR_CSR_TCF_SHIFT (7U) 1938 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 1939 1940 /*! @name PSR - Low Power Timer Prescale Register */ 1941 #define LPTMR_PSR_PCS_MASK (0x3U) 1942 #define LPTMR_PSR_PCS_SHIFT (0U) 1943 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 1944 #define LPTMR_PSR_PBYP_MASK (0x4U) 1945 #define LPTMR_PSR_PBYP_SHIFT (2U) 1946 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 1947 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 1948 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 1949 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 1950 1951 /*! @name CMR - Low Power Timer Compare Register */ 1952 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 1953 #define LPTMR_CMR_COMPARE_SHIFT (0U) 1954 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 1955 1956 /*! @name CNR - Low Power Timer Counter Register */ 1957 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 1958 #define LPTMR_CNR_COUNTER_SHIFT (0U) 1959 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 1960 1961 1962 /*! 1963 * @} 1964 */ /* end of group LPTMR_Register_Masks */ 1965 1966 1967 /* LPTMR - Peripheral instance base addresses */ 1968 /** Peripheral LPTMR0 base address */ 1969 #define LPTMR0_BASE (0x40040000u) 1970 /** Peripheral LPTMR0 base pointer */ 1971 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 1972 /** Array initializer of LPTMR peripheral base addresses */ 1973 #define LPTMR_BASE_ADDRS { LPTMR0_BASE } 1974 /** Array initializer of LPTMR peripheral base pointers */ 1975 #define LPTMR_BASE_PTRS { LPTMR0 } 1976 /** Interrupt vectors for the LPTMR peripheral type */ 1977 #define LPTMR_IRQS { LPTMR0_IRQn } 1978 1979 /*! 1980 * @} 1981 */ /* end of group LPTMR_Peripheral_Access_Layer */ 1982 1983 1984 /* ---------------------------------------------------------------------------- 1985 -- MCG Peripheral Access Layer 1986 ---------------------------------------------------------------------------- */ 1987 1988 /*! 1989 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 1990 * @{ 1991 */ 1992 1993 /** MCG - Register Layout Typedef */ 1994 typedef struct { 1995 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 1996 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 1997 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 1998 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 1999 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 2000 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 2001 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ 2002 uint8_t RESERVED_0[1]; 2003 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 2004 uint8_t RESERVED_1[1]; 2005 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 2006 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 2007 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 2008 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 2009 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */ 2010 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */ 2011 } MCG_Type; 2012 2013 /* ---------------------------------------------------------------------------- 2014 -- MCG Register Masks 2015 ---------------------------------------------------------------------------- */ 2016 2017 /*! 2018 * @addtogroup MCG_Register_Masks MCG Register Masks 2019 * @{ 2020 */ 2021 2022 /*! @name C1 - MCG Control 1 Register */ 2023 #define MCG_C1_IREFSTEN_MASK (0x1U) 2024 #define MCG_C1_IREFSTEN_SHIFT (0U) 2025 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) 2026 #define MCG_C1_IRCLKEN_MASK (0x2U) 2027 #define MCG_C1_IRCLKEN_SHIFT (1U) 2028 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) 2029 #define MCG_C1_IREFS_MASK (0x4U) 2030 #define MCG_C1_IREFS_SHIFT (2U) 2031 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) 2032 #define MCG_C1_FRDIV_MASK (0x38U) 2033 #define MCG_C1_FRDIV_SHIFT (3U) 2034 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) 2035 #define MCG_C1_CLKS_MASK (0xC0U) 2036 #define MCG_C1_CLKS_SHIFT (6U) 2037 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) 2038 2039 /*! @name C2 - MCG Control 2 Register */ 2040 #define MCG_C2_IRCS_MASK (0x1U) 2041 #define MCG_C2_IRCS_SHIFT (0U) 2042 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) 2043 #define MCG_C2_LP_MASK (0x2U) 2044 #define MCG_C2_LP_SHIFT (1U) 2045 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) 2046 #define MCG_C2_EREFS0_MASK (0x4U) 2047 #define MCG_C2_EREFS0_SHIFT (2U) 2048 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) 2049 #define MCG_C2_HGO0_MASK (0x8U) 2050 #define MCG_C2_HGO0_SHIFT (3U) 2051 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) 2052 #define MCG_C2_RANGE0_MASK (0x30U) 2053 #define MCG_C2_RANGE0_SHIFT (4U) 2054 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) 2055 #define MCG_C2_LOCRE0_MASK (0x80U) 2056 #define MCG_C2_LOCRE0_SHIFT (7U) 2057 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) 2058 2059 /*! @name C3 - MCG Control 3 Register */ 2060 #define MCG_C3_SCTRIM_MASK (0xFFU) 2061 #define MCG_C3_SCTRIM_SHIFT (0U) 2062 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) 2063 2064 /*! @name C4 - MCG Control 4 Register */ 2065 #define MCG_C4_SCFTRIM_MASK (0x1U) 2066 #define MCG_C4_SCFTRIM_SHIFT (0U) 2067 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) 2068 #define MCG_C4_FCTRIM_MASK (0x1EU) 2069 #define MCG_C4_FCTRIM_SHIFT (1U) 2070 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) 2071 #define MCG_C4_DRST_DRS_MASK (0x60U) 2072 #define MCG_C4_DRST_DRS_SHIFT (5U) 2073 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) 2074 #define MCG_C4_DMX32_MASK (0x80U) 2075 #define MCG_C4_DMX32_SHIFT (7U) 2076 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) 2077 2078 /*! @name C5 - MCG Control 5 Register */ 2079 #define MCG_C5_PRDIV0_MASK (0x1FU) 2080 #define MCG_C5_PRDIV0_SHIFT (0U) 2081 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) 2082 #define MCG_C5_PLLSTEN0_MASK (0x20U) 2083 #define MCG_C5_PLLSTEN0_SHIFT (5U) 2084 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) 2085 #define MCG_C5_PLLCLKEN0_MASK (0x40U) 2086 #define MCG_C5_PLLCLKEN0_SHIFT (6U) 2087 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) 2088 2089 /*! @name C6 - MCG Control 6 Register */ 2090 #define MCG_C6_VDIV0_MASK (0x1FU) 2091 #define MCG_C6_VDIV0_SHIFT (0U) 2092 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) 2093 #define MCG_C6_CME0_MASK (0x20U) 2094 #define MCG_C6_CME0_SHIFT (5U) 2095 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) 2096 #define MCG_C6_PLLS_MASK (0x40U) 2097 #define MCG_C6_PLLS_SHIFT (6U) 2098 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) 2099 #define MCG_C6_LOLIE0_MASK (0x80U) 2100 #define MCG_C6_LOLIE0_SHIFT (7U) 2101 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) 2102 2103 /*! @name S - MCG Status Register */ 2104 #define MCG_S_IRCST_MASK (0x1U) 2105 #define MCG_S_IRCST_SHIFT (0U) 2106 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) 2107 #define MCG_S_OSCINIT0_MASK (0x2U) 2108 #define MCG_S_OSCINIT0_SHIFT (1U) 2109 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) 2110 #define MCG_S_CLKST_MASK (0xCU) 2111 #define MCG_S_CLKST_SHIFT (2U) 2112 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) 2113 #define MCG_S_IREFST_MASK (0x10U) 2114 #define MCG_S_IREFST_SHIFT (4U) 2115 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) 2116 #define MCG_S_PLLST_MASK (0x20U) 2117 #define MCG_S_PLLST_SHIFT (5U) 2118 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) 2119 #define MCG_S_LOCK0_MASK (0x40U) 2120 #define MCG_S_LOCK0_SHIFT (6U) 2121 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) 2122 #define MCG_S_LOLS0_MASK (0x80U) 2123 #define MCG_S_LOLS0_SHIFT (7U) 2124 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) 2125 2126 /*! @name SC - MCG Status and Control Register */ 2127 #define MCG_SC_LOCS0_MASK (0x1U) 2128 #define MCG_SC_LOCS0_SHIFT (0U) 2129 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) 2130 #define MCG_SC_FCRDIV_MASK (0xEU) 2131 #define MCG_SC_FCRDIV_SHIFT (1U) 2132 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) 2133 #define MCG_SC_FLTPRSRV_MASK (0x10U) 2134 #define MCG_SC_FLTPRSRV_SHIFT (4U) 2135 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) 2136 #define MCG_SC_ATMF_MASK (0x20U) 2137 #define MCG_SC_ATMF_SHIFT (5U) 2138 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) 2139 #define MCG_SC_ATMS_MASK (0x40U) 2140 #define MCG_SC_ATMS_SHIFT (6U) 2141 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) 2142 #define MCG_SC_ATME_MASK (0x80U) 2143 #define MCG_SC_ATME_SHIFT (7U) 2144 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) 2145 2146 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ 2147 #define MCG_ATCVH_ATCVH_MASK (0xFFU) 2148 #define MCG_ATCVH_ATCVH_SHIFT (0U) 2149 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) 2150 2151 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ 2152 #define MCG_ATCVL_ATCVL_MASK (0xFFU) 2153 #define MCG_ATCVL_ATCVL_SHIFT (0U) 2154 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) 2155 2156 /*! @name C8 - MCG Control 8 Register */ 2157 #define MCG_C8_LOLRE_MASK (0x40U) 2158 #define MCG_C8_LOLRE_SHIFT (6U) 2159 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) 2160 2161 2162 /*! 2163 * @} 2164 */ /* end of group MCG_Register_Masks */ 2165 2166 2167 /* MCG - Peripheral instance base addresses */ 2168 /** Peripheral MCG base address */ 2169 #define MCG_BASE (0x40064000u) 2170 /** Peripheral MCG base pointer */ 2171 #define MCG ((MCG_Type *)MCG_BASE) 2172 /** Array initializer of MCG peripheral base addresses */ 2173 #define MCG_BASE_ADDRS { MCG_BASE } 2174 /** Array initializer of MCG peripheral base pointers */ 2175 #define MCG_BASE_PTRS { MCG } 2176 /** Interrupt vectors for the MCG peripheral type */ 2177 #define MCG_IRQS { MCG_IRQn } 2178 /* MCG C2[EREFS] backward compatibility */ 2179 #define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK) 2180 #define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT) 2181 #define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH) 2182 #define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x)) 2183 2184 /* MCG C2[HGO] backward compatibility */ 2185 #define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK) 2186 #define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT) 2187 #define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH) 2188 #define MCG_C2_HGO(x) (MCG_C2_HGO0(x)) 2189 2190 /* MCG C2[RANGE] backward compatibility */ 2191 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK) 2192 #define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT) 2193 #define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH) 2194 #define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x)) 2195 2196 2197 /*! 2198 * @} 2199 */ /* end of group MCG_Peripheral_Access_Layer */ 2200 2201 2202 /* ---------------------------------------------------------------------------- 2203 -- MCM Peripheral Access Layer 2204 ---------------------------------------------------------------------------- */ 2205 2206 /*! 2207 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 2208 * @{ 2209 */ 2210 2211 /** MCM - Register Layout Typedef */ 2212 typedef struct { 2213 uint8_t RESERVED_0[8]; 2214 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 2215 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 2216 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 2217 uint8_t RESERVED_1[48]; 2218 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 2219 } MCM_Type; 2220 2221 /* ---------------------------------------------------------------------------- 2222 -- MCM Register Masks 2223 ---------------------------------------------------------------------------- */ 2224 2225 /*! 2226 * @addtogroup MCM_Register_Masks MCM Register Masks 2227 * @{ 2228 */ 2229 2230 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 2231 #define MCM_PLASC_ASC_MASK (0xFFU) 2232 #define MCM_PLASC_ASC_SHIFT (0U) 2233 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 2234 2235 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 2236 #define MCM_PLAMC_AMC_MASK (0xFFU) 2237 #define MCM_PLAMC_AMC_SHIFT (0U) 2238 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 2239 2240 /*! @name PLACR - Platform Control Register */ 2241 #define MCM_PLACR_ARB_MASK (0x200U) 2242 #define MCM_PLACR_ARB_SHIFT (9U) 2243 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) 2244 #define MCM_PLACR_CFCC_MASK (0x400U) 2245 #define MCM_PLACR_CFCC_SHIFT (10U) 2246 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 2247 #define MCM_PLACR_DFCDA_MASK (0x800U) 2248 #define MCM_PLACR_DFCDA_SHIFT (11U) 2249 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 2250 #define MCM_PLACR_DFCIC_MASK (0x1000U) 2251 #define MCM_PLACR_DFCIC_SHIFT (12U) 2252 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 2253 #define MCM_PLACR_DFCC_MASK (0x2000U) 2254 #define MCM_PLACR_DFCC_SHIFT (13U) 2255 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 2256 #define MCM_PLACR_EFDS_MASK (0x4000U) 2257 #define MCM_PLACR_EFDS_SHIFT (14U) 2258 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 2259 #define MCM_PLACR_DFCS_MASK (0x8000U) 2260 #define MCM_PLACR_DFCS_SHIFT (15U) 2261 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 2262 #define MCM_PLACR_ESFC_MASK (0x10000U) 2263 #define MCM_PLACR_ESFC_SHIFT (16U) 2264 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 2265 2266 /*! @name CPO - Compute Operation Control Register */ 2267 #define MCM_CPO_CPOREQ_MASK (0x1U) 2268 #define MCM_CPO_CPOREQ_SHIFT (0U) 2269 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 2270 #define MCM_CPO_CPOACK_MASK (0x2U) 2271 #define MCM_CPO_CPOACK_SHIFT (1U) 2272 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 2273 #define MCM_CPO_CPOWOI_MASK (0x4U) 2274 #define MCM_CPO_CPOWOI_SHIFT (2U) 2275 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 2276 2277 2278 /*! 2279 * @} 2280 */ /* end of group MCM_Register_Masks */ 2281 2282 2283 /* MCM - Peripheral instance base addresses */ 2284 /** Peripheral MCM base address */ 2285 #define MCM_BASE (0xF0003000u) 2286 /** Peripheral MCM base pointer */ 2287 #define MCM ((MCM_Type *)MCM_BASE) 2288 /** Array initializer of MCM peripheral base addresses */ 2289 #define MCM_BASE_ADDRS { MCM_BASE } 2290 /** Array initializer of MCM peripheral base pointers */ 2291 #define MCM_BASE_PTRS { MCM } 2292 2293 /*! 2294 * @} 2295 */ /* end of group MCM_Peripheral_Access_Layer */ 2296 2297 2298 /* ---------------------------------------------------------------------------- 2299 -- MTB Peripheral Access Layer 2300 ---------------------------------------------------------------------------- */ 2301 2302 /*! 2303 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 2304 * @{ 2305 */ 2306 2307 /** MTB - Register Layout Typedef */ 2308 typedef struct { 2309 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 2310 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 2311 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 2312 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 2313 uint8_t RESERVED_0[3824]; 2314 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 2315 uint8_t RESERVED_1[156]; 2316 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 2317 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 2318 uint8_t RESERVED_2[8]; 2319 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 2320 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 2321 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 2322 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 2323 uint8_t RESERVED_3[8]; 2324 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 2325 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 2326 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 2327 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 2328 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 2329 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 2330 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 2331 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 2332 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 2333 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 2334 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 2335 } MTB_Type; 2336 2337 /* ---------------------------------------------------------------------------- 2338 -- MTB Register Masks 2339 ---------------------------------------------------------------------------- */ 2340 2341 /*! 2342 * @addtogroup MTB_Register_Masks MTB Register Masks 2343 * @{ 2344 */ 2345 2346 /*! @name POSITION - MTB Position Register */ 2347 #define MTB_POSITION_WRAP_MASK (0x4U) 2348 #define MTB_POSITION_WRAP_SHIFT (2U) 2349 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) 2350 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) 2351 #define MTB_POSITION_POINTER_SHIFT (3U) 2352 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) 2353 2354 /*! @name MASTER - MTB Master Register */ 2355 #define MTB_MASTER_MASK_MASK (0x1FU) 2356 #define MTB_MASTER_MASK_SHIFT (0U) 2357 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) 2358 #define MTB_MASTER_TSTARTEN_MASK (0x20U) 2359 #define MTB_MASTER_TSTARTEN_SHIFT (5U) 2360 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) 2361 #define MTB_MASTER_TSTOPEN_MASK (0x40U) 2362 #define MTB_MASTER_TSTOPEN_SHIFT (6U) 2363 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) 2364 #define MTB_MASTER_SFRWPRIV_MASK (0x80U) 2365 #define MTB_MASTER_SFRWPRIV_SHIFT (7U) 2366 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) 2367 #define MTB_MASTER_RAMPRIV_MASK (0x100U) 2368 #define MTB_MASTER_RAMPRIV_SHIFT (8U) 2369 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) 2370 #define MTB_MASTER_HALTREQ_MASK (0x200U) 2371 #define MTB_MASTER_HALTREQ_SHIFT (9U) 2372 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) 2373 #define MTB_MASTER_EN_MASK (0x80000000U) 2374 #define MTB_MASTER_EN_SHIFT (31U) 2375 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) 2376 2377 /*! @name FLOW - MTB Flow Register */ 2378 #define MTB_FLOW_AUTOSTOP_MASK (0x1U) 2379 #define MTB_FLOW_AUTOSTOP_SHIFT (0U) 2380 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) 2381 #define MTB_FLOW_AUTOHALT_MASK (0x2U) 2382 #define MTB_FLOW_AUTOHALT_SHIFT (1U) 2383 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) 2384 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) 2385 #define MTB_FLOW_WATERMARK_SHIFT (3U) 2386 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) 2387 2388 /*! @name BASE - MTB Base Register */ 2389 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) 2390 #define MTB_BASE_BASEADDR_SHIFT (0U) 2391 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) 2392 2393 /*! @name MODECTRL - Integration Mode Control Register */ 2394 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) 2395 #define MTB_MODECTRL_MODECTRL_SHIFT (0U) 2396 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) 2397 2398 /*! @name TAGSET - Claim TAG Set Register */ 2399 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) 2400 #define MTB_TAGSET_TAGSET_SHIFT (0U) 2401 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) 2402 2403 /*! @name TAGCLEAR - Claim TAG Clear Register */ 2404 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) 2405 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) 2406 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) 2407 2408 /*! @name LOCKACCESS - Lock Access Register */ 2409 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) 2410 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) 2411 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) 2412 2413 /*! @name LOCKSTAT - Lock Status Register */ 2414 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) 2415 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) 2416 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) 2417 2418 /*! @name AUTHSTAT - Authentication Status Register */ 2419 #define MTB_AUTHSTAT_BIT0_MASK (0x1U) 2420 #define MTB_AUTHSTAT_BIT0_SHIFT (0U) 2421 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) 2422 #define MTB_AUTHSTAT_BIT1_MASK (0x2U) 2423 #define MTB_AUTHSTAT_BIT1_SHIFT (1U) 2424 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) 2425 #define MTB_AUTHSTAT_BIT2_MASK (0x4U) 2426 #define MTB_AUTHSTAT_BIT2_SHIFT (2U) 2427 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) 2428 #define MTB_AUTHSTAT_BIT3_MASK (0x8U) 2429 #define MTB_AUTHSTAT_BIT3_SHIFT (3U) 2430 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) 2431 2432 /*! @name DEVICEARCH - Device Architecture Register */ 2433 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) 2434 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) 2435 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) 2436 2437 /*! @name DEVICECFG - Device Configuration Register */ 2438 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 2439 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) 2440 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) 2441 2442 /*! @name DEVICETYPID - Device Type Identifier Register */ 2443 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 2444 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) 2445 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) 2446 2447 /*! @name PERIPHID4 - Peripheral ID Register */ 2448 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 2449 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) 2450 #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) 2451 2452 /*! @name PERIPHID5 - Peripheral ID Register */ 2453 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 2454 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) 2455 #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) 2456 2457 /*! @name PERIPHID6 - Peripheral ID Register */ 2458 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 2459 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) 2460 #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) 2461 2462 /*! @name PERIPHID7 - Peripheral ID Register */ 2463 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 2464 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) 2465 #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) 2466 2467 /*! @name PERIPHID0 - Peripheral ID Register */ 2468 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 2469 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) 2470 #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) 2471 2472 /*! @name PERIPHID1 - Peripheral ID Register */ 2473 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 2474 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) 2475 #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) 2476 2477 /*! @name PERIPHID2 - Peripheral ID Register */ 2478 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 2479 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) 2480 #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) 2481 2482 /*! @name PERIPHID3 - Peripheral ID Register */ 2483 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 2484 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) 2485 #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) 2486 2487 /*! @name COMPID - Component ID Register */ 2488 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) 2489 #define MTB_COMPID_COMPID_SHIFT (0U) 2490 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) 2491 2492 /* The count of MTB_COMPID */ 2493 #define MTB_COMPID_COUNT (4U) 2494 2495 2496 /*! 2497 * @} 2498 */ /* end of group MTB_Register_Masks */ 2499 2500 2501 /* MTB - Peripheral instance base addresses */ 2502 /** Peripheral MTB base address */ 2503 #define MTB_BASE (0xF0000000u) 2504 /** Peripheral MTB base pointer */ 2505 #define MTB ((MTB_Type *)MTB_BASE) 2506 /** Array initializer of MTB peripheral base addresses */ 2507 #define MTB_BASE_ADDRS { MTB_BASE } 2508 /** Array initializer of MTB peripheral base pointers */ 2509 #define MTB_BASE_PTRS { MTB } 2510 2511 /*! 2512 * @} 2513 */ /* end of group MTB_Peripheral_Access_Layer */ 2514 2515 2516 /* ---------------------------------------------------------------------------- 2517 -- MTBDWT Peripheral Access Layer 2518 ---------------------------------------------------------------------------- */ 2519 2520 /*! 2521 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 2522 * @{ 2523 */ 2524 2525 /** MTBDWT - Register Layout Typedef */ 2526 typedef struct { 2527 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 2528 uint8_t RESERVED_0[28]; 2529 struct { /* offset: 0x20, array step: 0x10 */ 2530 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 2531 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 2532 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 2533 uint8_t RESERVED_0[4]; 2534 } COMPARATOR[2]; 2535 uint8_t RESERVED_1[448]; 2536 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 2537 uint8_t RESERVED_2[3524]; 2538 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 2539 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 2540 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 2541 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 2542 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 2543 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 2544 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 2545 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 2546 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 2547 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 2548 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 2549 } MTBDWT_Type; 2550 2551 /* ---------------------------------------------------------------------------- 2552 -- MTBDWT Register Masks 2553 ---------------------------------------------------------------------------- */ 2554 2555 /*! 2556 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 2557 * @{ 2558 */ 2559 2560 /*! @name CTRL - MTB DWT Control Register */ 2561 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) 2562 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) 2563 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) 2564 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) 2565 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) 2566 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) 2567 2568 /*! @name COMP - MTB_DWT Comparator Register */ 2569 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) 2570 #define MTBDWT_COMP_COMP_SHIFT (0U) 2571 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) 2572 2573 /* The count of MTBDWT_COMP */ 2574 #define MTBDWT_COMP_COUNT (2U) 2575 2576 /*! @name MASK - MTB_DWT Comparator Mask Register */ 2577 #define MTBDWT_MASK_MASK_MASK (0x1FU) 2578 #define MTBDWT_MASK_MASK_SHIFT (0U) 2579 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) 2580 2581 /* The count of MTBDWT_MASK */ 2582 #define MTBDWT_MASK_COUNT (2U) 2583 2584 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ 2585 #define MTBDWT_FCT_FUNCTION_MASK (0xFU) 2586 #define MTBDWT_FCT_FUNCTION_SHIFT (0U) 2587 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) 2588 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) 2589 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) 2590 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) 2591 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) 2592 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) 2593 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) 2594 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) 2595 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) 2596 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) 2597 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) 2598 #define MTBDWT_FCT_MATCHED_SHIFT (24U) 2599 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) 2600 2601 /* The count of MTBDWT_FCT */ 2602 #define MTBDWT_FCT_COUNT (2U) 2603 2604 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ 2605 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) 2606 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) 2607 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) 2608 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) 2609 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) 2610 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) 2611 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) 2612 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) 2613 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) 2614 2615 /*! @name DEVICECFG - Device Configuration Register */ 2616 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 2617 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) 2618 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) 2619 2620 /*! @name DEVICETYPID - Device Type Identifier Register */ 2621 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 2622 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) 2623 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 2624 2625 /*! @name PERIPHID4 - Peripheral ID Register */ 2626 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 2627 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) 2628 #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) 2629 2630 /*! @name PERIPHID5 - Peripheral ID Register */ 2631 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 2632 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) 2633 #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) 2634 2635 /*! @name PERIPHID6 - Peripheral ID Register */ 2636 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 2637 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) 2638 #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) 2639 2640 /*! @name PERIPHID7 - Peripheral ID Register */ 2641 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 2642 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) 2643 #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) 2644 2645 /*! @name PERIPHID0 - Peripheral ID Register */ 2646 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 2647 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) 2648 #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) 2649 2650 /*! @name PERIPHID1 - Peripheral ID Register */ 2651 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 2652 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) 2653 #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) 2654 2655 /*! @name PERIPHID2 - Peripheral ID Register */ 2656 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 2657 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) 2658 #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) 2659 2660 /*! @name PERIPHID3 - Peripheral ID Register */ 2661 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 2662 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) 2663 #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) 2664 2665 /*! @name COMPID - Component ID Register */ 2666 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) 2667 #define MTBDWT_COMPID_COMPID_SHIFT (0U) 2668 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) 2669 2670 /* The count of MTBDWT_COMPID */ 2671 #define MTBDWT_COMPID_COUNT (4U) 2672 2673 2674 /*! 2675 * @} 2676 */ /* end of group MTBDWT_Register_Masks */ 2677 2678 2679 /* MTBDWT - Peripheral instance base addresses */ 2680 /** Peripheral MTBDWT base address */ 2681 #define MTBDWT_BASE (0xF0001000u) 2682 /** Peripheral MTBDWT base pointer */ 2683 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 2684 /** Array initializer of MTBDWT peripheral base addresses */ 2685 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } 2686 /** Array initializer of MTBDWT peripheral base pointers */ 2687 #define MTBDWT_BASE_PTRS { MTBDWT } 2688 2689 /*! 2690 * @} 2691 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 2692 2693 2694 /* ---------------------------------------------------------------------------- 2695 -- NV Peripheral Access Layer 2696 ---------------------------------------------------------------------------- */ 2697 2698 /*! 2699 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 2700 * @{ 2701 */ 2702 2703 /** NV - Register Layout Typedef */ 2704 typedef struct { 2705 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 2706 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 2707 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 2708 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 2709 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 2710 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 2711 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 2712 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 2713 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 2714 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 2715 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 2716 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 2717 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 2718 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 2719 } NV_Type; 2720 2721 /* ---------------------------------------------------------------------------- 2722 -- NV Register Masks 2723 ---------------------------------------------------------------------------- */ 2724 2725 /*! 2726 * @addtogroup NV_Register_Masks NV Register Masks 2727 * @{ 2728 */ 2729 2730 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ 2731 #define NV_BACKKEY3_KEY_MASK (0xFFU) 2732 #define NV_BACKKEY3_KEY_SHIFT (0U) 2733 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) 2734 2735 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ 2736 #define NV_BACKKEY2_KEY_MASK (0xFFU) 2737 #define NV_BACKKEY2_KEY_SHIFT (0U) 2738 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) 2739 2740 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ 2741 #define NV_BACKKEY1_KEY_MASK (0xFFU) 2742 #define NV_BACKKEY1_KEY_SHIFT (0U) 2743 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) 2744 2745 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ 2746 #define NV_BACKKEY0_KEY_MASK (0xFFU) 2747 #define NV_BACKKEY0_KEY_SHIFT (0U) 2748 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) 2749 2750 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ 2751 #define NV_BACKKEY7_KEY_MASK (0xFFU) 2752 #define NV_BACKKEY7_KEY_SHIFT (0U) 2753 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) 2754 2755 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ 2756 #define NV_BACKKEY6_KEY_MASK (0xFFU) 2757 #define NV_BACKKEY6_KEY_SHIFT (0U) 2758 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) 2759 2760 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ 2761 #define NV_BACKKEY5_KEY_MASK (0xFFU) 2762 #define NV_BACKKEY5_KEY_SHIFT (0U) 2763 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) 2764 2765 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ 2766 #define NV_BACKKEY4_KEY_MASK (0xFFU) 2767 #define NV_BACKKEY4_KEY_SHIFT (0U) 2768 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) 2769 2770 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ 2771 #define NV_FPROT3_PROT_MASK (0xFFU) 2772 #define NV_FPROT3_PROT_SHIFT (0U) 2773 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) 2774 2775 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ 2776 #define NV_FPROT2_PROT_MASK (0xFFU) 2777 #define NV_FPROT2_PROT_SHIFT (0U) 2778 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) 2779 2780 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ 2781 #define NV_FPROT1_PROT_MASK (0xFFU) 2782 #define NV_FPROT1_PROT_SHIFT (0U) 2783 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) 2784 2785 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ 2786 #define NV_FPROT0_PROT_MASK (0xFFU) 2787 #define NV_FPROT0_PROT_SHIFT (0U) 2788 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) 2789 2790 /*! @name FSEC - Non-volatile Flash Security Register */ 2791 #define NV_FSEC_SEC_MASK (0x3U) 2792 #define NV_FSEC_SEC_SHIFT (0U) 2793 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) 2794 #define NV_FSEC_FSLACC_MASK (0xCU) 2795 #define NV_FSEC_FSLACC_SHIFT (2U) 2796 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) 2797 #define NV_FSEC_MEEN_MASK (0x30U) 2798 #define NV_FSEC_MEEN_SHIFT (4U) 2799 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) 2800 #define NV_FSEC_KEYEN_MASK (0xC0U) 2801 #define NV_FSEC_KEYEN_SHIFT (6U) 2802 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) 2803 2804 /*! @name FOPT - Non-volatile Flash Option Register */ 2805 #define NV_FOPT_LPBOOT0_MASK (0x1U) 2806 #define NV_FOPT_LPBOOT0_SHIFT (0U) 2807 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK) 2808 #define NV_FOPT_NMI_DIS_MASK (0x4U) 2809 #define NV_FOPT_NMI_DIS_SHIFT (2U) 2810 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) 2811 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) 2812 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) 2813 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) 2814 #define NV_FOPT_LPBOOT1_MASK (0x10U) 2815 #define NV_FOPT_LPBOOT1_SHIFT (4U) 2816 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK) 2817 #define NV_FOPT_FAST_INIT_MASK (0x20U) 2818 #define NV_FOPT_FAST_INIT_SHIFT (5U) 2819 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) 2820 2821 2822 /*! 2823 * @} 2824 */ /* end of group NV_Register_Masks */ 2825 2826 2827 /* NV - Peripheral instance base addresses */ 2828 /** Peripheral FTFA_FlashConfig base address */ 2829 #define FTFA_FlashConfig_BASE (0x400u) 2830 /** Peripheral FTFA_FlashConfig base pointer */ 2831 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 2832 /** Array initializer of NV peripheral base addresses */ 2833 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } 2834 /** Array initializer of NV peripheral base pointers */ 2835 #define NV_BASE_PTRS { FTFA_FlashConfig } 2836 2837 /*! 2838 * @} 2839 */ /* end of group NV_Peripheral_Access_Layer */ 2840 2841 2842 /* ---------------------------------------------------------------------------- 2843 -- OSC Peripheral Access Layer 2844 ---------------------------------------------------------------------------- */ 2845 2846 /*! 2847 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 2848 * @{ 2849 */ 2850 2851 /** OSC - Register Layout Typedef */ 2852 typedef struct { 2853 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 2854 } OSC_Type; 2855 2856 /* ---------------------------------------------------------------------------- 2857 -- OSC Register Masks 2858 ---------------------------------------------------------------------------- */ 2859 2860 /*! 2861 * @addtogroup OSC_Register_Masks OSC Register Masks 2862 * @{ 2863 */ 2864 2865 /*! @name CR - OSC Control Register */ 2866 #define OSC_CR_SC16P_MASK (0x1U) 2867 #define OSC_CR_SC16P_SHIFT (0U) 2868 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) 2869 #define OSC_CR_SC8P_MASK (0x2U) 2870 #define OSC_CR_SC8P_SHIFT (1U) 2871 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) 2872 #define OSC_CR_SC4P_MASK (0x4U) 2873 #define OSC_CR_SC4P_SHIFT (2U) 2874 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) 2875 #define OSC_CR_SC2P_MASK (0x8U) 2876 #define OSC_CR_SC2P_SHIFT (3U) 2877 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) 2878 #define OSC_CR_EREFSTEN_MASK (0x20U) 2879 #define OSC_CR_EREFSTEN_SHIFT (5U) 2880 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) 2881 #define OSC_CR_ERCLKEN_MASK (0x80U) 2882 #define OSC_CR_ERCLKEN_SHIFT (7U) 2883 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) 2884 2885 2886 /*! 2887 * @} 2888 */ /* end of group OSC_Register_Masks */ 2889 2890 2891 /* OSC - Peripheral instance base addresses */ 2892 /** Peripheral OSC0 base address */ 2893 #define OSC0_BASE (0x40065000u) 2894 /** Peripheral OSC0 base pointer */ 2895 #define OSC0 ((OSC_Type *)OSC0_BASE) 2896 /** Array initializer of OSC peripheral base addresses */ 2897 #define OSC_BASE_ADDRS { OSC0_BASE } 2898 /** Array initializer of OSC peripheral base pointers */ 2899 #define OSC_BASE_PTRS { OSC0 } 2900 2901 /*! 2902 * @} 2903 */ /* end of group OSC_Peripheral_Access_Layer */ 2904 2905 2906 /* ---------------------------------------------------------------------------- 2907 -- PIT Peripheral Access Layer 2908 ---------------------------------------------------------------------------- */ 2909 2910 /*! 2911 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 2912 * @{ 2913 */ 2914 2915 /** PIT - Register Layout Typedef */ 2916 typedef struct { 2917 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 2918 uint8_t RESERVED_0[220]; 2919 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 2920 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 2921 uint8_t RESERVED_1[24]; 2922 struct { /* offset: 0x100, array step: 0x10 */ 2923 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 2924 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 2925 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 2926 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 2927 } CHANNEL[2]; 2928 } PIT_Type; 2929 2930 /* ---------------------------------------------------------------------------- 2931 -- PIT Register Masks 2932 ---------------------------------------------------------------------------- */ 2933 2934 /*! 2935 * @addtogroup PIT_Register_Masks PIT Register Masks 2936 * @{ 2937 */ 2938 2939 /*! @name MCR - PIT Module Control Register */ 2940 #define PIT_MCR_FRZ_MASK (0x1U) 2941 #define PIT_MCR_FRZ_SHIFT (0U) 2942 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 2943 #define PIT_MCR_MDIS_MASK (0x2U) 2944 #define PIT_MCR_MDIS_SHIFT (1U) 2945 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 2946 2947 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ 2948 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) 2949 #define PIT_LTMR64H_LTH_SHIFT (0U) 2950 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) 2951 2952 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ 2953 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) 2954 #define PIT_LTMR64L_LTL_SHIFT (0U) 2955 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) 2956 2957 /*! @name LDVAL - Timer Load Value Register */ 2958 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 2959 #define PIT_LDVAL_TSV_SHIFT (0U) 2960 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 2961 2962 /* The count of PIT_LDVAL */ 2963 #define PIT_LDVAL_COUNT (2U) 2964 2965 /*! @name CVAL - Current Timer Value Register */ 2966 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 2967 #define PIT_CVAL_TVL_SHIFT (0U) 2968 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 2969 2970 /* The count of PIT_CVAL */ 2971 #define PIT_CVAL_COUNT (2U) 2972 2973 /*! @name TCTRL - Timer Control Register */ 2974 #define PIT_TCTRL_TEN_MASK (0x1U) 2975 #define PIT_TCTRL_TEN_SHIFT (0U) 2976 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 2977 #define PIT_TCTRL_TIE_MASK (0x2U) 2978 #define PIT_TCTRL_TIE_SHIFT (1U) 2979 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 2980 #define PIT_TCTRL_CHN_MASK (0x4U) 2981 #define PIT_TCTRL_CHN_SHIFT (2U) 2982 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 2983 2984 /* The count of PIT_TCTRL */ 2985 #define PIT_TCTRL_COUNT (2U) 2986 2987 /*! @name TFLG - Timer Flag Register */ 2988 #define PIT_TFLG_TIF_MASK (0x1U) 2989 #define PIT_TFLG_TIF_SHIFT (0U) 2990 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 2991 2992 /* The count of PIT_TFLG */ 2993 #define PIT_TFLG_COUNT (2U) 2994 2995 2996 /*! 2997 * @} 2998 */ /* end of group PIT_Register_Masks */ 2999 3000 3001 /* PIT - Peripheral instance base addresses */ 3002 /** Peripheral PIT base address */ 3003 #define PIT_BASE (0x40037000u) 3004 /** Peripheral PIT base pointer */ 3005 #define PIT ((PIT_Type *)PIT_BASE) 3006 /** Array initializer of PIT peripheral base addresses */ 3007 #define PIT_BASE_ADDRS { PIT_BASE } 3008 /** Array initializer of PIT peripheral base pointers */ 3009 #define PIT_BASE_PTRS { PIT } 3010 /** Interrupt vectors for the PIT peripheral type */ 3011 #define PIT_IRQS { { PIT_IRQn, PIT_IRQn } } 3012 3013 /*! 3014 * @} 3015 */ /* end of group PIT_Peripheral_Access_Layer */ 3016 3017 3018 /* ---------------------------------------------------------------------------- 3019 -- PMC Peripheral Access Layer 3020 ---------------------------------------------------------------------------- */ 3021 3022 /*! 3023 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 3024 * @{ 3025 */ 3026 3027 /** PMC - Register Layout Typedef */ 3028 typedef struct { 3029 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 3030 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 3031 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 3032 } PMC_Type; 3033 3034 /* ---------------------------------------------------------------------------- 3035 -- PMC Register Masks 3036 ---------------------------------------------------------------------------- */ 3037 3038 /*! 3039 * @addtogroup PMC_Register_Masks PMC Register Masks 3040 * @{ 3041 */ 3042 3043 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ 3044 #define PMC_LVDSC1_LVDV_MASK (0x3U) 3045 #define PMC_LVDSC1_LVDV_SHIFT (0U) 3046 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) 3047 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 3048 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 3049 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 3050 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 3051 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 3052 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 3053 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 3054 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 3055 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 3056 #define PMC_LVDSC1_LVDF_MASK (0x80U) 3057 #define PMC_LVDSC1_LVDF_SHIFT (7U) 3058 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 3059 3060 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ 3061 #define PMC_LVDSC2_LVWV_MASK (0x3U) 3062 #define PMC_LVDSC2_LVWV_SHIFT (0U) 3063 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) 3064 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 3065 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 3066 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 3067 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 3068 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 3069 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 3070 #define PMC_LVDSC2_LVWF_MASK (0x80U) 3071 #define PMC_LVDSC2_LVWF_SHIFT (7U) 3072 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 3073 3074 /*! @name REGSC - Regulator Status And Control register */ 3075 #define PMC_REGSC_BGBE_MASK (0x1U) 3076 #define PMC_REGSC_BGBE_SHIFT (0U) 3077 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) 3078 #define PMC_REGSC_REGONS_MASK (0x4U) 3079 #define PMC_REGSC_REGONS_SHIFT (2U) 3080 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) 3081 #define PMC_REGSC_ACKISO_MASK (0x8U) 3082 #define PMC_REGSC_ACKISO_SHIFT (3U) 3083 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) 3084 #define PMC_REGSC_BGEN_MASK (0x10U) 3085 #define PMC_REGSC_BGEN_SHIFT (4U) 3086 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) 3087 3088 3089 /*! 3090 * @} 3091 */ /* end of group PMC_Register_Masks */ 3092 3093 3094 /* PMC - Peripheral instance base addresses */ 3095 /** Peripheral PMC base address */ 3096 #define PMC_BASE (0x4007D000u) 3097 /** Peripheral PMC base pointer */ 3098 #define PMC ((PMC_Type *)PMC_BASE) 3099 /** Array initializer of PMC peripheral base addresses */ 3100 #define PMC_BASE_ADDRS { PMC_BASE } 3101 /** Array initializer of PMC peripheral base pointers */ 3102 #define PMC_BASE_PTRS { PMC } 3103 /** Interrupt vectors for the PMC peripheral type */ 3104 #define PMC_IRQS { LVD_LVW_IRQn } 3105 3106 /*! 3107 * @} 3108 */ /* end of group PMC_Peripheral_Access_Layer */ 3109 3110 3111 /* ---------------------------------------------------------------------------- 3112 -- PORT Peripheral Access Layer 3113 ---------------------------------------------------------------------------- */ 3114 3115 /*! 3116 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 3117 * @{ 3118 */ 3119 3120 /** PORT - Register Layout Typedef */ 3121 typedef struct { 3122 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 3123 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 3124 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 3125 uint8_t RESERVED_0[24]; 3126 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 3127 } PORT_Type; 3128 3129 /* ---------------------------------------------------------------------------- 3130 -- PORT Register Masks 3131 ---------------------------------------------------------------------------- */ 3132 3133 /*! 3134 * @addtogroup PORT_Register_Masks PORT Register Masks 3135 * @{ 3136 */ 3137 3138 /*! @name PCR - Pin Control Register n */ 3139 #define PORT_PCR_PS_MASK (0x1U) 3140 #define PORT_PCR_PS_SHIFT (0U) 3141 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 3142 #define PORT_PCR_PE_MASK (0x2U) 3143 #define PORT_PCR_PE_SHIFT (1U) 3144 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 3145 #define PORT_PCR_SRE_MASK (0x4U) 3146 #define PORT_PCR_SRE_SHIFT (2U) 3147 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) 3148 #define PORT_PCR_PFE_MASK (0x10U) 3149 #define PORT_PCR_PFE_SHIFT (4U) 3150 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) 3151 #define PORT_PCR_DSE_MASK (0x40U) 3152 #define PORT_PCR_DSE_SHIFT (6U) 3153 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) 3154 #define PORT_PCR_MUX_MASK (0x700U) 3155 #define PORT_PCR_MUX_SHIFT (8U) 3156 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 3157 #define PORT_PCR_IRQC_MASK (0xF0000U) 3158 #define PORT_PCR_IRQC_SHIFT (16U) 3159 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 3160 #define PORT_PCR_ISF_MASK (0x1000000U) 3161 #define PORT_PCR_ISF_SHIFT (24U) 3162 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 3163 3164 /* The count of PORT_PCR */ 3165 #define PORT_PCR_COUNT (32U) 3166 3167 /*! @name GPCLR - Global Pin Control Low Register */ 3168 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 3169 #define PORT_GPCLR_GPWD_SHIFT (0U) 3170 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 3171 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 3172 #define PORT_GPCLR_GPWE_SHIFT (16U) 3173 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 3174 3175 /*! @name GPCHR - Global Pin Control High Register */ 3176 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 3177 #define PORT_GPCHR_GPWD_SHIFT (0U) 3178 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 3179 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 3180 #define PORT_GPCHR_GPWE_SHIFT (16U) 3181 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 3182 3183 /*! @name ISFR - Interrupt Status Flag Register */ 3184 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 3185 #define PORT_ISFR_ISF_SHIFT (0U) 3186 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 3187 3188 3189 /*! 3190 * @} 3191 */ /* end of group PORT_Register_Masks */ 3192 3193 3194 /* PORT - Peripheral instance base addresses */ 3195 /** Peripheral PORTA base address */ 3196 #define PORTA_BASE (0x40049000u) 3197 /** Peripheral PORTA base pointer */ 3198 #define PORTA ((PORT_Type *)PORTA_BASE) 3199 /** Peripheral PORTB base address */ 3200 #define PORTB_BASE (0x4004A000u) 3201 /** Peripheral PORTB base pointer */ 3202 #define PORTB ((PORT_Type *)PORTB_BASE) 3203 /** Peripheral PORTC base address */ 3204 #define PORTC_BASE (0x4004B000u) 3205 /** Peripheral PORTC base pointer */ 3206 #define PORTC ((PORT_Type *)PORTC_BASE) 3207 /** Peripheral PORTD base address */ 3208 #define PORTD_BASE (0x4004C000u) 3209 /** Peripheral PORTD base pointer */ 3210 #define PORTD ((PORT_Type *)PORTD_BASE) 3211 /** Peripheral PORTE base address */ 3212 #define PORTE_BASE (0x4004D000u) 3213 /** Peripheral PORTE base pointer */ 3214 #define PORTE ((PORT_Type *)PORTE_BASE) 3215 /** Array initializer of PORT peripheral base addresses */ 3216 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } 3217 /** Array initializer of PORT peripheral base pointers */ 3218 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } 3219 /** Interrupt vectors for the PORT peripheral type */ 3220 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, NotAvail_IRQn, PORTD_IRQn, NotAvail_IRQn } 3221 3222 /*! 3223 * @} 3224 */ /* end of group PORT_Peripheral_Access_Layer */ 3225 3226 3227 /* ---------------------------------------------------------------------------- 3228 -- RCM Peripheral Access Layer 3229 ---------------------------------------------------------------------------- */ 3230 3231 /*! 3232 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 3233 * @{ 3234 */ 3235 3236 /** RCM - Register Layout Typedef */ 3237 typedef struct { 3238 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 3239 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 3240 uint8_t RESERVED_0[2]; 3241 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 3242 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 3243 } RCM_Type; 3244 3245 /* ---------------------------------------------------------------------------- 3246 -- RCM Register Masks 3247 ---------------------------------------------------------------------------- */ 3248 3249 /*! 3250 * @addtogroup RCM_Register_Masks RCM Register Masks 3251 * @{ 3252 */ 3253 3254 /*! @name SRS0 - System Reset Status Register 0 */ 3255 #define RCM_SRS0_WAKEUP_MASK (0x1U) 3256 #define RCM_SRS0_WAKEUP_SHIFT (0U) 3257 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) 3258 #define RCM_SRS0_LVD_MASK (0x2U) 3259 #define RCM_SRS0_LVD_SHIFT (1U) 3260 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) 3261 #define RCM_SRS0_LOC_MASK (0x4U) 3262 #define RCM_SRS0_LOC_SHIFT (2U) 3263 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) 3264 #define RCM_SRS0_LOL_MASK (0x8U) 3265 #define RCM_SRS0_LOL_SHIFT (3U) 3266 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) 3267 #define RCM_SRS0_WDOG_MASK (0x20U) 3268 #define RCM_SRS0_WDOG_SHIFT (5U) 3269 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) 3270 #define RCM_SRS0_PIN_MASK (0x40U) 3271 #define RCM_SRS0_PIN_SHIFT (6U) 3272 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) 3273 #define RCM_SRS0_POR_MASK (0x80U) 3274 #define RCM_SRS0_POR_SHIFT (7U) 3275 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) 3276 3277 /*! @name SRS1 - System Reset Status Register 1 */ 3278 #define RCM_SRS1_LOCKUP_MASK (0x2U) 3279 #define RCM_SRS1_LOCKUP_SHIFT (1U) 3280 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) 3281 #define RCM_SRS1_SW_MASK (0x4U) 3282 #define RCM_SRS1_SW_SHIFT (2U) 3283 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) 3284 #define RCM_SRS1_MDM_AP_MASK (0x8U) 3285 #define RCM_SRS1_MDM_AP_SHIFT (3U) 3286 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) 3287 #define RCM_SRS1_SACKERR_MASK (0x20U) 3288 #define RCM_SRS1_SACKERR_SHIFT (5U) 3289 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) 3290 3291 /*! @name RPFC - Reset Pin Filter Control register */ 3292 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) 3293 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) 3294 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) 3295 #define RCM_RPFC_RSTFLTSS_MASK (0x4U) 3296 #define RCM_RPFC_RSTFLTSS_SHIFT (2U) 3297 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) 3298 3299 /*! @name RPFW - Reset Pin Filter Width register */ 3300 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) 3301 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) 3302 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) 3303 3304 3305 /*! 3306 * @} 3307 */ /* end of group RCM_Register_Masks */ 3308 3309 3310 /* RCM - Peripheral instance base addresses */ 3311 /** Peripheral RCM base address */ 3312 #define RCM_BASE (0x4007F000u) 3313 /** Peripheral RCM base pointer */ 3314 #define RCM ((RCM_Type *)RCM_BASE) 3315 /** Array initializer of RCM peripheral base addresses */ 3316 #define RCM_BASE_ADDRS { RCM_BASE } 3317 /** Array initializer of RCM peripheral base pointers */ 3318 #define RCM_BASE_PTRS { RCM } 3319 3320 /*! 3321 * @} 3322 */ /* end of group RCM_Peripheral_Access_Layer */ 3323 3324 3325 /* ---------------------------------------------------------------------------- 3326 -- ROM Peripheral Access Layer 3327 ---------------------------------------------------------------------------- */ 3328 3329 /*! 3330 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 3331 * @{ 3332 */ 3333 3334 /** ROM - Register Layout Typedef */ 3335 typedef struct { 3336 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 3337 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 3338 uint8_t RESERVED_0[4028]; 3339 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 3340 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 3341 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 3342 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 3343 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 3344 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 3345 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 3346 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 3347 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 3348 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 3349 } ROM_Type; 3350 3351 /* ---------------------------------------------------------------------------- 3352 -- ROM Register Masks 3353 ---------------------------------------------------------------------------- */ 3354 3355 /*! 3356 * @addtogroup ROM_Register_Masks ROM Register Masks 3357 * @{ 3358 */ 3359 3360 /*! @name ENTRY - Entry */ 3361 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 3362 #define ROM_ENTRY_ENTRY_SHIFT (0U) 3363 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 3364 3365 /* The count of ROM_ENTRY */ 3366 #define ROM_ENTRY_COUNT (3U) 3367 3368 /*! @name TABLEMARK - End of Table Marker Register */ 3369 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 3370 #define ROM_TABLEMARK_MARK_SHIFT (0U) 3371 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 3372 3373 /*! @name SYSACCESS - System Access Register */ 3374 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 3375 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 3376 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 3377 3378 /*! @name PERIPHID4 - Peripheral ID Register */ 3379 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 3380 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 3381 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 3382 3383 /*! @name PERIPHID5 - Peripheral ID Register */ 3384 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 3385 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 3386 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 3387 3388 /*! @name PERIPHID6 - Peripheral ID Register */ 3389 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 3390 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 3391 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 3392 3393 /*! @name PERIPHID7 - Peripheral ID Register */ 3394 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 3395 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 3396 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 3397 3398 /*! @name PERIPHID0 - Peripheral ID Register */ 3399 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 3400 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 3401 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 3402 3403 /*! @name PERIPHID1 - Peripheral ID Register */ 3404 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 3405 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 3406 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 3407 3408 /*! @name PERIPHID2 - Peripheral ID Register */ 3409 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 3410 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 3411 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 3412 3413 /*! @name PERIPHID3 - Peripheral ID Register */ 3414 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 3415 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 3416 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 3417 3418 /*! @name COMPID - Component ID Register */ 3419 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 3420 #define ROM_COMPID_COMPID_SHIFT (0U) 3421 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 3422 3423 /* The count of ROM_COMPID */ 3424 #define ROM_COMPID_COUNT (4U) 3425 3426 3427 /*! 3428 * @} 3429 */ /* end of group ROM_Register_Masks */ 3430 3431 3432 /* ROM - Peripheral instance base addresses */ 3433 /** Peripheral ROM base address */ 3434 #define ROM_BASE (0xF0002000u) 3435 /** Peripheral ROM base pointer */ 3436 #define ROM ((ROM_Type *)ROM_BASE) 3437 /** Array initializer of ROM peripheral base addresses */ 3438 #define ROM_BASE_ADDRS { ROM_BASE } 3439 /** Array initializer of ROM peripheral base pointers */ 3440 #define ROM_BASE_PTRS { ROM } 3441 3442 /*! 3443 * @} 3444 */ /* end of group ROM_Peripheral_Access_Layer */ 3445 3446 3447 /* ---------------------------------------------------------------------------- 3448 -- RTC Peripheral Access Layer 3449 ---------------------------------------------------------------------------- */ 3450 3451 /*! 3452 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 3453 * @{ 3454 */ 3455 3456 /** RTC - Register Layout Typedef */ 3457 typedef struct { 3458 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 3459 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 3460 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 3461 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 3462 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 3463 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 3464 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 3465 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 3466 } RTC_Type; 3467 3468 /* ---------------------------------------------------------------------------- 3469 -- RTC Register Masks 3470 ---------------------------------------------------------------------------- */ 3471 3472 /*! 3473 * @addtogroup RTC_Register_Masks RTC Register Masks 3474 * @{ 3475 */ 3476 3477 /*! @name TSR - RTC Time Seconds Register */ 3478 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) 3479 #define RTC_TSR_TSR_SHIFT (0U) 3480 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) 3481 3482 /*! @name TPR - RTC Time Prescaler Register */ 3483 #define RTC_TPR_TPR_MASK (0xFFFFU) 3484 #define RTC_TPR_TPR_SHIFT (0U) 3485 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) 3486 3487 /*! @name TAR - RTC Time Alarm Register */ 3488 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) 3489 #define RTC_TAR_TAR_SHIFT (0U) 3490 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) 3491 3492 /*! @name TCR - RTC Time Compensation Register */ 3493 #define RTC_TCR_TCR_MASK (0xFFU) 3494 #define RTC_TCR_TCR_SHIFT (0U) 3495 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) 3496 #define RTC_TCR_CIR_MASK (0xFF00U) 3497 #define RTC_TCR_CIR_SHIFT (8U) 3498 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) 3499 #define RTC_TCR_TCV_MASK (0xFF0000U) 3500 #define RTC_TCR_TCV_SHIFT (16U) 3501 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) 3502 #define RTC_TCR_CIC_MASK (0xFF000000U) 3503 #define RTC_TCR_CIC_SHIFT (24U) 3504 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) 3505 3506 /*! @name CR - RTC Control Register */ 3507 #define RTC_CR_SWR_MASK (0x1U) 3508 #define RTC_CR_SWR_SHIFT (0U) 3509 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) 3510 #define RTC_CR_WPE_MASK (0x2U) 3511 #define RTC_CR_WPE_SHIFT (1U) 3512 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) 3513 #define RTC_CR_SUP_MASK (0x4U) 3514 #define RTC_CR_SUP_SHIFT (2U) 3515 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) 3516 #define RTC_CR_UM_MASK (0x8U) 3517 #define RTC_CR_UM_SHIFT (3U) 3518 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) 3519 #define RTC_CR_OSCE_MASK (0x100U) 3520 #define RTC_CR_OSCE_SHIFT (8U) 3521 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) 3522 #define RTC_CR_CLKO_MASK (0x200U) 3523 #define RTC_CR_CLKO_SHIFT (9U) 3524 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) 3525 #define RTC_CR_SC16P_MASK (0x400U) 3526 #define RTC_CR_SC16P_SHIFT (10U) 3527 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) 3528 #define RTC_CR_SC8P_MASK (0x800U) 3529 #define RTC_CR_SC8P_SHIFT (11U) 3530 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) 3531 #define RTC_CR_SC4P_MASK (0x1000U) 3532 #define RTC_CR_SC4P_SHIFT (12U) 3533 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) 3534 #define RTC_CR_SC2P_MASK (0x2000U) 3535 #define RTC_CR_SC2P_SHIFT (13U) 3536 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) 3537 3538 /*! @name SR - RTC Status Register */ 3539 #define RTC_SR_TIF_MASK (0x1U) 3540 #define RTC_SR_TIF_SHIFT (0U) 3541 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) 3542 #define RTC_SR_TOF_MASK (0x2U) 3543 #define RTC_SR_TOF_SHIFT (1U) 3544 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) 3545 #define RTC_SR_TAF_MASK (0x4U) 3546 #define RTC_SR_TAF_SHIFT (2U) 3547 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) 3548 #define RTC_SR_TCE_MASK (0x10U) 3549 #define RTC_SR_TCE_SHIFT (4U) 3550 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) 3551 3552 /*! @name LR - RTC Lock Register */ 3553 #define RTC_LR_TCL_MASK (0x8U) 3554 #define RTC_LR_TCL_SHIFT (3U) 3555 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) 3556 #define RTC_LR_CRL_MASK (0x10U) 3557 #define RTC_LR_CRL_SHIFT (4U) 3558 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) 3559 #define RTC_LR_SRL_MASK (0x20U) 3560 #define RTC_LR_SRL_SHIFT (5U) 3561 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) 3562 #define RTC_LR_LRL_MASK (0x40U) 3563 #define RTC_LR_LRL_SHIFT (6U) 3564 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) 3565 3566 /*! @name IER - RTC Interrupt Enable Register */ 3567 #define RTC_IER_TIIE_MASK (0x1U) 3568 #define RTC_IER_TIIE_SHIFT (0U) 3569 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) 3570 #define RTC_IER_TOIE_MASK (0x2U) 3571 #define RTC_IER_TOIE_SHIFT (1U) 3572 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) 3573 #define RTC_IER_TAIE_MASK (0x4U) 3574 #define RTC_IER_TAIE_SHIFT (2U) 3575 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) 3576 #define RTC_IER_TSIE_MASK (0x10U) 3577 #define RTC_IER_TSIE_SHIFT (4U) 3578 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) 3579 #define RTC_IER_WPON_MASK (0x80U) 3580 #define RTC_IER_WPON_SHIFT (7U) 3581 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) 3582 3583 3584 /*! 3585 * @} 3586 */ /* end of group RTC_Register_Masks */ 3587 3588 3589 /* RTC - Peripheral instance base addresses */ 3590 /** Peripheral RTC base address */ 3591 #define RTC_BASE (0x4003D000u) 3592 /** Peripheral RTC base pointer */ 3593 #define RTC ((RTC_Type *)RTC_BASE) 3594 /** Array initializer of RTC peripheral base addresses */ 3595 #define RTC_BASE_ADDRS { RTC_BASE } 3596 /** Array initializer of RTC peripheral base pointers */ 3597 #define RTC_BASE_PTRS { RTC } 3598 /** Interrupt vectors for the RTC peripheral type */ 3599 #define RTC_IRQS { RTC_IRQn } 3600 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } 3601 3602 /*! 3603 * @} 3604 */ /* end of group RTC_Peripheral_Access_Layer */ 3605 3606 3607 /* ---------------------------------------------------------------------------- 3608 -- SIM Peripheral Access Layer 3609 ---------------------------------------------------------------------------- */ 3610 3611 /*! 3612 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 3613 * @{ 3614 */ 3615 3616 /** SIM - Register Layout Typedef */ 3617 typedef struct { 3618 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 3619 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 3620 uint8_t RESERVED_0[4092]; 3621 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 3622 uint8_t RESERVED_1[4]; 3623 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 3624 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 3625 uint8_t RESERVED_2[4]; 3626 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 3627 uint8_t RESERVED_3[8]; 3628 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 3629 uint8_t RESERVED_4[12]; 3630 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 3631 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 3632 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 3633 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 3634 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 3635 uint8_t RESERVED_5[4]; 3636 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 3637 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 3638 uint8_t RESERVED_6[4]; 3639 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 3640 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 3641 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 3642 uint8_t RESERVED_7[156]; 3643 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ 3644 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */ 3645 } SIM_Type; 3646 3647 /* ---------------------------------------------------------------------------- 3648 -- SIM Register Masks 3649 ---------------------------------------------------------------------------- */ 3650 3651 /*! 3652 * @addtogroup SIM_Register_Masks SIM Register Masks 3653 * @{ 3654 */ 3655 3656 /*! @name SOPT1 - System Options Register 1 */ 3657 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) 3658 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) 3659 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) 3660 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) 3661 #define SIM_SOPT1_USBVSTBY_SHIFT (29U) 3662 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) 3663 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) 3664 #define SIM_SOPT1_USBSSTBY_SHIFT (30U) 3665 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) 3666 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U) 3667 #define SIM_SOPT1_USBREGEN_SHIFT (31U) 3668 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) 3669 3670 /*! @name SOPT1CFG - SOPT1 Configuration Register */ 3671 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) 3672 #define SIM_SOPT1CFG_URWE_SHIFT (24U) 3673 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) 3674 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) 3675 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U) 3676 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) 3677 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) 3678 #define SIM_SOPT1CFG_USSWE_SHIFT (26U) 3679 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) 3680 3681 /*! @name SOPT2 - System Options Register 2 */ 3682 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) 3683 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) 3684 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) 3685 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) 3686 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) 3687 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) 3688 #define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U) 3689 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) 3690 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) 3691 #define SIM_SOPT2_USBSRC_MASK (0x40000U) 3692 #define SIM_SOPT2_USBSRC_SHIFT (18U) 3693 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) 3694 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U) 3695 #define SIM_SOPT2_TPMSRC_SHIFT (24U) 3696 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) 3697 #define SIM_SOPT2_UART0SRC_MASK (0xC000000U) 3698 #define SIM_SOPT2_UART0SRC_SHIFT (26U) 3699 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_UART0SRC_SHIFT)) & SIM_SOPT2_UART0SRC_MASK) 3700 3701 /*! @name SOPT4 - System Options Register 4 */ 3702 #define SIM_SOPT4_TPM1CH0SRC_MASK (0x40000U) 3703 #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U) 3704 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK) 3705 #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U) 3706 #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U) 3707 #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK) 3708 #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U) 3709 #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U) 3710 #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK) 3711 #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U) 3712 #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U) 3713 #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK) 3714 #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U) 3715 #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U) 3716 #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK) 3717 3718 /*! @name SOPT5 - System Options Register 5 */ 3719 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U) 3720 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U) 3721 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) 3722 #define SIM_SOPT5_UART0RXSRC_MASK (0x4U) 3723 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U) 3724 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) 3725 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U) 3726 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U) 3727 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) 3728 #define SIM_SOPT5_UART1RXSRC_MASK (0x40U) 3729 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U) 3730 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) 3731 #define SIM_SOPT5_UART0ODE_MASK (0x10000U) 3732 #define SIM_SOPT5_UART0ODE_SHIFT (16U) 3733 #define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK) 3734 #define SIM_SOPT5_UART1ODE_MASK (0x20000U) 3735 #define SIM_SOPT5_UART1ODE_SHIFT (17U) 3736 #define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK) 3737 #define SIM_SOPT5_UART2ODE_MASK (0x40000U) 3738 #define SIM_SOPT5_UART2ODE_SHIFT (18U) 3739 #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK) 3740 3741 /*! @name SOPT7 - System Options Register 7 */ 3742 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) 3743 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) 3744 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) 3745 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) 3746 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) 3747 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) 3748 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) 3749 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) 3750 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) 3751 3752 /*! @name SDID - System Device Identification Register */ 3753 #define SIM_SDID_PINID_MASK (0xFU) 3754 #define SIM_SDID_PINID_SHIFT (0U) 3755 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) 3756 #define SIM_SDID_DIEID_MASK (0xF80U) 3757 #define SIM_SDID_DIEID_SHIFT (7U) 3758 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) 3759 #define SIM_SDID_REVID_MASK (0xF000U) 3760 #define SIM_SDID_REVID_SHIFT (12U) 3761 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 3762 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U) 3763 #define SIM_SDID_SRAMSIZE_SHIFT (16U) 3764 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) 3765 #define SIM_SDID_SERIESID_MASK (0xF00000U) 3766 #define SIM_SDID_SERIESID_SHIFT (20U) 3767 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) 3768 #define SIM_SDID_SUBFAMID_MASK (0xF000000U) 3769 #define SIM_SDID_SUBFAMID_SHIFT (24U) 3770 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) 3771 #define SIM_SDID_FAMID_MASK (0xF0000000U) 3772 #define SIM_SDID_FAMID_SHIFT (28U) 3773 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) 3774 3775 /*! @name SCGC4 - System Clock Gating Control Register 4 */ 3776 #define SIM_SCGC4_I2C0_MASK (0x40U) 3777 #define SIM_SCGC4_I2C0_SHIFT (6U) 3778 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) 3779 #define SIM_SCGC4_I2C1_MASK (0x80U) 3780 #define SIM_SCGC4_I2C1_SHIFT (7U) 3781 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) 3782 #define SIM_SCGC4_UART0_MASK (0x400U) 3783 #define SIM_SCGC4_UART0_SHIFT (10U) 3784 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) 3785 #define SIM_SCGC4_UART1_MASK (0x800U) 3786 #define SIM_SCGC4_UART1_SHIFT (11U) 3787 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) 3788 #define SIM_SCGC4_UART2_MASK (0x1000U) 3789 #define SIM_SCGC4_UART2_SHIFT (12U) 3790 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) 3791 #define SIM_SCGC4_USBOTG_MASK (0x40000U) 3792 #define SIM_SCGC4_USBOTG_SHIFT (18U) 3793 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) 3794 #define SIM_SCGC4_CMP_MASK (0x80000U) 3795 #define SIM_SCGC4_CMP_SHIFT (19U) 3796 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) 3797 #define SIM_SCGC4_SPI0_MASK (0x400000U) 3798 #define SIM_SCGC4_SPI0_SHIFT (22U) 3799 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK) 3800 #define SIM_SCGC4_SPI1_MASK (0x800000U) 3801 #define SIM_SCGC4_SPI1_SHIFT (23U) 3802 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK) 3803 3804 /*! @name SCGC5 - System Clock Gating Control Register 5 */ 3805 #define SIM_SCGC5_LPTMR_MASK (0x1U) 3806 #define SIM_SCGC5_LPTMR_SHIFT (0U) 3807 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) 3808 #define SIM_SCGC5_TSI_MASK (0x20U) 3809 #define SIM_SCGC5_TSI_SHIFT (5U) 3810 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK) 3811 #define SIM_SCGC5_PORTA_MASK (0x200U) 3812 #define SIM_SCGC5_PORTA_SHIFT (9U) 3813 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) 3814 #define SIM_SCGC5_PORTB_MASK (0x400U) 3815 #define SIM_SCGC5_PORTB_SHIFT (10U) 3816 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) 3817 #define SIM_SCGC5_PORTC_MASK (0x800U) 3818 #define SIM_SCGC5_PORTC_SHIFT (11U) 3819 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) 3820 #define SIM_SCGC5_PORTD_MASK (0x1000U) 3821 #define SIM_SCGC5_PORTD_SHIFT (12U) 3822 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) 3823 #define SIM_SCGC5_PORTE_MASK (0x2000U) 3824 #define SIM_SCGC5_PORTE_SHIFT (13U) 3825 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) 3826 3827 /*! @name SCGC6 - System Clock Gating Control Register 6 */ 3828 #define SIM_SCGC6_FTF_MASK (0x1U) 3829 #define SIM_SCGC6_FTF_SHIFT (0U) 3830 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) 3831 #define SIM_SCGC6_DMAMUX_MASK (0x2U) 3832 #define SIM_SCGC6_DMAMUX_SHIFT (1U) 3833 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) 3834 #define SIM_SCGC6_PIT_MASK (0x800000U) 3835 #define SIM_SCGC6_PIT_SHIFT (23U) 3836 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) 3837 #define SIM_SCGC6_TPM0_MASK (0x1000000U) 3838 #define SIM_SCGC6_TPM0_SHIFT (24U) 3839 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK) 3840 #define SIM_SCGC6_TPM1_MASK (0x2000000U) 3841 #define SIM_SCGC6_TPM1_SHIFT (25U) 3842 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK) 3843 #define SIM_SCGC6_TPM2_MASK (0x4000000U) 3844 #define SIM_SCGC6_TPM2_SHIFT (26U) 3845 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK) 3846 #define SIM_SCGC6_ADC0_MASK (0x8000000U) 3847 #define SIM_SCGC6_ADC0_SHIFT (27U) 3848 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) 3849 #define SIM_SCGC6_RTC_MASK (0x20000000U) 3850 #define SIM_SCGC6_RTC_SHIFT (29U) 3851 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) 3852 #define SIM_SCGC6_DAC0_MASK (0x80000000U) 3853 #define SIM_SCGC6_DAC0_SHIFT (31U) 3854 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) 3855 3856 /*! @name SCGC7 - System Clock Gating Control Register 7 */ 3857 #define SIM_SCGC7_DMA_MASK (0x100U) 3858 #define SIM_SCGC7_DMA_SHIFT (8U) 3859 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) 3860 3861 /*! @name CLKDIV1 - System Clock Divider Register 1 */ 3862 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U) 3863 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) 3864 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) 3865 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) 3866 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) 3867 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) 3868 3869 /*! @name FCFG1 - Flash Configuration Register 1 */ 3870 #define SIM_FCFG1_FLASHDIS_MASK (0x1U) 3871 #define SIM_FCFG1_FLASHDIS_SHIFT (0U) 3872 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) 3873 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) 3874 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) 3875 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) 3876 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) 3877 #define SIM_FCFG1_PFSIZE_SHIFT (24U) 3878 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) 3879 3880 /*! @name FCFG2 - Flash Configuration Register 2 */ 3881 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) 3882 #define SIM_FCFG2_MAXADDR0_SHIFT (24U) 3883 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) 3884 3885 /*! @name UIDMH - Unique Identification Register Mid-High */ 3886 #define SIM_UIDMH_UID_MASK (0xFFFFU) 3887 #define SIM_UIDMH_UID_SHIFT (0U) 3888 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) 3889 3890 /*! @name UIDML - Unique Identification Register Mid Low */ 3891 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) 3892 #define SIM_UIDML_UID_SHIFT (0U) 3893 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) 3894 3895 /*! @name UIDL - Unique Identification Register Low */ 3896 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) 3897 #define SIM_UIDL_UID_SHIFT (0U) 3898 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) 3899 3900 /*! @name COPC - COP Control Register */ 3901 #define SIM_COPC_COPW_MASK (0x1U) 3902 #define SIM_COPC_COPW_SHIFT (0U) 3903 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK) 3904 #define SIM_COPC_COPCLKS_MASK (0x2U) 3905 #define SIM_COPC_COPCLKS_SHIFT (1U) 3906 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK) 3907 #define SIM_COPC_COPT_MASK (0xCU) 3908 #define SIM_COPC_COPT_SHIFT (2U) 3909 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK) 3910 3911 /*! @name SRVCOP - Service COP Register */ 3912 #define SIM_SRVCOP_SRVCOP_MASK (0xFFU) 3913 #define SIM_SRVCOP_SRVCOP_SHIFT (0U) 3914 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK) 3915 3916 3917 /*! 3918 * @} 3919 */ /* end of group SIM_Register_Masks */ 3920 3921 3922 /* SIM - Peripheral instance base addresses */ 3923 /** Peripheral SIM base address */ 3924 #define SIM_BASE (0x40047000u) 3925 /** Peripheral SIM base pointer */ 3926 #define SIM ((SIM_Type *)SIM_BASE) 3927 /** Array initializer of SIM peripheral base addresses */ 3928 #define SIM_BASE_ADDRS { SIM_BASE } 3929 /** Array initializer of SIM peripheral base pointers */ 3930 #define SIM_BASE_PTRS { SIM } 3931 3932 /*! 3933 * @} 3934 */ /* end of group SIM_Peripheral_Access_Layer */ 3935 3936 3937 /* ---------------------------------------------------------------------------- 3938 -- SMC Peripheral Access Layer 3939 ---------------------------------------------------------------------------- */ 3940 3941 /*! 3942 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 3943 * @{ 3944 */ 3945 3946 /** SMC - Register Layout Typedef */ 3947 typedef struct { 3948 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 3949 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 3950 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 3951 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 3952 } SMC_Type; 3953 3954 /* ---------------------------------------------------------------------------- 3955 -- SMC Register Masks 3956 ---------------------------------------------------------------------------- */ 3957 3958 /*! 3959 * @addtogroup SMC_Register_Masks SMC Register Masks 3960 * @{ 3961 */ 3962 3963 /*! @name PMPROT - Power Mode Protection register */ 3964 #define SMC_PMPROT_AVLLS_MASK (0x2U) 3965 #define SMC_PMPROT_AVLLS_SHIFT (1U) 3966 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) 3967 #define SMC_PMPROT_ALLS_MASK (0x8U) 3968 #define SMC_PMPROT_ALLS_SHIFT (3U) 3969 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) 3970 #define SMC_PMPROT_AVLP_MASK (0x20U) 3971 #define SMC_PMPROT_AVLP_SHIFT (5U) 3972 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 3973 3974 /*! @name PMCTRL - Power Mode Control register */ 3975 #define SMC_PMCTRL_STOPM_MASK (0x7U) 3976 #define SMC_PMCTRL_STOPM_SHIFT (0U) 3977 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 3978 #define SMC_PMCTRL_STOPA_MASK (0x8U) 3979 #define SMC_PMCTRL_STOPA_SHIFT (3U) 3980 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) 3981 #define SMC_PMCTRL_RUNM_MASK (0x60U) 3982 #define SMC_PMCTRL_RUNM_SHIFT (5U) 3983 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 3984 3985 /*! @name STOPCTRL - Stop Control Register */ 3986 #define SMC_STOPCTRL_VLLSM_MASK (0x7U) 3987 #define SMC_STOPCTRL_VLLSM_SHIFT (0U) 3988 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK) 3989 #define SMC_STOPCTRL_PORPO_MASK (0x20U) 3990 #define SMC_STOPCTRL_PORPO_SHIFT (5U) 3991 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) 3992 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) 3993 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) 3994 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) 3995 3996 /*! @name PMSTAT - Power Mode Status register */ 3997 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU) 3998 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 3999 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 4000 4001 4002 /*! 4003 * @} 4004 */ /* end of group SMC_Register_Masks */ 4005 4006 4007 /* SMC - Peripheral instance base addresses */ 4008 /** Peripheral SMC base address */ 4009 #define SMC_BASE (0x4007E000u) 4010 /** Peripheral SMC base pointer */ 4011 #define SMC ((SMC_Type *)SMC_BASE) 4012 /** Array initializer of SMC peripheral base addresses */ 4013 #define SMC_BASE_ADDRS { SMC_BASE } 4014 /** Array initializer of SMC peripheral base pointers */ 4015 #define SMC_BASE_PTRS { SMC } 4016 4017 /*! 4018 * @} 4019 */ /* end of group SMC_Peripheral_Access_Layer */ 4020 4021 4022 /* ---------------------------------------------------------------------------- 4023 -- SPI Peripheral Access Layer 4024 ---------------------------------------------------------------------------- */ 4025 4026 /*! 4027 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 4028 * @{ 4029 */ 4030 4031 /** SPI - Register Layout Typedef */ 4032 typedef struct { 4033 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */ 4034 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */ 4035 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */ 4036 __IO uint8_t S; /**< SPI status register, offset: 0x3 */ 4037 uint8_t RESERVED_0[1]; 4038 __IO uint8_t D; /**< SPI data register, offset: 0x5 */ 4039 uint8_t RESERVED_1[1]; 4040 __IO uint8_t M; /**< SPI match register, offset: 0x7 */ 4041 } SPI_Type; 4042 4043 /* ---------------------------------------------------------------------------- 4044 -- SPI Register Masks 4045 ---------------------------------------------------------------------------- */ 4046 4047 /*! 4048 * @addtogroup SPI_Register_Masks SPI Register Masks 4049 * @{ 4050 */ 4051 4052 /*! @name C1 - SPI control register 1 */ 4053 #define SPI_C1_LSBFE_MASK (0x1U) 4054 #define SPI_C1_LSBFE_SHIFT (0U) 4055 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) 4056 #define SPI_C1_SSOE_MASK (0x2U) 4057 #define SPI_C1_SSOE_SHIFT (1U) 4058 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) 4059 #define SPI_C1_CPHA_MASK (0x4U) 4060 #define SPI_C1_CPHA_SHIFT (2U) 4061 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) 4062 #define SPI_C1_CPOL_MASK (0x8U) 4063 #define SPI_C1_CPOL_SHIFT (3U) 4064 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) 4065 #define SPI_C1_MSTR_MASK (0x10U) 4066 #define SPI_C1_MSTR_SHIFT (4U) 4067 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) 4068 #define SPI_C1_SPTIE_MASK (0x20U) 4069 #define SPI_C1_SPTIE_SHIFT (5U) 4070 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) 4071 #define SPI_C1_SPE_MASK (0x40U) 4072 #define SPI_C1_SPE_SHIFT (6U) 4073 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) 4074 #define SPI_C1_SPIE_MASK (0x80U) 4075 #define SPI_C1_SPIE_SHIFT (7U) 4076 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) 4077 4078 /*! @name C2 - SPI control register 2 */ 4079 #define SPI_C2_SPC0_MASK (0x1U) 4080 #define SPI_C2_SPC0_SHIFT (0U) 4081 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) 4082 #define SPI_C2_SPISWAI_MASK (0x2U) 4083 #define SPI_C2_SPISWAI_SHIFT (1U) 4084 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) 4085 #define SPI_C2_RXDMAE_MASK (0x4U) 4086 #define SPI_C2_RXDMAE_SHIFT (2U) 4087 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK) 4088 #define SPI_C2_BIDIROE_MASK (0x8U) 4089 #define SPI_C2_BIDIROE_SHIFT (3U) 4090 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) 4091 #define SPI_C2_MODFEN_MASK (0x10U) 4092 #define SPI_C2_MODFEN_SHIFT (4U) 4093 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) 4094 #define SPI_C2_TXDMAE_MASK (0x20U) 4095 #define SPI_C2_TXDMAE_SHIFT (5U) 4096 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK) 4097 #define SPI_C2_SPMIE_MASK (0x80U) 4098 #define SPI_C2_SPMIE_SHIFT (7U) 4099 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) 4100 4101 /*! @name BR - SPI baud rate register */ 4102 #define SPI_BR_SPR_MASK (0xFU) 4103 #define SPI_BR_SPR_SHIFT (0U) 4104 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) 4105 #define SPI_BR_SPPR_MASK (0x70U) 4106 #define SPI_BR_SPPR_SHIFT (4U) 4107 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) 4108 4109 /*! @name S - SPI status register */ 4110 #define SPI_S_MODF_MASK (0x10U) 4111 #define SPI_S_MODF_SHIFT (4U) 4112 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) 4113 #define SPI_S_SPTEF_MASK (0x20U) 4114 #define SPI_S_SPTEF_SHIFT (5U) 4115 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) 4116 #define SPI_S_SPMF_MASK (0x40U) 4117 #define SPI_S_SPMF_SHIFT (6U) 4118 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) 4119 #define SPI_S_SPRF_MASK (0x80U) 4120 #define SPI_S_SPRF_SHIFT (7U) 4121 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) 4122 4123 /*! @name D - SPI data register */ 4124 #define SPI_D_Bits_MASK (0xFFU) 4125 #define SPI_D_Bits_SHIFT (0U) 4126 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_D_Bits_SHIFT)) & SPI_D_Bits_MASK) 4127 4128 /*! @name M - SPI match register */ 4129 #define SPI_M_Bits_MASK (0xFFU) 4130 #define SPI_M_Bits_SHIFT (0U) 4131 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_M_Bits_SHIFT)) & SPI_M_Bits_MASK) 4132 4133 4134 /*! 4135 * @} 4136 */ /* end of group SPI_Register_Masks */ 4137 4138 4139 /* SPI - Peripheral instance base addresses */ 4140 /** Peripheral SPI0 base address */ 4141 #define SPI0_BASE (0x40076000u) 4142 /** Peripheral SPI0 base pointer */ 4143 #define SPI0 ((SPI_Type *)SPI0_BASE) 4144 /** Peripheral SPI1 base address */ 4145 #define SPI1_BASE (0x40077000u) 4146 /** Peripheral SPI1 base pointer */ 4147 #define SPI1 ((SPI_Type *)SPI1_BASE) 4148 /** Array initializer of SPI peripheral base addresses */ 4149 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } 4150 /** Array initializer of SPI peripheral base pointers */ 4151 #define SPI_BASE_PTRS { SPI0, SPI1 } 4152 /** Interrupt vectors for the SPI peripheral type */ 4153 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } 4154 4155 /*! 4156 * @} 4157 */ /* end of group SPI_Peripheral_Access_Layer */ 4158 4159 4160 /* ---------------------------------------------------------------------------- 4161 -- TPM Peripheral Access Layer 4162 ---------------------------------------------------------------------------- */ 4163 4164 /*! 4165 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer 4166 * @{ 4167 */ 4168 4169 /** TPM - Register Layout Typedef */ 4170 typedef struct { 4171 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ 4172 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 4173 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 4174 struct { /* offset: 0xC, array step: 0x8 */ 4175 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ 4176 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 4177 } CONTROLS[6]; 4178 uint8_t RESERVED_0[20]; 4179 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ 4180 uint8_t RESERVED_1[48]; 4181 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 4182 } TPM_Type; 4183 4184 /* ---------------------------------------------------------------------------- 4185 -- TPM Register Masks 4186 ---------------------------------------------------------------------------- */ 4187 4188 /*! 4189 * @addtogroup TPM_Register_Masks TPM Register Masks 4190 * @{ 4191 */ 4192 4193 /*! @name SC - Status and Control */ 4194 #define TPM_SC_PS_MASK (0x7U) 4195 #define TPM_SC_PS_SHIFT (0U) 4196 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) 4197 #define TPM_SC_CMOD_MASK (0x18U) 4198 #define TPM_SC_CMOD_SHIFT (3U) 4199 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) 4200 #define TPM_SC_CPWMS_MASK (0x20U) 4201 #define TPM_SC_CPWMS_SHIFT (5U) 4202 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) 4203 #define TPM_SC_TOIE_MASK (0x40U) 4204 #define TPM_SC_TOIE_SHIFT (6U) 4205 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) 4206 #define TPM_SC_TOF_MASK (0x80U) 4207 #define TPM_SC_TOF_SHIFT (7U) 4208 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) 4209 #define TPM_SC_DMA_MASK (0x100U) 4210 #define TPM_SC_DMA_SHIFT (8U) 4211 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) 4212 4213 /*! @name CNT - Counter */ 4214 #define TPM_CNT_COUNT_MASK (0xFFFFU) 4215 #define TPM_CNT_COUNT_SHIFT (0U) 4216 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) 4217 4218 /*! @name MOD - Modulo */ 4219 #define TPM_MOD_MOD_MASK (0xFFFFU) 4220 #define TPM_MOD_MOD_SHIFT (0U) 4221 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) 4222 4223 /*! @name CnSC - Channel (n) Status and Control */ 4224 #define TPM_CnSC_DMA_MASK (0x1U) 4225 #define TPM_CnSC_DMA_SHIFT (0U) 4226 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) 4227 #define TPM_CnSC_ELSA_MASK (0x4U) 4228 #define TPM_CnSC_ELSA_SHIFT (2U) 4229 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) 4230 #define TPM_CnSC_ELSB_MASK (0x8U) 4231 #define TPM_CnSC_ELSB_SHIFT (3U) 4232 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) 4233 #define TPM_CnSC_MSA_MASK (0x10U) 4234 #define TPM_CnSC_MSA_SHIFT (4U) 4235 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) 4236 #define TPM_CnSC_MSB_MASK (0x20U) 4237 #define TPM_CnSC_MSB_SHIFT (5U) 4238 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) 4239 #define TPM_CnSC_CHIE_MASK (0x40U) 4240 #define TPM_CnSC_CHIE_SHIFT (6U) 4241 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) 4242 #define TPM_CnSC_CHF_MASK (0x80U) 4243 #define TPM_CnSC_CHF_SHIFT (7U) 4244 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) 4245 4246 /* The count of TPM_CnSC */ 4247 #define TPM_CnSC_COUNT (6U) 4248 4249 /*! @name CnV - Channel (n) Value */ 4250 #define TPM_CnV_VAL_MASK (0xFFFFU) 4251 #define TPM_CnV_VAL_SHIFT (0U) 4252 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) 4253 4254 /* The count of TPM_CnV */ 4255 #define TPM_CnV_COUNT (6U) 4256 4257 /*! @name STATUS - Capture and Compare Status */ 4258 #define TPM_STATUS_CH0F_MASK (0x1U) 4259 #define TPM_STATUS_CH0F_SHIFT (0U) 4260 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) 4261 #define TPM_STATUS_CH1F_MASK (0x2U) 4262 #define TPM_STATUS_CH1F_SHIFT (1U) 4263 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) 4264 #define TPM_STATUS_CH2F_MASK (0x4U) 4265 #define TPM_STATUS_CH2F_SHIFT (2U) 4266 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) 4267 #define TPM_STATUS_CH3F_MASK (0x8U) 4268 #define TPM_STATUS_CH3F_SHIFT (3U) 4269 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) 4270 #define TPM_STATUS_CH4F_MASK (0x10U) 4271 #define TPM_STATUS_CH4F_SHIFT (4U) 4272 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) 4273 #define TPM_STATUS_CH5F_MASK (0x20U) 4274 #define TPM_STATUS_CH5F_SHIFT (5U) 4275 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) 4276 #define TPM_STATUS_TOF_MASK (0x100U) 4277 #define TPM_STATUS_TOF_SHIFT (8U) 4278 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) 4279 4280 /*! @name CONF - Configuration */ 4281 #define TPM_CONF_DOZEEN_MASK (0x20U) 4282 #define TPM_CONF_DOZEEN_SHIFT (5U) 4283 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) 4284 #define TPM_CONF_DBGMODE_MASK (0xC0U) 4285 #define TPM_CONF_DBGMODE_SHIFT (6U) 4286 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) 4287 #define TPM_CONF_GTBEEN_MASK (0x200U) 4288 #define TPM_CONF_GTBEEN_SHIFT (9U) 4289 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) 4290 #define TPM_CONF_CSOT_MASK (0x10000U) 4291 #define TPM_CONF_CSOT_SHIFT (16U) 4292 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) 4293 #define TPM_CONF_CSOO_MASK (0x20000U) 4294 #define TPM_CONF_CSOO_SHIFT (17U) 4295 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) 4296 #define TPM_CONF_CROT_MASK (0x40000U) 4297 #define TPM_CONF_CROT_SHIFT (18U) 4298 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) 4299 #define TPM_CONF_TRGSEL_MASK (0xF000000U) 4300 #define TPM_CONF_TRGSEL_SHIFT (24U) 4301 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) 4302 4303 4304 /*! 4305 * @} 4306 */ /* end of group TPM_Register_Masks */ 4307 4308 4309 /* TPM - Peripheral instance base addresses */ 4310 /** Peripheral TPM0 base address */ 4311 #define TPM0_BASE (0x40038000u) 4312 /** Peripheral TPM0 base pointer */ 4313 #define TPM0 ((TPM_Type *)TPM0_BASE) 4314 /** Peripheral TPM1 base address */ 4315 #define TPM1_BASE (0x40039000u) 4316 /** Peripheral TPM1 base pointer */ 4317 #define TPM1 ((TPM_Type *)TPM1_BASE) 4318 /** Peripheral TPM2 base address */ 4319 #define TPM2_BASE (0x4003A000u) 4320 /** Peripheral TPM2 base pointer */ 4321 #define TPM2 ((TPM_Type *)TPM2_BASE) 4322 /** Array initializer of TPM peripheral base addresses */ 4323 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } 4324 /** Array initializer of TPM peripheral base pointers */ 4325 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } 4326 /** Interrupt vectors for the TPM peripheral type */ 4327 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } 4328 4329 /*! 4330 * @} 4331 */ /* end of group TPM_Peripheral_Access_Layer */ 4332 4333 4334 /* ---------------------------------------------------------------------------- 4335 -- TSI Peripheral Access Layer 4336 ---------------------------------------------------------------------------- */ 4337 4338 /*! 4339 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer 4340 * @{ 4341 */ 4342 4343 /** TSI - Register Layout Typedef */ 4344 typedef struct { 4345 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ 4346 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ 4347 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ 4348 } TSI_Type; 4349 4350 /* ---------------------------------------------------------------------------- 4351 -- TSI Register Masks 4352 ---------------------------------------------------------------------------- */ 4353 4354 /*! 4355 * @addtogroup TSI_Register_Masks TSI Register Masks 4356 * @{ 4357 */ 4358 4359 /*! @name GENCS - TSI General Control and Status Register */ 4360 #define TSI_GENCS_CURSW_MASK (0x2U) 4361 #define TSI_GENCS_CURSW_SHIFT (1U) 4362 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK) 4363 #define TSI_GENCS_EOSF_MASK (0x4U) 4364 #define TSI_GENCS_EOSF_SHIFT (2U) 4365 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) 4366 #define TSI_GENCS_SCNIP_MASK (0x8U) 4367 #define TSI_GENCS_SCNIP_SHIFT (3U) 4368 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) 4369 #define TSI_GENCS_STM_MASK (0x10U) 4370 #define TSI_GENCS_STM_SHIFT (4U) 4371 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) 4372 #define TSI_GENCS_STPE_MASK (0x20U) 4373 #define TSI_GENCS_STPE_SHIFT (5U) 4374 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) 4375 #define TSI_GENCS_TSIIEN_MASK (0x40U) 4376 #define TSI_GENCS_TSIIEN_SHIFT (6U) 4377 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK) 4378 #define TSI_GENCS_TSIEN_MASK (0x80U) 4379 #define TSI_GENCS_TSIEN_SHIFT (7U) 4380 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) 4381 #define TSI_GENCS_NSCN_MASK (0x1F00U) 4382 #define TSI_GENCS_NSCN_SHIFT (8U) 4383 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK) 4384 #define TSI_GENCS_PS_MASK (0xE000U) 4385 #define TSI_GENCS_PS_SHIFT (13U) 4386 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK) 4387 #define TSI_GENCS_EXTCHRG_MASK (0x70000U) 4388 #define TSI_GENCS_EXTCHRG_SHIFT (16U) 4389 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK) 4390 #define TSI_GENCS_DVOLT_MASK (0x180000U) 4391 #define TSI_GENCS_DVOLT_SHIFT (19U) 4392 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) 4393 #define TSI_GENCS_REFCHRG_MASK (0xE00000U) 4394 #define TSI_GENCS_REFCHRG_SHIFT (21U) 4395 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK) 4396 #define TSI_GENCS_MODE_MASK (0xF000000U) 4397 #define TSI_GENCS_MODE_SHIFT (24U) 4398 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK) 4399 #define TSI_GENCS_ESOR_MASK (0x10000000U) 4400 #define TSI_GENCS_ESOR_SHIFT (28U) 4401 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) 4402 #define TSI_GENCS_OUTRGF_MASK (0x80000000U) 4403 #define TSI_GENCS_OUTRGF_SHIFT (31U) 4404 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) 4405 4406 /*! @name DATA - TSI DATA Register */ 4407 #define TSI_DATA_TSICNT_MASK (0xFFFFU) 4408 #define TSI_DATA_TSICNT_SHIFT (0U) 4409 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) 4410 #define TSI_DATA_SWTS_MASK (0x400000U) 4411 #define TSI_DATA_SWTS_SHIFT (22U) 4412 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK) 4413 #define TSI_DATA_DMAEN_MASK (0x800000U) 4414 #define TSI_DATA_DMAEN_SHIFT (23U) 4415 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK) 4416 #define TSI_DATA_TSICH_MASK (0xF0000000U) 4417 #define TSI_DATA_TSICH_SHIFT (28U) 4418 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK) 4419 4420 /*! @name TSHD - TSI Threshold Register */ 4421 #define TSI_TSHD_THRESL_MASK (0xFFFFU) 4422 #define TSI_TSHD_THRESL_SHIFT (0U) 4423 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) 4424 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U) 4425 #define TSI_TSHD_THRESH_SHIFT (16U) 4426 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) 4427 4428 4429 /*! 4430 * @} 4431 */ /* end of group TSI_Register_Masks */ 4432 4433 4434 /* TSI - Peripheral instance base addresses */ 4435 /** Peripheral TSI0 base address */ 4436 #define TSI0_BASE (0x40045000u) 4437 /** Peripheral TSI0 base pointer */ 4438 #define TSI0 ((TSI_Type *)TSI0_BASE) 4439 /** Array initializer of TSI peripheral base addresses */ 4440 #define TSI_BASE_ADDRS { TSI0_BASE } 4441 /** Array initializer of TSI peripheral base pointers */ 4442 #define TSI_BASE_PTRS { TSI0 } 4443 /** Interrupt vectors for the TSI peripheral type */ 4444 #define TSI_IRQS { TSI0_IRQn } 4445 4446 /*! 4447 * @} 4448 */ /* end of group TSI_Peripheral_Access_Layer */ 4449 4450 4451 /* ---------------------------------------------------------------------------- 4452 -- UART Peripheral Access Layer 4453 ---------------------------------------------------------------------------- */ 4454 4455 /*! 4456 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 4457 * @{ 4458 */ 4459 4460 /** UART - Register Layout Typedef */ 4461 typedef struct { 4462 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 4463 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 4464 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 4465 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 4466 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 4467 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 4468 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 4469 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 4470 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */ 4471 } UART_Type; 4472 4473 /* ---------------------------------------------------------------------------- 4474 -- UART Register Masks 4475 ---------------------------------------------------------------------------- */ 4476 4477 /*! 4478 * @addtogroup UART_Register_Masks UART Register Masks 4479 * @{ 4480 */ 4481 4482 /*! @name BDH - UART Baud Rate Register: High */ 4483 #define UART_BDH_SBR_MASK (0x1FU) 4484 #define UART_BDH_SBR_SHIFT (0U) 4485 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 4486 #define UART_BDH_SBNS_MASK (0x20U) 4487 #define UART_BDH_SBNS_SHIFT (5U) 4488 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) 4489 #define UART_BDH_RXEDGIE_MASK (0x40U) 4490 #define UART_BDH_RXEDGIE_SHIFT (6U) 4491 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 4492 #define UART_BDH_LBKDIE_MASK (0x80U) 4493 #define UART_BDH_LBKDIE_SHIFT (7U) 4494 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) 4495 4496 /*! @name BDL - UART Baud Rate Register: Low */ 4497 #define UART_BDL_SBR_MASK (0xFFU) 4498 #define UART_BDL_SBR_SHIFT (0U) 4499 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 4500 4501 /*! @name C1 - UART Control Register 1 */ 4502 #define UART_C1_PT_MASK (0x1U) 4503 #define UART_C1_PT_SHIFT (0U) 4504 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 4505 #define UART_C1_PE_MASK (0x2U) 4506 #define UART_C1_PE_SHIFT (1U) 4507 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 4508 #define UART_C1_ILT_MASK (0x4U) 4509 #define UART_C1_ILT_SHIFT (2U) 4510 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 4511 #define UART_C1_WAKE_MASK (0x8U) 4512 #define UART_C1_WAKE_SHIFT (3U) 4513 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 4514 #define UART_C1_M_MASK (0x10U) 4515 #define UART_C1_M_SHIFT (4U) 4516 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 4517 #define UART_C1_RSRC_MASK (0x20U) 4518 #define UART_C1_RSRC_SHIFT (5U) 4519 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 4520 #define UART_C1_UARTSWAI_MASK (0x40U) 4521 #define UART_C1_UARTSWAI_SHIFT (6U) 4522 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) 4523 #define UART_C1_LOOPS_MASK (0x80U) 4524 #define UART_C1_LOOPS_SHIFT (7U) 4525 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 4526 4527 /*! @name C2 - UART Control Register 2 */ 4528 #define UART_C2_SBK_MASK (0x1U) 4529 #define UART_C2_SBK_SHIFT (0U) 4530 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 4531 #define UART_C2_RWU_MASK (0x2U) 4532 #define UART_C2_RWU_SHIFT (1U) 4533 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 4534 #define UART_C2_RE_MASK (0x4U) 4535 #define UART_C2_RE_SHIFT (2U) 4536 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 4537 #define UART_C2_TE_MASK (0x8U) 4538 #define UART_C2_TE_SHIFT (3U) 4539 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 4540 #define UART_C2_ILIE_MASK (0x10U) 4541 #define UART_C2_ILIE_SHIFT (4U) 4542 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 4543 #define UART_C2_RIE_MASK (0x20U) 4544 #define UART_C2_RIE_SHIFT (5U) 4545 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 4546 #define UART_C2_TCIE_MASK (0x40U) 4547 #define UART_C2_TCIE_SHIFT (6U) 4548 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 4549 #define UART_C2_TIE_MASK (0x80U) 4550 #define UART_C2_TIE_SHIFT (7U) 4551 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 4552 4553 /*! @name S1 - UART Status Register 1 */ 4554 #define UART_S1_PF_MASK (0x1U) 4555 #define UART_S1_PF_SHIFT (0U) 4556 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 4557 #define UART_S1_FE_MASK (0x2U) 4558 #define UART_S1_FE_SHIFT (1U) 4559 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 4560 #define UART_S1_NF_MASK (0x4U) 4561 #define UART_S1_NF_SHIFT (2U) 4562 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 4563 #define UART_S1_OR_MASK (0x8U) 4564 #define UART_S1_OR_SHIFT (3U) 4565 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 4566 #define UART_S1_IDLE_MASK (0x10U) 4567 #define UART_S1_IDLE_SHIFT (4U) 4568 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 4569 #define UART_S1_RDRF_MASK (0x20U) 4570 #define UART_S1_RDRF_SHIFT (5U) 4571 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 4572 #define UART_S1_TC_MASK (0x40U) 4573 #define UART_S1_TC_SHIFT (6U) 4574 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 4575 #define UART_S1_TDRE_MASK (0x80U) 4576 #define UART_S1_TDRE_SHIFT (7U) 4577 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 4578 4579 /*! @name S2 - UART Status Register 2 */ 4580 #define UART_S2_RAF_MASK (0x1U) 4581 #define UART_S2_RAF_SHIFT (0U) 4582 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 4583 #define UART_S2_LBKDE_MASK (0x2U) 4584 #define UART_S2_LBKDE_SHIFT (1U) 4585 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) 4586 #define UART_S2_BRK13_MASK (0x4U) 4587 #define UART_S2_BRK13_SHIFT (2U) 4588 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 4589 #define UART_S2_RWUID_MASK (0x8U) 4590 #define UART_S2_RWUID_SHIFT (3U) 4591 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 4592 #define UART_S2_RXINV_MASK (0x10U) 4593 #define UART_S2_RXINV_SHIFT (4U) 4594 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 4595 #define UART_S2_RXEDGIF_MASK (0x40U) 4596 #define UART_S2_RXEDGIF_SHIFT (6U) 4597 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 4598 #define UART_S2_LBKDIF_MASK (0x80U) 4599 #define UART_S2_LBKDIF_SHIFT (7U) 4600 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) 4601 4602 /*! @name C3 - UART Control Register 3 */ 4603 #define UART_C3_PEIE_MASK (0x1U) 4604 #define UART_C3_PEIE_SHIFT (0U) 4605 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 4606 #define UART_C3_FEIE_MASK (0x2U) 4607 #define UART_C3_FEIE_SHIFT (1U) 4608 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 4609 #define UART_C3_NEIE_MASK (0x4U) 4610 #define UART_C3_NEIE_SHIFT (2U) 4611 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 4612 #define UART_C3_ORIE_MASK (0x8U) 4613 #define UART_C3_ORIE_SHIFT (3U) 4614 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 4615 #define UART_C3_TXINV_MASK (0x10U) 4616 #define UART_C3_TXINV_SHIFT (4U) 4617 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 4618 #define UART_C3_TXDIR_MASK (0x20U) 4619 #define UART_C3_TXDIR_SHIFT (5U) 4620 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 4621 #define UART_C3_T8_MASK (0x40U) 4622 #define UART_C3_T8_SHIFT (6U) 4623 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 4624 #define UART_C3_R8_MASK (0x80U) 4625 #define UART_C3_R8_SHIFT (7U) 4626 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 4627 4628 /*! @name D - UART Data Register */ 4629 #define UART_D_R0T0_MASK (0x1U) 4630 #define UART_D_R0T0_SHIFT (0U) 4631 #define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK) 4632 #define UART_D_R1T1_MASK (0x2U) 4633 #define UART_D_R1T1_SHIFT (1U) 4634 #define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK) 4635 #define UART_D_R2T2_MASK (0x4U) 4636 #define UART_D_R2T2_SHIFT (2U) 4637 #define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK) 4638 #define UART_D_R3T3_MASK (0x8U) 4639 #define UART_D_R3T3_SHIFT (3U) 4640 #define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK) 4641 #define UART_D_R4T4_MASK (0x10U) 4642 #define UART_D_R4T4_SHIFT (4U) 4643 #define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK) 4644 #define UART_D_R5T5_MASK (0x20U) 4645 #define UART_D_R5T5_SHIFT (5U) 4646 #define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK) 4647 #define UART_D_R6T6_MASK (0x40U) 4648 #define UART_D_R6T6_SHIFT (6U) 4649 #define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK) 4650 #define UART_D_R7T7_MASK (0x80U) 4651 #define UART_D_R7T7_SHIFT (7U) 4652 #define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK) 4653 4654 /*! @name C4 - UART Control Register 4 */ 4655 #define UART_C4_RDMAS_MASK (0x20U) 4656 #define UART_C4_RDMAS_SHIFT (5U) 4657 #define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_RDMAS_SHIFT)) & UART_C4_RDMAS_MASK) 4658 #define UART_C4_TDMAS_MASK (0x80U) 4659 #define UART_C4_TDMAS_SHIFT (7U) 4660 #define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_TDMAS_SHIFT)) & UART_C4_TDMAS_MASK) 4661 4662 4663 /*! 4664 * @} 4665 */ /* end of group UART_Register_Masks */ 4666 4667 4668 /* UART - Peripheral instance base addresses */ 4669 /** Peripheral UART1 base address */ 4670 #define UART1_BASE (0x4006B000u) 4671 /** Peripheral UART1 base pointer */ 4672 #define UART1 ((UART_Type *)UART1_BASE) 4673 /** Peripheral UART2 base address */ 4674 #define UART2_BASE (0x4006C000u) 4675 /** Peripheral UART2 base pointer */ 4676 #define UART2 ((UART_Type *)UART2_BASE) 4677 /** Array initializer of UART peripheral base addresses */ 4678 #define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE } 4679 /** Array initializer of UART peripheral base pointers */ 4680 #define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2 } 4681 /** Interrupt vectors for the UART peripheral type */ 4682 #define UART_RX_TX_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn } 4683 #define UART_ERR_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn } 4684 4685 /*! 4686 * @} 4687 */ /* end of group UART_Peripheral_Access_Layer */ 4688 4689 4690 /* ---------------------------------------------------------------------------- 4691 -- UART0 Peripheral Access Layer 4692 ---------------------------------------------------------------------------- */ 4693 4694 /*! 4695 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer 4696 * @{ 4697 */ 4698 4699 /** UART0 - Register Layout Typedef */ 4700 typedef struct { 4701 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */ 4702 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */ 4703 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 4704 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 4705 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 4706 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 4707 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 4708 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 4709 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 4710 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 4711 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 4712 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 4713 } UART0_Type; 4714 4715 /* ---------------------------------------------------------------------------- 4716 -- UART0 Register Masks 4717 ---------------------------------------------------------------------------- */ 4718 4719 /*! 4720 * @addtogroup UART0_Register_Masks UART0 Register Masks 4721 * @{ 4722 */ 4723 4724 /*! @name BDH - UART Baud Rate Register High */ 4725 #define UART0_BDH_SBR_MASK (0x1FU) 4726 #define UART0_BDH_SBR_SHIFT (0U) 4727 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBR_SHIFT)) & UART0_BDH_SBR_MASK) 4728 #define UART0_BDH_SBNS_MASK (0x20U) 4729 #define UART0_BDH_SBNS_SHIFT (5U) 4730 #define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBNS_SHIFT)) & UART0_BDH_SBNS_MASK) 4731 #define UART0_BDH_RXEDGIE_MASK (0x40U) 4732 #define UART0_BDH_RXEDGIE_SHIFT (6U) 4733 #define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_RXEDGIE_SHIFT)) & UART0_BDH_RXEDGIE_MASK) 4734 #define UART0_BDH_LBKDIE_MASK (0x80U) 4735 #define UART0_BDH_LBKDIE_SHIFT (7U) 4736 #define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_LBKDIE_SHIFT)) & UART0_BDH_LBKDIE_MASK) 4737 4738 /*! @name BDL - UART Baud Rate Register Low */ 4739 #define UART0_BDL_SBR_MASK (0xFFU) 4740 #define UART0_BDL_SBR_SHIFT (0U) 4741 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDL_SBR_SHIFT)) & UART0_BDL_SBR_MASK) 4742 4743 /*! @name C1 - UART Control Register 1 */ 4744 #define UART0_C1_PT_MASK (0x1U) 4745 #define UART0_C1_PT_SHIFT (0U) 4746 #define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PT_SHIFT)) & UART0_C1_PT_MASK) 4747 #define UART0_C1_PE_MASK (0x2U) 4748 #define UART0_C1_PE_SHIFT (1U) 4749 #define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PE_SHIFT)) & UART0_C1_PE_MASK) 4750 #define UART0_C1_ILT_MASK (0x4U) 4751 #define UART0_C1_ILT_SHIFT (2U) 4752 #define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_ILT_SHIFT)) & UART0_C1_ILT_MASK) 4753 #define UART0_C1_WAKE_MASK (0x8U) 4754 #define UART0_C1_WAKE_SHIFT (3U) 4755 #define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_WAKE_SHIFT)) & UART0_C1_WAKE_MASK) 4756 #define UART0_C1_M_MASK (0x10U) 4757 #define UART0_C1_M_SHIFT (4U) 4758 #define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_M_SHIFT)) & UART0_C1_M_MASK) 4759 #define UART0_C1_RSRC_MASK (0x20U) 4760 #define UART0_C1_RSRC_SHIFT (5U) 4761 #define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_RSRC_SHIFT)) & UART0_C1_RSRC_MASK) 4762 #define UART0_C1_DOZEEN_MASK (0x40U) 4763 #define UART0_C1_DOZEEN_SHIFT (6U) 4764 #define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_DOZEEN_SHIFT)) & UART0_C1_DOZEEN_MASK) 4765 #define UART0_C1_LOOPS_MASK (0x80U) 4766 #define UART0_C1_LOOPS_SHIFT (7U) 4767 #define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_LOOPS_SHIFT)) & UART0_C1_LOOPS_MASK) 4768 4769 /*! @name C2 - UART Control Register 2 */ 4770 #define UART0_C2_SBK_MASK (0x1U) 4771 #define UART0_C2_SBK_SHIFT (0U) 4772 #define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_SBK_SHIFT)) & UART0_C2_SBK_MASK) 4773 #define UART0_C2_RWU_MASK (0x2U) 4774 #define UART0_C2_RWU_SHIFT (1U) 4775 #define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RWU_SHIFT)) & UART0_C2_RWU_MASK) 4776 #define UART0_C2_RE_MASK (0x4U) 4777 #define UART0_C2_RE_SHIFT (2U) 4778 #define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RE_SHIFT)) & UART0_C2_RE_MASK) 4779 #define UART0_C2_TE_MASK (0x8U) 4780 #define UART0_C2_TE_SHIFT (3U) 4781 #define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TE_SHIFT)) & UART0_C2_TE_MASK) 4782 #define UART0_C2_ILIE_MASK (0x10U) 4783 #define UART0_C2_ILIE_SHIFT (4U) 4784 #define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_ILIE_SHIFT)) & UART0_C2_ILIE_MASK) 4785 #define UART0_C2_RIE_MASK (0x20U) 4786 #define UART0_C2_RIE_SHIFT (5U) 4787 #define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RIE_SHIFT)) & UART0_C2_RIE_MASK) 4788 #define UART0_C2_TCIE_MASK (0x40U) 4789 #define UART0_C2_TCIE_SHIFT (6U) 4790 #define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TCIE_SHIFT)) & UART0_C2_TCIE_MASK) 4791 #define UART0_C2_TIE_MASK (0x80U) 4792 #define UART0_C2_TIE_SHIFT (7U) 4793 #define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TIE_SHIFT)) & UART0_C2_TIE_MASK) 4794 4795 /*! @name S1 - UART Status Register 1 */ 4796 #define UART0_S1_PF_MASK (0x1U) 4797 #define UART0_S1_PF_SHIFT (0U) 4798 #define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_PF_SHIFT)) & UART0_S1_PF_MASK) 4799 #define UART0_S1_FE_MASK (0x2U) 4800 #define UART0_S1_FE_SHIFT (1U) 4801 #define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_FE_SHIFT)) & UART0_S1_FE_MASK) 4802 #define UART0_S1_NF_MASK (0x4U) 4803 #define UART0_S1_NF_SHIFT (2U) 4804 #define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_NF_SHIFT)) & UART0_S1_NF_MASK) 4805 #define UART0_S1_OR_MASK (0x8U) 4806 #define UART0_S1_OR_SHIFT (3U) 4807 #define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_OR_SHIFT)) & UART0_S1_OR_MASK) 4808 #define UART0_S1_IDLE_MASK (0x10U) 4809 #define UART0_S1_IDLE_SHIFT (4U) 4810 #define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_IDLE_SHIFT)) & UART0_S1_IDLE_MASK) 4811 #define UART0_S1_RDRF_MASK (0x20U) 4812 #define UART0_S1_RDRF_SHIFT (5U) 4813 #define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_RDRF_SHIFT)) & UART0_S1_RDRF_MASK) 4814 #define UART0_S1_TC_MASK (0x40U) 4815 #define UART0_S1_TC_SHIFT (6U) 4816 #define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TC_SHIFT)) & UART0_S1_TC_MASK) 4817 #define UART0_S1_TDRE_MASK (0x80U) 4818 #define UART0_S1_TDRE_SHIFT (7U) 4819 #define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TDRE_SHIFT)) & UART0_S1_TDRE_MASK) 4820 4821 /*! @name S2 - UART Status Register 2 */ 4822 #define UART0_S2_RAF_MASK (0x1U) 4823 #define UART0_S2_RAF_SHIFT (0U) 4824 #define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RAF_SHIFT)) & UART0_S2_RAF_MASK) 4825 #define UART0_S2_LBKDE_MASK (0x2U) 4826 #define UART0_S2_LBKDE_SHIFT (1U) 4827 #define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDE_SHIFT)) & UART0_S2_LBKDE_MASK) 4828 #define UART0_S2_BRK13_MASK (0x4U) 4829 #define UART0_S2_BRK13_SHIFT (2U) 4830 #define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_BRK13_SHIFT)) & UART0_S2_BRK13_MASK) 4831 #define UART0_S2_RWUID_MASK (0x8U) 4832 #define UART0_S2_RWUID_SHIFT (3U) 4833 #define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RWUID_SHIFT)) & UART0_S2_RWUID_MASK) 4834 #define UART0_S2_RXINV_MASK (0x10U) 4835 #define UART0_S2_RXINV_SHIFT (4U) 4836 #define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXINV_SHIFT)) & UART0_S2_RXINV_MASK) 4837 #define UART0_S2_MSBF_MASK (0x20U) 4838 #define UART0_S2_MSBF_SHIFT (5U) 4839 #define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_MSBF_SHIFT)) & UART0_S2_MSBF_MASK) 4840 #define UART0_S2_RXEDGIF_MASK (0x40U) 4841 #define UART0_S2_RXEDGIF_SHIFT (6U) 4842 #define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXEDGIF_SHIFT)) & UART0_S2_RXEDGIF_MASK) 4843 #define UART0_S2_LBKDIF_MASK (0x80U) 4844 #define UART0_S2_LBKDIF_SHIFT (7U) 4845 #define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDIF_SHIFT)) & UART0_S2_LBKDIF_MASK) 4846 4847 /*! @name C3 - UART Control Register 3 */ 4848 #define UART0_C3_PEIE_MASK (0x1U) 4849 #define UART0_C3_PEIE_SHIFT (0U) 4850 #define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_PEIE_SHIFT)) & UART0_C3_PEIE_MASK) 4851 #define UART0_C3_FEIE_MASK (0x2U) 4852 #define UART0_C3_FEIE_SHIFT (1U) 4853 #define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_FEIE_SHIFT)) & UART0_C3_FEIE_MASK) 4854 #define UART0_C3_NEIE_MASK (0x4U) 4855 #define UART0_C3_NEIE_SHIFT (2U) 4856 #define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_NEIE_SHIFT)) & UART0_C3_NEIE_MASK) 4857 #define UART0_C3_ORIE_MASK (0x8U) 4858 #define UART0_C3_ORIE_SHIFT (3U) 4859 #define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_ORIE_SHIFT)) & UART0_C3_ORIE_MASK) 4860 #define UART0_C3_TXINV_MASK (0x10U) 4861 #define UART0_C3_TXINV_SHIFT (4U) 4862 #define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXINV_SHIFT)) & UART0_C3_TXINV_MASK) 4863 #define UART0_C3_TXDIR_MASK (0x20U) 4864 #define UART0_C3_TXDIR_SHIFT (5U) 4865 #define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXDIR_SHIFT)) & UART0_C3_TXDIR_MASK) 4866 #define UART0_C3_R9T8_MASK (0x40U) 4867 #define UART0_C3_R9T8_SHIFT (6U) 4868 #define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R9T8_SHIFT)) & UART0_C3_R9T8_MASK) 4869 #define UART0_C3_R8T9_MASK (0x80U) 4870 #define UART0_C3_R8T9_SHIFT (7U) 4871 #define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R8T9_SHIFT)) & UART0_C3_R8T9_MASK) 4872 4873 /*! @name D - UART Data Register */ 4874 #define UART0_D_R0T0_MASK (0x1U) 4875 #define UART0_D_R0T0_SHIFT (0U) 4876 #define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R0T0_SHIFT)) & UART0_D_R0T0_MASK) 4877 #define UART0_D_R1T1_MASK (0x2U) 4878 #define UART0_D_R1T1_SHIFT (1U) 4879 #define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R1T1_SHIFT)) & UART0_D_R1T1_MASK) 4880 #define UART0_D_R2T2_MASK (0x4U) 4881 #define UART0_D_R2T2_SHIFT (2U) 4882 #define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R2T2_SHIFT)) & UART0_D_R2T2_MASK) 4883 #define UART0_D_R3T3_MASK (0x8U) 4884 #define UART0_D_R3T3_SHIFT (3U) 4885 #define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R3T3_SHIFT)) & UART0_D_R3T3_MASK) 4886 #define UART0_D_R4T4_MASK (0x10U) 4887 #define UART0_D_R4T4_SHIFT (4U) 4888 #define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R4T4_SHIFT)) & UART0_D_R4T4_MASK) 4889 #define UART0_D_R5T5_MASK (0x20U) 4890 #define UART0_D_R5T5_SHIFT (5U) 4891 #define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R5T5_SHIFT)) & UART0_D_R5T5_MASK) 4892 #define UART0_D_R6T6_MASK (0x40U) 4893 #define UART0_D_R6T6_SHIFT (6U) 4894 #define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R6T6_SHIFT)) & UART0_D_R6T6_MASK) 4895 #define UART0_D_R7T7_MASK (0x80U) 4896 #define UART0_D_R7T7_SHIFT (7U) 4897 #define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R7T7_SHIFT)) & UART0_D_R7T7_MASK) 4898 4899 /*! @name MA1 - UART Match Address Registers 1 */ 4900 #define UART0_MA1_MA_MASK (0xFFU) 4901 #define UART0_MA1_MA_SHIFT (0U) 4902 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA1_MA_SHIFT)) & UART0_MA1_MA_MASK) 4903 4904 /*! @name MA2 - UART Match Address Registers 2 */ 4905 #define UART0_MA2_MA_MASK (0xFFU) 4906 #define UART0_MA2_MA_SHIFT (0U) 4907 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA2_MA_SHIFT)) & UART0_MA2_MA_MASK) 4908 4909 /*! @name C4 - UART Control Register 4 */ 4910 #define UART0_C4_OSR_MASK (0x1FU) 4911 #define UART0_C4_OSR_SHIFT (0U) 4912 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_OSR_SHIFT)) & UART0_C4_OSR_MASK) 4913 #define UART0_C4_M10_MASK (0x20U) 4914 #define UART0_C4_M10_SHIFT (5U) 4915 #define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_M10_SHIFT)) & UART0_C4_M10_MASK) 4916 #define UART0_C4_MAEN2_MASK (0x40U) 4917 #define UART0_C4_MAEN2_SHIFT (6U) 4918 #define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN2_SHIFT)) & UART0_C4_MAEN2_MASK) 4919 #define UART0_C4_MAEN1_MASK (0x80U) 4920 #define UART0_C4_MAEN1_SHIFT (7U) 4921 #define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN1_SHIFT)) & UART0_C4_MAEN1_MASK) 4922 4923 /*! @name C5 - UART Control Register 5 */ 4924 #define UART0_C5_RESYNCDIS_MASK (0x1U) 4925 #define UART0_C5_RESYNCDIS_SHIFT (0U) 4926 #define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RESYNCDIS_SHIFT)) & UART0_C5_RESYNCDIS_MASK) 4927 #define UART0_C5_BOTHEDGE_MASK (0x2U) 4928 #define UART0_C5_BOTHEDGE_SHIFT (1U) 4929 #define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_BOTHEDGE_SHIFT)) & UART0_C5_BOTHEDGE_MASK) 4930 #define UART0_C5_RDMAE_MASK (0x20U) 4931 #define UART0_C5_RDMAE_SHIFT (5U) 4932 #define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RDMAE_SHIFT)) & UART0_C5_RDMAE_MASK) 4933 #define UART0_C5_TDMAE_MASK (0x80U) 4934 #define UART0_C5_TDMAE_SHIFT (7U) 4935 #define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_TDMAE_SHIFT)) & UART0_C5_TDMAE_MASK) 4936 4937 4938 /*! 4939 * @} 4940 */ /* end of group UART0_Register_Masks */ 4941 4942 4943 /* UART0 - Peripheral instance base addresses */ 4944 /** Peripheral UART0 base address */ 4945 #define UART0_BASE (0x4006A000u) 4946 /** Peripheral UART0 base pointer */ 4947 #define UART0 ((UART0_Type *)UART0_BASE) 4948 /** Array initializer of UART0 peripheral base addresses */ 4949 #define UART0_BASE_ADDRS { UART0_BASE } 4950 /** Array initializer of UART0 peripheral base pointers */ 4951 #define UART0_BASE_PTRS { UART0 } 4952 /** Interrupt vectors for the UART0 peripheral type */ 4953 #define UART0_RX_TX_IRQS { UART0_IRQn } 4954 #define UART0_ERR_IRQS { UART0_IRQn } 4955 4956 /*! 4957 * @} 4958 */ /* end of group UART0_Peripheral_Access_Layer */ 4959 4960 4961 /* ---------------------------------------------------------------------------- 4962 -- USB Peripheral Access Layer 4963 ---------------------------------------------------------------------------- */ 4964 4965 /*! 4966 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 4967 * @{ 4968 */ 4969 4970 /** USB - Register Layout Typedef */ 4971 typedef struct { 4972 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ 4973 uint8_t RESERVED_0[3]; 4974 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ 4975 uint8_t RESERVED_1[3]; 4976 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ 4977 uint8_t RESERVED_2[3]; 4978 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ 4979 uint8_t RESERVED_3[3]; 4980 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ 4981 uint8_t RESERVED_4[3]; 4982 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ 4983 uint8_t RESERVED_5[3]; 4984 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ 4985 uint8_t RESERVED_6[3]; 4986 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ 4987 uint8_t RESERVED_7[99]; 4988 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ 4989 uint8_t RESERVED_8[3]; 4990 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ 4991 uint8_t RESERVED_9[3]; 4992 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ 4993 uint8_t RESERVED_10[3]; 4994 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ 4995 uint8_t RESERVED_11[3]; 4996 __I uint8_t STAT; /**< Status register, offset: 0x90 */ 4997 uint8_t RESERVED_12[3]; 4998 __IO uint8_t CTL; /**< Control register, offset: 0x94 */ 4999 uint8_t RESERVED_13[3]; 5000 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ 5001 uint8_t RESERVED_14[3]; 5002 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ 5003 uint8_t RESERVED_15[3]; 5004 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ 5005 uint8_t RESERVED_16[3]; 5006 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ 5007 uint8_t RESERVED_17[3]; 5008 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ 5009 uint8_t RESERVED_18[3]; 5010 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ 5011 uint8_t RESERVED_19[3]; 5012 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 5013 uint8_t RESERVED_20[3]; 5014 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 5015 uint8_t RESERVED_21[11]; 5016 struct { /* offset: 0xC0, array step: 0x4 */ 5017 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ 5018 uint8_t RESERVED_0[3]; 5019 } ENDPOINT[16]; 5020 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ 5021 uint8_t RESERVED_22[3]; 5022 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ 5023 uint8_t RESERVED_23[3]; 5024 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ 5025 uint8_t RESERVED_24[3]; 5026 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ 5027 uint8_t RESERVED_25[7]; 5028 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ 5029 } USB_Type; 5030 5031 /* ---------------------------------------------------------------------------- 5032 -- USB Register Masks 5033 ---------------------------------------------------------------------------- */ 5034 5035 /*! 5036 * @addtogroup USB_Register_Masks USB Register Masks 5037 * @{ 5038 */ 5039 5040 /*! @name PERID - Peripheral ID register */ 5041 #define USB_PERID_ID_MASK (0x3FU) 5042 #define USB_PERID_ID_SHIFT (0U) 5043 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) 5044 5045 /*! @name IDCOMP - Peripheral ID Complement register */ 5046 #define USB_IDCOMP_NID_MASK (0x3FU) 5047 #define USB_IDCOMP_NID_SHIFT (0U) 5048 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) 5049 5050 /*! @name REV - Peripheral Revision register */ 5051 #define USB_REV_REV_MASK (0xFFU) 5052 #define USB_REV_REV_SHIFT (0U) 5053 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) 5054 5055 /*! @name ADDINFO - Peripheral Additional Info register */ 5056 #define USB_ADDINFO_IEHOST_MASK (0x1U) 5057 #define USB_ADDINFO_IEHOST_SHIFT (0U) 5058 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) 5059 #define USB_ADDINFO_IRQNUM_MASK (0xF8U) 5060 #define USB_ADDINFO_IRQNUM_SHIFT (3U) 5061 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) 5062 5063 /*! @name OTGISTAT - OTG Interrupt Status register */ 5064 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) 5065 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) 5066 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) 5067 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) 5068 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) 5069 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) 5070 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) 5071 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) 5072 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) 5073 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) 5074 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) 5075 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) 5076 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) 5077 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) 5078 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) 5079 #define USB_OTGISTAT_IDCHG_MASK (0x80U) 5080 #define USB_OTGISTAT_IDCHG_SHIFT (7U) 5081 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) 5082 5083 /*! @name OTGICR - OTG Interrupt Control Register */ 5084 #define USB_OTGICR_AVBUSEN_MASK (0x1U) 5085 #define USB_OTGICR_AVBUSEN_SHIFT (0U) 5086 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) 5087 #define USB_OTGICR_BSESSEN_MASK (0x4U) 5088 #define USB_OTGICR_BSESSEN_SHIFT (2U) 5089 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) 5090 #define USB_OTGICR_SESSVLDEN_MASK (0x8U) 5091 #define USB_OTGICR_SESSVLDEN_SHIFT (3U) 5092 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) 5093 #define USB_OTGICR_LINESTATEEN_MASK (0x20U) 5094 #define USB_OTGICR_LINESTATEEN_SHIFT (5U) 5095 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) 5096 #define USB_OTGICR_ONEMSECEN_MASK (0x40U) 5097 #define USB_OTGICR_ONEMSECEN_SHIFT (6U) 5098 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) 5099 #define USB_OTGICR_IDEN_MASK (0x80U) 5100 #define USB_OTGICR_IDEN_SHIFT (7U) 5101 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) 5102 5103 /*! @name OTGSTAT - OTG Status register */ 5104 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) 5105 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) 5106 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) 5107 #define USB_OTGSTAT_BSESSEND_MASK (0x4U) 5108 #define USB_OTGSTAT_BSESSEND_SHIFT (2U) 5109 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) 5110 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U) 5111 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U) 5112 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) 5113 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) 5114 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) 5115 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) 5116 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) 5117 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) 5118 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) 5119 #define USB_OTGSTAT_ID_MASK (0x80U) 5120 #define USB_OTGSTAT_ID_SHIFT (7U) 5121 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) 5122 5123 /*! @name OTGCTL - OTG Control register */ 5124 #define USB_OTGCTL_OTGEN_MASK (0x4U) 5125 #define USB_OTGCTL_OTGEN_SHIFT (2U) 5126 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) 5127 #define USB_OTGCTL_DMLOW_MASK (0x10U) 5128 #define USB_OTGCTL_DMLOW_SHIFT (4U) 5129 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) 5130 #define USB_OTGCTL_DPLOW_MASK (0x20U) 5131 #define USB_OTGCTL_DPLOW_SHIFT (5U) 5132 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) 5133 #define USB_OTGCTL_DPHIGH_MASK (0x80U) 5134 #define USB_OTGCTL_DPHIGH_SHIFT (7U) 5135 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) 5136 5137 /*! @name ISTAT - Interrupt Status register */ 5138 #define USB_ISTAT_USBRST_MASK (0x1U) 5139 #define USB_ISTAT_USBRST_SHIFT (0U) 5140 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) 5141 #define USB_ISTAT_ERROR_MASK (0x2U) 5142 #define USB_ISTAT_ERROR_SHIFT (1U) 5143 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) 5144 #define USB_ISTAT_SOFTOK_MASK (0x4U) 5145 #define USB_ISTAT_SOFTOK_SHIFT (2U) 5146 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) 5147 #define USB_ISTAT_TOKDNE_MASK (0x8U) 5148 #define USB_ISTAT_TOKDNE_SHIFT (3U) 5149 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) 5150 #define USB_ISTAT_SLEEP_MASK (0x10U) 5151 #define USB_ISTAT_SLEEP_SHIFT (4U) 5152 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) 5153 #define USB_ISTAT_RESUME_MASK (0x20U) 5154 #define USB_ISTAT_RESUME_SHIFT (5U) 5155 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) 5156 #define USB_ISTAT_ATTACH_MASK (0x40U) 5157 #define USB_ISTAT_ATTACH_SHIFT (6U) 5158 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) 5159 #define USB_ISTAT_STALL_MASK (0x80U) 5160 #define USB_ISTAT_STALL_SHIFT (7U) 5161 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) 5162 5163 /*! @name INTEN - Interrupt Enable register */ 5164 #define USB_INTEN_USBRSTEN_MASK (0x1U) 5165 #define USB_INTEN_USBRSTEN_SHIFT (0U) 5166 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) 5167 #define USB_INTEN_ERROREN_MASK (0x2U) 5168 #define USB_INTEN_ERROREN_SHIFT (1U) 5169 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) 5170 #define USB_INTEN_SOFTOKEN_MASK (0x4U) 5171 #define USB_INTEN_SOFTOKEN_SHIFT (2U) 5172 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) 5173 #define USB_INTEN_TOKDNEEN_MASK (0x8U) 5174 #define USB_INTEN_TOKDNEEN_SHIFT (3U) 5175 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) 5176 #define USB_INTEN_SLEEPEN_MASK (0x10U) 5177 #define USB_INTEN_SLEEPEN_SHIFT (4U) 5178 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) 5179 #define USB_INTEN_RESUMEEN_MASK (0x20U) 5180 #define USB_INTEN_RESUMEEN_SHIFT (5U) 5181 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) 5182 #define USB_INTEN_ATTACHEN_MASK (0x40U) 5183 #define USB_INTEN_ATTACHEN_SHIFT (6U) 5184 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) 5185 #define USB_INTEN_STALLEN_MASK (0x80U) 5186 #define USB_INTEN_STALLEN_SHIFT (7U) 5187 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) 5188 5189 /*! @name ERRSTAT - Error Interrupt Status register */ 5190 #define USB_ERRSTAT_PIDERR_MASK (0x1U) 5191 #define USB_ERRSTAT_PIDERR_SHIFT (0U) 5192 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) 5193 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) 5194 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) 5195 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) 5196 #define USB_ERRSTAT_CRC16_MASK (0x4U) 5197 #define USB_ERRSTAT_CRC16_SHIFT (2U) 5198 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) 5199 #define USB_ERRSTAT_DFN8_MASK (0x8U) 5200 #define USB_ERRSTAT_DFN8_SHIFT (3U) 5201 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) 5202 #define USB_ERRSTAT_BTOERR_MASK (0x10U) 5203 #define USB_ERRSTAT_BTOERR_SHIFT (4U) 5204 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) 5205 #define USB_ERRSTAT_DMAERR_MASK (0x20U) 5206 #define USB_ERRSTAT_DMAERR_SHIFT (5U) 5207 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) 5208 #define USB_ERRSTAT_BTSERR_MASK (0x80U) 5209 #define USB_ERRSTAT_BTSERR_SHIFT (7U) 5210 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) 5211 5212 /*! @name ERREN - Error Interrupt Enable register */ 5213 #define USB_ERREN_PIDERREN_MASK (0x1U) 5214 #define USB_ERREN_PIDERREN_SHIFT (0U) 5215 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) 5216 #define USB_ERREN_CRC5EOFEN_MASK (0x2U) 5217 #define USB_ERREN_CRC5EOFEN_SHIFT (1U) 5218 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) 5219 #define USB_ERREN_CRC16EN_MASK (0x4U) 5220 #define USB_ERREN_CRC16EN_SHIFT (2U) 5221 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) 5222 #define USB_ERREN_DFN8EN_MASK (0x8U) 5223 #define USB_ERREN_DFN8EN_SHIFT (3U) 5224 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) 5225 #define USB_ERREN_BTOERREN_MASK (0x10U) 5226 #define USB_ERREN_BTOERREN_SHIFT (4U) 5227 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) 5228 #define USB_ERREN_DMAERREN_MASK (0x20U) 5229 #define USB_ERREN_DMAERREN_SHIFT (5U) 5230 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) 5231 #define USB_ERREN_BTSERREN_MASK (0x80U) 5232 #define USB_ERREN_BTSERREN_SHIFT (7U) 5233 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) 5234 5235 /*! @name STAT - Status register */ 5236 #define USB_STAT_ODD_MASK (0x4U) 5237 #define USB_STAT_ODD_SHIFT (2U) 5238 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) 5239 #define USB_STAT_TX_MASK (0x8U) 5240 #define USB_STAT_TX_SHIFT (3U) 5241 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) 5242 #define USB_STAT_ENDP_MASK (0xF0U) 5243 #define USB_STAT_ENDP_SHIFT (4U) 5244 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) 5245 5246 /*! @name CTL - Control register */ 5247 #define USB_CTL_USBENSOFEN_MASK (0x1U) 5248 #define USB_CTL_USBENSOFEN_SHIFT (0U) 5249 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) 5250 #define USB_CTL_ODDRST_MASK (0x2U) 5251 #define USB_CTL_ODDRST_SHIFT (1U) 5252 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) 5253 #define USB_CTL_RESUME_MASK (0x4U) 5254 #define USB_CTL_RESUME_SHIFT (2U) 5255 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) 5256 #define USB_CTL_HOSTMODEEN_MASK (0x8U) 5257 #define USB_CTL_HOSTMODEEN_SHIFT (3U) 5258 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) 5259 #define USB_CTL_RESET_MASK (0x10U) 5260 #define USB_CTL_RESET_SHIFT (4U) 5261 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) 5262 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) 5263 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) 5264 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) 5265 #define USB_CTL_SE0_MASK (0x40U) 5266 #define USB_CTL_SE0_SHIFT (6U) 5267 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) 5268 #define USB_CTL_JSTATE_MASK (0x80U) 5269 #define USB_CTL_JSTATE_SHIFT (7U) 5270 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) 5271 5272 /*! @name ADDR - Address register */ 5273 #define USB_ADDR_ADDR_MASK (0x7FU) 5274 #define USB_ADDR_ADDR_SHIFT (0U) 5275 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) 5276 #define USB_ADDR_LSEN_MASK (0x80U) 5277 #define USB_ADDR_LSEN_SHIFT (7U) 5278 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) 5279 5280 /*! @name BDTPAGE1 - BDT Page Register 1 */ 5281 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) 5282 #define USB_BDTPAGE1_BDTBA_SHIFT (1U) 5283 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) 5284 5285 /*! @name FRMNUML - Frame Number Register Low */ 5286 #define USB_FRMNUML_FRM_MASK (0xFFU) 5287 #define USB_FRMNUML_FRM_SHIFT (0U) 5288 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) 5289 5290 /*! @name FRMNUMH - Frame Number Register High */ 5291 #define USB_FRMNUMH_FRM_MASK (0x7U) 5292 #define USB_FRMNUMH_FRM_SHIFT (0U) 5293 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) 5294 5295 /*! @name TOKEN - Token register */ 5296 #define USB_TOKEN_TOKENENDPT_MASK (0xFU) 5297 #define USB_TOKEN_TOKENENDPT_SHIFT (0U) 5298 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) 5299 #define USB_TOKEN_TOKENPID_MASK (0xF0U) 5300 #define USB_TOKEN_TOKENPID_SHIFT (4U) 5301 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) 5302 5303 /*! @name SOFTHLD - SOF Threshold Register */ 5304 #define USB_SOFTHLD_CNT_MASK (0xFFU) 5305 #define USB_SOFTHLD_CNT_SHIFT (0U) 5306 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) 5307 5308 /*! @name BDTPAGE2 - BDT Page Register 2 */ 5309 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) 5310 #define USB_BDTPAGE2_BDTBA_SHIFT (0U) 5311 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) 5312 5313 /*! @name BDTPAGE3 - BDT Page Register 3 */ 5314 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) 5315 #define USB_BDTPAGE3_BDTBA_SHIFT (0U) 5316 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) 5317 5318 /*! @name ENDPT - Endpoint Control register */ 5319 #define USB_ENDPT_EPHSHK_MASK (0x1U) 5320 #define USB_ENDPT_EPHSHK_SHIFT (0U) 5321 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) 5322 #define USB_ENDPT_EPSTALL_MASK (0x2U) 5323 #define USB_ENDPT_EPSTALL_SHIFT (1U) 5324 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) 5325 #define USB_ENDPT_EPTXEN_MASK (0x4U) 5326 #define USB_ENDPT_EPTXEN_SHIFT (2U) 5327 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) 5328 #define USB_ENDPT_EPRXEN_MASK (0x8U) 5329 #define USB_ENDPT_EPRXEN_SHIFT (3U) 5330 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) 5331 #define USB_ENDPT_EPCTLDIS_MASK (0x10U) 5332 #define USB_ENDPT_EPCTLDIS_SHIFT (4U) 5333 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) 5334 #define USB_ENDPT_RETRYDIS_MASK (0x40U) 5335 #define USB_ENDPT_RETRYDIS_SHIFT (6U) 5336 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) 5337 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) 5338 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) 5339 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) 5340 5341 /* The count of USB_ENDPT */ 5342 #define USB_ENDPT_COUNT (16U) 5343 5344 /*! @name USBCTRL - USB Control register */ 5345 #define USB_USBCTRL_PDE_MASK (0x40U) 5346 #define USB_USBCTRL_PDE_SHIFT (6U) 5347 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) 5348 #define USB_USBCTRL_SUSP_MASK (0x80U) 5349 #define USB_USBCTRL_SUSP_SHIFT (7U) 5350 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) 5351 5352 /*! @name OBSERVE - USB OTG Observe register */ 5353 #define USB_OBSERVE_DMPD_MASK (0x10U) 5354 #define USB_OBSERVE_DMPD_SHIFT (4U) 5355 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) 5356 #define USB_OBSERVE_DPPD_MASK (0x40U) 5357 #define USB_OBSERVE_DPPD_SHIFT (6U) 5358 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) 5359 #define USB_OBSERVE_DPPU_MASK (0x80U) 5360 #define USB_OBSERVE_DPPU_SHIFT (7U) 5361 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) 5362 5363 /*! @name CONTROL - USB OTG Control register */ 5364 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) 5365 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) 5366 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) 5367 5368 /*! @name USBTRC0 - USB Transceiver Control Register 0 */ 5369 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) 5370 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) 5371 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) 5372 #define USB_USBTRC0_SYNC_DET_MASK (0x2U) 5373 #define USB_USBTRC0_SYNC_DET_SHIFT (1U) 5374 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) 5375 #define USB_USBTRC0_USBRESMEN_MASK (0x20U) 5376 #define USB_USBTRC0_USBRESMEN_SHIFT (5U) 5377 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) 5378 #define USB_USBTRC0_USBRESET_MASK (0x80U) 5379 #define USB_USBTRC0_USBRESET_SHIFT (7U) 5380 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) 5381 5382 /*! @name USBFRMADJUST - Frame Adjust Register */ 5383 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) 5384 #define USB_USBFRMADJUST_ADJ_SHIFT (0U) 5385 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) 5386 5387 5388 /*! 5389 * @} 5390 */ /* end of group USB_Register_Masks */ 5391 5392 5393 /* USB - Peripheral instance base addresses */ 5394 /** Peripheral USB0 base address */ 5395 #define USB0_BASE (0x40072000u) 5396 /** Peripheral USB0 base pointer */ 5397 #define USB0 ((USB_Type *)USB0_BASE) 5398 /** Array initializer of USB peripheral base addresses */ 5399 #define USB_BASE_ADDRS { USB0_BASE } 5400 /** Array initializer of USB peripheral base pointers */ 5401 #define USB_BASE_PTRS { USB0 } 5402 /** Interrupt vectors for the USB peripheral type */ 5403 #define USB_IRQS { USB0_IRQn } 5404 5405 /*! 5406 * @} 5407 */ /* end of group USB_Peripheral_Access_Layer */ 5408 5409 5410 /* 5411 ** End of section using anonymous unions 5412 */ 5413 5414 #if defined(__ARMCC_VERSION) 5415 #pragma pop 5416 #elif defined(__CWCC__) 5417 #pragma pop 5418 #elif defined(__GNUC__) 5419 /* leave anonymous unions enabled */ 5420 #elif defined(__IAR_SYSTEMS_ICC__) 5421 #pragma language=default 5422 #else 5423 #error Not supported compiler type 5424 #endif 5425 5426 /*! 5427 * @} 5428 */ /* end of group Peripheral_access_layer */ 5429 5430 5431 /* ---------------------------------------------------------------------------- 5432 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 5433 ---------------------------------------------------------------------------- */ 5434 5435 /*! 5436 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 5437 * @{ 5438 */ 5439 5440 #if defined(__ARMCC_VERSION) 5441 #if (__ARMCC_VERSION >= 6010050) 5442 #pragma clang system_header 5443 #endif 5444 #elif defined(__IAR_SYSTEMS_ICC__) 5445 #pragma system_include 5446 #endif 5447 5448 /** 5449 * @brief Mask and left-shift a bit field value for use in a register bit range. 5450 * @param field Name of the register bit field. 5451 * @param value Value of the bit field. 5452 * @return Masked and shifted value. 5453 */ 5454 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 5455 /** 5456 * @brief Mask and right-shift a register value to extract a bit field value. 5457 * @param field Name of the register bit field. 5458 * @param value Value of the register. 5459 * @return Masked and shifted bit field value. 5460 */ 5461 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 5462 5463 /*! 5464 * @} 5465 */ /* end of group Bit_Field_Generic_Macros */ 5466 5467 5468 /* ---------------------------------------------------------------------------- 5469 -- SDK Compatibility 5470 ---------------------------------------------------------------------------- */ 5471 5472 /*! 5473 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 5474 * @{ 5475 */ 5476 5477 #define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated 5478 #define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated 5479 #define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated 5480 #define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated 5481 #define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated 5482 #define DMA_REQC0 This_symbol_has_been_deprecated 5483 #define DMA_REQC1 This_symbol_has_been_deprecated 5484 #define DMA_REQC2 This_symbol_has_been_deprecated 5485 #define DMA_REQC3 This_symbol_has_been_deprecated 5486 #define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK 5487 #define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT 5488 #define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK 5489 #define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT 5490 #define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0 5491 #define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated 5492 #define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated 5493 #define UART_C4_LBKDDMAS_MASK This_symbol_has_been_deprecated 5494 #define UART_C4_LBKDDMAS_SHIFT This_symbol_has_been_deprecated 5495 #define UART_C4_ILDMAS_MASK This_symbol_has_been_deprecated 5496 #define UART_C4_ILDMAS_SHIFT This_symbol_has_been_deprecated 5497 #define UART_C4_TCDMAS_MASK This_symbol_has_been_deprecated 5498 #define UART_C4_TCDMAS_SHIFT This_symbol_has_been_deprecated 5499 #define UARTLP_Type UART0_Type 5500 #define UARTLP_BDH_REG UART0_BDH_REG 5501 #define UARTLP_BDL_REG UART0_BDL_REG 5502 #define UARTLP_C1_REG UART0_C1_REG 5503 #define UARTLP_C2_REG UART0_C2_REG 5504 #define UARTLP_S1_REG UART0_S1_REG 5505 #define UARTLP_S2_REG UART0_S2_REG 5506 #define UARTLP_C3_REG UART0_C3_REG 5507 #define UARTLP_D_REG UART0_D_REG 5508 #define UARTLP_MA1_REG UART0_MA1_REG 5509 #define UARTLP_MA2_REG UART0_MA2_REG 5510 #define UARTLP_C4_REG UART0_C4_REG 5511 #define UARTLP_C5_REG UART0_C5_REG 5512 #define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK 5513 #define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT 5514 #define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x) 5515 #define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK 5516 #define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT 5517 #define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK 5518 #define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT 5519 #define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK 5520 #define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT 5521 #define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK 5522 #define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT 5523 #define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x) 5524 #define UARTLP_C1_PT_MASK UART0_C1_PT_MASK 5525 #define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT 5526 #define UARTLP_C1_PE_MASK UART0_C1_PE_MASK 5527 #define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT 5528 #define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK 5529 #define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT 5530 #define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK 5531 #define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT 5532 #define UARTLP_C1_M_MASK UART0_C1_M_MASK 5533 #define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT 5534 #define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK 5535 #define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT 5536 #define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK 5537 #define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT 5538 #define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK 5539 #define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT 5540 #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK 5541 #define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT 5542 #define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK 5543 #define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT 5544 #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK 5545 #define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT 5546 #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK 5547 #define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT 5548 #define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK 5549 #define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT 5550 #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK 5551 #define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT 5552 #define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK 5553 #define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT 5554 #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK 5555 #define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT 5556 #define UARTLP_S1_PF_MASK UART0_S1_PF_MASK 5557 #define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT 5558 #define UARTLP_S1_FE_MASK UART0_S1_FE_MASK 5559 #define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT 5560 #define UARTLP_S1_NF_MASK UART0_S1_NF_MASK 5561 #define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT 5562 #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK 5563 #define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT 5564 #define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK 5565 #define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT 5566 #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK 5567 #define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT 5568 #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK 5569 #define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT 5570 #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK 5571 #define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT 5572 #define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK 5573 #define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT 5574 #define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK 5575 #define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT 5576 #define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK 5577 #define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT 5578 #define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK 5579 #define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT 5580 #define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK 5581 #define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT 5582 #define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK 5583 #define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT 5584 #define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK 5585 #define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT 5586 #define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK 5587 #define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT 5588 #define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK 5589 #define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT 5590 #define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK 5591 #define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT 5592 #define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK 5593 #define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT 5594 #define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK 5595 #define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT 5596 #define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK 5597 #define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT 5598 #define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK 5599 #define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT 5600 #define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK 5601 #define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT 5602 #define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK 5603 #define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT 5604 #define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK 5605 #define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT 5606 #define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK 5607 #define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT 5608 #define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK 5609 #define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT 5610 #define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK 5611 #define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT 5612 #define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK 5613 #define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT 5614 #define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK 5615 #define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT 5616 #define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK 5617 #define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT 5618 #define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK 5619 #define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT 5620 #define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK 5621 #define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT 5622 #define UARTLP_MA1_MA(x) UART0_MA1_MA(x) 5623 #define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK 5624 #define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT 5625 #define UARTLP_MA2_MA(x) UART0_MA2_MA(x) 5626 #define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK 5627 #define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT 5628 #define UARTLP_C4_OSR(x) UART0_C4_OSR(x) 5629 #define UARTLP_C4_M10_MASK UART0_C4_M10_MASK 5630 #define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT 5631 #define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK 5632 #define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT 5633 #define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK 5634 #define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT 5635 #define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK 5636 #define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT 5637 #define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK 5638 #define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT 5639 #define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK 5640 #define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT 5641 #define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK 5642 #define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT 5643 #define NV_FOPT_EZPORT_DIS_MASK This_symbol_has_been_deprecated 5644 #define NV_FOPT_EZPORT_DIS_SHIFT This_symbol_has_been_deprecated 5645 #define FPTA_BASE FGPIOA_BASE 5646 #define FPTA FGPIOA 5647 #define FPTB_BASE FGPIOB_BASE 5648 #define FPTB FGPIOB 5649 #define FPTC_BASE FGPIOC_BASE 5650 #define FPTC FGPIOC 5651 #define FPTD_BASE FGPIOD_BASE 5652 #define FPTD FGPIOD 5653 #define FPTE_BASE FGPIOE_BASE 5654 #define FPTE FGPIOE 5655 #define PTA_BASE GPIOA_BASE 5656 #define PTA GPIOA 5657 #define PTB_BASE GPIOB_BASE 5658 #define PTB GPIOB 5659 #define PTC_BASE GPIOC_BASE 5660 #define PTC GPIOC 5661 #define PTD_BASE GPIOD_BASE 5662 #define PTD GPIOD 5663 #define PTE_BASE GPIOE_BASE 5664 #define PTE GPIOE 5665 #define LPTimer_IRQn LPTMR0_IRQn 5666 #define LPTimer_IRQHandler LPTMR0_IRQHandler 5667 #define LLW_IRQn LLWU_IRQn 5668 #define LLW_IRQHandler LLWU_IRQHandler 5669 5670 /*! 5671 * @} 5672 */ /* end of group SDK_Compatibility_Symbols */ 5673 5674 5675 #endif /* _MKL25Z4_H_ */ 5676 5677
